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[PATCH] Makefile: Allow overriding defconfig
by Paul Menzel 18 Mar '20

18 Mar '20

From: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri, 31 Jan 2014 13:53:58 -0800 Allow specifying a file instead of /dev/null for defconfig. BUG=none BRANCH=none TEST=emerge-panther chromeos-seabios works and produces usable SeaBIOS image Change-Id: I01d902eb9a6dff9ced7e3dd061aa33f831a64e8c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/185752 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/227448 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> --- Makefile | 3 +++ scripts/kconfig/Makefile | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5f7d537..b57b529 100644 --- a/Makefile +++ b/Makefile @@ -7,6 +7,9 @@ # Output directory OUT=out/ +# Default config (can be overriden) +KCONFIG_DEFCONFIG?=/dev/null + # Common command definitions export HOSTCC := $(CC) export CONFIG_SHELL := sh diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index 1c12936..a3fe942 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -96,7 +96,7 @@ savedefconfig: $(obj)/conf defconfig: $(obj)/conf @echo " Build default config" - $(Q)$< --defconfig=/dev/null $(Kconfig) + $(Q)$< --defconfig=$(KCONFIG_DEFCONFIG) $(Kconfig) %_defconfig: $(obj)/conf $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) -- 2.25.1

3 2

[PATCH 1/2] fw/coreboot: Log coreboot table entries
by Paul Menzel 17 Mar '20

17 Mar '20

If the log level is at least 5, print out the coreboot table entries to the console. This is useful for debugging. Relocating coreboot bios tables Looking at type 0x10 (start: 0x0, size 4096/0x1000) Looking at type 0x1 (start: 0x1000, size 651264/0x9f000) Looking at type 0x1 (start: 0xc0000, size 2146123776/0x7feb4000) Looking at type 0x10 (start: 0x7ff74000, size 573440/0x8c000) Copying SMBIOS entry point from 0x7ff74000 to 0x000f5700 Copying ACPI RSDP from 0x7ff75000 to 0x000f56e0 Looking at type 0x2 (start: 0xb0000000, size 268435456/0x10000000) Looking at type 0x1 (start: 0x100000000, size 2147483648/0x80000000) Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/fw/coreboot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index 7c0954b..96a4748 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -266,6 +266,8 @@ coreboot_platform_setup(void) int i, count = MEM_RANGE_COUNT(cbm); for (i=0; i<count; i++) { struct cb_memory_range *m = &cbm->map[i]; + dprintf(5, "Looking at type 0x%x (start: 0x%llx, size %llu/0x%llx)\n", + m->type, m->start, m->size, m->size); if (m->type == CB_MEM_TABLE) scan_tables(m->start, m->size); } -- 2.26.0.rc2

1 1

[RFC] [PATCH] fw/coreboot: Don't scan all of memory
by Paul Menzel 17 Mar '20

17 Mar '20

From: Raul E Rangel <rrangel(a)chromium.org> Date: Tue, 14 Jan 2020 14:19:00 -0700 There seems to be a mismatch between the ACPI table coreboot writes, and what SeaBIOS is scanning: SeaBIOS: Scanning: 0x00000000 : 0x00001000 Scanning: 0xade50000 : 0xb0000000 Coreboot: IMD ROOT 0. affff000 00001000 IMD SMALL 1. afffe000 00001000 FSP MEMORY 2. aeffe000 01000000 CONSOLE 3. aefde000 00020000 TIME STAMP 4. aefdd000 00000910 TSEG 5. adfdd000 01000000 RAMSTAGE 6. adede000 000ff000 REFCODE 7. ade8e000 00050000 ACPI GNVS 8. ade8d000 00001000 COREBOOT 9. ade85000 00008000 ACPI 10. ade61000 00024000 TPM2 TCGLOG11. ade51000 00010000 SMBIOS 12. ade50000 00000800 BUG=none TEST=Dali is able to boot Change-Id: I1db339f08d0754b836f84fe87cbf1139f27270e1 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/seabios/+… Reviewed-by: Martin Roth <martinroth(a)chromium.org> Commit-Queue: Martin Roth <martinroth(a)chromium.org> Tested-by: Martin Roth <martinroth(a)chromium.org> --- The real bug should be fixed here. src/fw/coreboot.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index 7c0954b..b95c680 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -243,10 +243,19 @@ void coreboot_debug_putc(char c) static void scan_tables(u32 start, u32 size) { + if (size > 0x100000) { + dprintf(5, "Size is too large: %d\n", size); + size = 0x100000; + } void *p = (void*)ALIGN(start, 16); void *end = (void*)start + size; - for (; p<end; p += 16) + dprintf(5, "Scanning: %p : %p\n", p, end); + for (; p<end; p += 16) { copy_table(p); + // dprintf(5, "."); + } + + dprintf(3, "\nDone Scanning\n"); } void @@ -266,9 +275,12 @@ coreboot_platform_setup(void) int i, count = MEM_RANGE_COUNT(cbm); for (i=0; i<count; i++) { struct cb_memory_range *m = &cbm->map[i]; + + dprintf(3, "Looking at type: %x\n", m->type); if (m->type == CB_MEM_TABLE) scan_tables(m->start, m->size); } + dprintf(3, "Done relocating coreboot bios tables\n"); find_acpi_features(); } -- 2.25.1

2 3

[PATCH] kbd: Add option for keyboard polling
by Paul Menzel 17 Mar '20

17 Mar '20

From: Marc Jones <marc.jones(a)se-eng.com> Date: Wed, 24 Sep 2014 15:14:41 -0600 Some devices don’t have legacy interrupt support, but still need to use a legacy keyboard. This patch adds a KBC check and manual call to the keyboard service if there is a key waiting in the KBC. BUG=chrome-os-partner:30836 BRANCH=None TEST=Build and boot Rambi SeaBIOS. Change-Id: I11033d29ec26b5a772588a0aa1a35678ab05a462 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: https://chromium-review.googlesource.com/219803 Reviewed-by: Mike Loptien <mike.loptien(a)se-eng.com> Tested-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/227501 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/Kconfig | 5 +++++ src/boot.c | 3 +++ src/kbd.c | 12 ++++++++++++ 3 files changed, 20 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 6606ce4..d389ede 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -440,6 +440,11 @@ menu "BIOS interfaces" default y help Support for int15c2 mouse calls. + config KBC_POLL + bool "Poll the keyboad controller for keys" + default n + help + Poll for keys when interrupts are not available. config S3_RESUME bool "S3 resume" diff --git a/src/boot.c b/src/boot.c index afeb36a..3beecee 100644 --- a/src/boot.c +++ b/src/boot.c @@ -631,7 +631,10 @@ get_keystroke_full(int msec) return get_raw_keystroke(); if (irqtimer_check(end)) return -1; + if (!CONFIG_KBC_POLL) yield_toirq(); + else + msleep(5); } } diff --git a/src/kbd.c b/src/kbd.c index 3f08d32..5726274 100644 --- a/src/kbd.c +++ b/src/kbd.c @@ -252,6 +252,18 @@ handle_16(struct bregs *regs) // XXX - set_leds should be called from irq handler set_leds(); + // If interrupts are not enabled do KBC polling. + // Check the KBC for a key on every keyboard service function (INT16). + // If interrupts are working the KBC status port should always be empty. + // (Yes, there is a race condition, but it is recoverable). + if (CONFIG_PS2PORT && CONFIG_KBC_POLL) { + u8 v = inb(PORT_PS2_STATUS); + if ((v & I8042_STR_OBF) && !(v & I8042_STR_AUXDATA)) { + v = inb(PORT_PS2_DATA); + process_key(v); + } + } + switch (regs->ah) { case 0x00: handle_1600(regs); break; case 0x01: handle_1601(regs); break; -- 2.25.1

3 2

[PATCH] kbd: Fix compilation with Chrome OS toolchain
by Paul Menzel 17 Mar '20

17 Mar '20

From: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue, 4 Nov 2014 16:16:46 -0800 gcc complains about using potentially unused variables. BUG=none BRANCH=none TEST=emerge-panther chromeos-seabios builds an image again Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I6c3d556a6519a5baa3a345e4dcb33b37b22db1b3 Reviewed-on: https://chromium-review.googlesource.com/227520 Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/kbd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/kbd.c b/src/kbd.c index 15e5ae7..3f08d32 100644 --- a/src/kbd.c +++ b/src/kbd.c @@ -162,7 +162,7 @@ handle_1609(struct bregs *regs) static void noinline handle_160a(struct bregs *regs) { - u8 param[2]; + u8 param[2] = { 0, 0 }; int ret = kbd_command(ATKBD_CMD_GETID, param); if (ret) { regs->bx = 0; -- 2.25.1

2 1

[PATCH] sdcard: Increase power-on timeout to 25 ms
by Paul Menzel 17 Mar '20

17 Mar '20

From: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri, 14 Dec 2018 01:20:31 -0600 This helps card detection on some Chromebooks. Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- Upstream from https://github.com/MrChromebox/SeaBIOS/ Matt, it’d be great if you could list the affected Chromebooks you know of. src/hw/sdcard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hw/sdcard.c b/src/hw/sdcard.c index 97517f4..2cd4e3d 100644 --- a/src/hw/sdcard.c +++ b/src/hw/sdcard.c @@ -128,7 +128,7 @@ struct sdhci_s { // SDHCI timeouts #define SDHCI_POWER_OFF_TIME 1 -#define SDHCI_POWER_ON_TIME 5 +#define SDHCI_POWER_ON_TIME 25 #define SDHCI_CLOCK_ON_TIME 1 // 74 clock cycles #define SDHCI_POWERUP_TIMEOUT 1000 #define SDHCI_PIO_TIMEOUT 1000 // XXX - this is just made up -- 2.25.1

3 2

[PATCH] Makefile: Use -mstack-alignment=4 instead of -mpreferred-stack-boundary=2 for clang
by Fangrui Song 17 Mar '20

17 Mar '20

( depends on https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/SWDV7M… "[PATCH] Makefile: Refactor cc-option" see linux/arch/x86/Makefile for a similar use case ) Signed-off-by: Fangrui Song <maskray(a)google.com> --- Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 7720db9..eae7ac0 100644 --- a/Makefile +++ b/Makefile @@ -59,7 +59,7 @@ CPPFLAGS = -P -MD -MT $@ COMMONCFLAGS := -I$(OUT) -Isrc -Os -MD -g \ -Wall -Wno-strict-aliasing -Wold-style-definition \ $(call cc-option,-Wtype-limits) \ - -m32 -march=i386 -mregparm=3 -mpreferred-stack-boundary=2 \ + -m32 -march=i386 -mregparm=3 \ -minline-all-stringops -fomit-frame-pointer \ -freg-struct-return -ffreestanding -fno-delete-null-pointer-checks \ -ffunction-sections -fdata-sections -fno-common -fno-merge-constants @@ -69,6 +69,7 @@ COMMONCFLAGS += $(call cc-option,-fno-stack-protector) COMMONCFLAGS += $(call cc-option,-fno-stack-protector-all) COMMONCFLAGS += $(call cc-option,-fstack-check=no) COMMONCFLAGS += $(call cc-option,-Wno-address-of-packed-member) +COMMONCFLAGS += $(call cc-option,-mpreferred-stack-boundary=2,-mstack-alignment=4) COMMA := , CFLAGS32FLAT := $(COMMONCFLAGS) -DMODE16=0 -DMODESEGMENT=0 -- 2.25.1

4 6

[PATCH v2 1/4] timer: add tsctimer_setfreq()
by Gerd Hoffmann 16 Mar '20

16 Mar '20

Add function to set tsc frequency directly, without calibration. Also tweak timer setup functions a bit: skip setup in case TimerPort has not the default value any more, i.e. another timer has been setup already. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/util.h | 1 + src/hw/timer.c | 26 +++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/util.h b/src/util.h index d96db788d1b8..94592a2d2e8d 100644 --- a/src/util.h +++ b/src/util.h @@ -171,6 +171,7 @@ void sdcard_setup(void); // hw/timer.c void timer_setup(void); void pmtimer_setup(u16 ioport); +void tsctimer_setfreq(u32 khz, const char *src); u32 timer_calc(u32 msecs); u32 timer_calc_usec(u32 usecs); int timer_check(u32 end); diff --git a/src/hw/timer.c b/src/hw/timer.c index bdcb3bfca211..56bb289a4adc 100644 --- a/src/hw/timer.c +++ b/src/hw/timer.c @@ -101,8 +101,10 @@ tsctimer_setup(void) void timer_setup(void) { - if (!CONFIG_TSC_TIMER || (CONFIG_PMTIMER && TimerPort != PORT_PIT_COUNTER0)) + if (!CONFIG_TSC_TIMER) return; + if (TimerPort != PORT_PIT_COUNTER0) + return; // have timer already // Check if CPU has a timestamp counter u32 eax, ebx, ecx, edx, cpuid_features = 0; @@ -113,11 +115,33 @@ timer_setup(void) tsctimer_setup(); } +void +tsctimer_setfreq(u32 khz, const char *src) +{ + if (!CONFIG_TSC_TIMER) + return; + if (TimerPort != PORT_PIT_COUNTER0) + return; // have timer already + + TimerKHz = khz; + ShiftTSC = 0; + while (TimerKHz >= 6000) { + ShiftTSC++; + TimerKHz = (TimerKHz + 1) >> 1; + } + TimerPort = 0; + + dprintf(1, "CPU Mhz=%u (%s)\n", (TimerKHz << ShiftTSC) / 1000, src); +} + void pmtimer_setup(u16 ioport) { if (!CONFIG_PMTIMER) return; + if (TimerPort != PORT_PIT_COUNTER0) + return; // have timer already + dprintf(1, "Using pmtimer, ioport 0x%x\n", ioport); TimerPort = ioport; TimerKHz = DIV_ROUND_UP(PMTIMER_HZ, 1000); -- 2.18.2

2 5

[PATCH] Makefile: Delete compiler driver option -nopie
by Fangrui Song 16 Mar '20

16 Mar '20

(This does no harm because we use LD directly.) -nopie is a typo. The actual option is -no-pie. CFLAGS does not need to include a link option. Signed-off-by: Fangrui Song <maskray(a)google.com> --- Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/Makefile b/Makefile index 8d087af..1400bf2 100644 --- a/Makefile +++ b/Makefile @@ -63,7 +63,6 @@ COMMONCFLAGS := -I$(OUT) -Isrc -Os -MD -g \ -minline-all-stringops -fomit-frame-pointer \ -freg-struct-return -ffreestanding -fno-delete-null-pointer-checks \ -ffunction-sections -fdata-sections -fno-common -fno-merge-constants -COMMONCFLAGS += $(call cc-option,-nopie) COMMONCFLAGS += $(call cc-option,-fno-pie) COMMONCFLAGS += $(call cc-option,-fno-stack-protector) COMMONCFLAGS += $(call cc-option,-fno-stack-protector-all) -- 2.25.1

1 0

[PATCH] Makefile: Change ET_EXEC to ET_REL so that lld can link bios.bin.elf
by Fangrui Song 16 Mar '20

16 Mar '20

( With https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CJR7WU… https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/GUYWC4… and this patch, I am able to link bios.bin.elf with lld 7 (a somewhat old version of lld. FreeBSD 12 uses lld 8 I considered an lld patch (https://reviews.llvm.org/D76174) but I now think it is probably not a good idea. In almost all circumstances this is an error. See Peter Smith's comment. It is just that seabios has a very particular use case which makes it work.) bios.bin.elf uses an extremely rare feature of GNU ld: an ET_EXEC can be linked as if it were an ET_REL. lld is rigid and will reject this use case. With this patch, I can link bios.bin.elf with lld 7. Signed-off-by: Fangrui Song <maskray(a)google.com> --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 66b3eab..8d087af 100644 --- a/Makefile +++ b/Makefile @@ -181,11 +181,11 @@ $(OUT)romlayout32seg.lds $(OUT)romlayout32flat.lds $(OUT)code32flat.o $(OUT)code $(OUT)rom16.o: $(OUT)code16.o $(OUT)romlayout16.lds @echo " Linking $@" - $(Q)$(LD) -T $(OUT)romlayout16.lds $< -o $@ + $(Q)$(LD) -T $(OUT)romlayout16.lds $< -o $@ && printf '\1' | dd of=$@ conv=notrunc bs=1 seek=16 # Change ET_EXEC to ET_REL $(OUT)rom32seg.o: $(OUT)code32seg.o $(OUT)romlayout32seg.lds @echo " Linking $@" - $(Q)$(LD) -T $(OUT)romlayout32seg.lds $< -o $@ + $(Q)$(LD) -T $(OUT)romlayout32seg.lds $< -o $@ && printf '\1' | dd of=$@ conv=notrunc bs=1 seek=16 # Change ET_EXEC to ET_REL $(OUT)bios.bin.elf: $(OUT)rom16.strip.o $(OUT)rom32seg.strip.o $(OUT)code32flat.o $(OUT)romlayout32flat.lds @echo " Linking $@" -- 2.25.1

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