SeaBIOS

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[PATCH] Remove dev-i440fx.c/h - move code closer to its callers.
by Kevin O'Connor 19 Jun '11

19 Jun '11

It's easier to understand the code when it is in the same file as its callers. --- Makefile | 2 +- src/acpi.c | 15 ++++++- src/dev-i440fx.c | 116 ------------------------------------------------------ src/dev-i440fx.h | 14 ------ src/pciinit.c | 43 +++++++++++++++++++- src/shadow.c | 29 +++++++++---- src/smm.c | 36 +++++++++++++++- src/util.h | 7 --- 8 files changed, 109 insertions(+), 153 deletions(-) delete mode 100644 src/dev-i440fx.c delete mode 100644 src/dev-i440fx.h diff --git a/Makefile b/Makefile index 05bcee3..a96c89d 100644 --- a/Makefile +++ b/Makefile @@ -19,7 +19,7 @@ SRCBOTH=misc.c pmm.c stacks.c output.c util.c block.c floppy.c ata.c mouse.c \ SRC16=$(SRCBOTH) system.c disk.c font.c SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ - lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c \ + lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c \ pci_region.c biostables.c xen.c SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c diff --git a/src/acpi.c b/src/acpi.c index 6428d9c..584e557 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -12,7 +12,6 @@ #include "pci_ids.h" // PCI_VENDOR_ID_INTEL #include "pci_regs.h" // PCI_INTERRUPT_LINE #include "paravirt.h" -#include "dev-i440fx.h" // piix4_fadt_init /****************************************************/ /* ACPI tables init */ @@ -213,6 +212,20 @@ build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev) h->checksum -= checksum(h, len); } +#define PIIX4_ACPI_ENABLE 0xf1 +#define PIIX4_ACPI_DISABLE 0xf0 +#define PIIX4_GPE0_BLK 0xafe0 +#define PIIX4_GPE0_BLK_LEN 4 + +static void piix4_fadt_init(u16 bdf, void *arg) +{ + struct fadt_descriptor_rev1 *fadt = arg; + fadt->acpi_enable = PIIX4_ACPI_ENABLE; + fadt->acpi_disable = PIIX4_ACPI_DISABLE; + fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK); + fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN; +} + static const struct pci_device_id fadt_init_tbl[] = { /* PIIX4 Power Management device (for ACPI) */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, diff --git a/src/dev-i440fx.c b/src/dev-i440fx.c deleted file mode 100644 index 346f6d0..0000000 --- a/src/dev-i440fx.c +++ /dev/null @@ -1,116 +0,0 @@ -// initialization function which are specific to i440fx chipset -// -// Copyright (C) 2008 Kevin O'Connor <kevin(a)koconnor.net> -// Copyright (C) 2006 Fabrice Bellard -// -// Copyright (C) 2010 Isaku Yamahata <yamahata at valinux co jp> -// Split out from pciinit.c -// -// This file may be distributed under the terms of the GNU LGPLv3 license. -// - -#include "config.h" // CONFIG_DEBUG_LEVEL -#include "util.h" // dprintf -#include "ioport.h" // outb -#include "pci.h" // pci_config_writeb -#include "pci_ids.h" -#include "pci_regs.h" // PCI_INTERRUPT_LINE -#include "acpi.h" -#include "dev-i440fx.h" - -#define I440FX_PAM0 0x59 - -void i440fx_bios_make_writable(u16 bdf, void *arg) -{ - make_bios_writable_intel(bdf, I440FX_PAM0); -} - -void i440fx_bios_make_readonly(u16 bdf, void *arg) -{ - make_bios_readonly_intel(bdf, I440FX_PAM0); -} - -/* PIIX3/PIIX4 PCI to ISA bridge */ -void piix_isa_bridge_init(u16 bdf, void *arg) -{ - int i, irq; - u8 elcr[2]; - - elcr[0] = 0x00; - elcr[1] = 0x00; - for (i = 0; i < 4; i++) { - irq = pci_irqs[i]; - /* set to trigger level */ - elcr[irq >> 3] |= (1 << (irq & 7)); - /* activate irq remapping in PIIX */ - pci_config_writeb(bdf, 0x60 + i, irq); - } - outb(elcr[0], 0x4d0); - outb(elcr[1], 0x4d1); - dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]); -} - -/* PIIX3/PIIX4 IDE */ -void piix_ide_init(u16 bdf, void *arg) -{ - pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0 - pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1 - pci_bios_allocate_regions(bdf, NULL); -} - -/* PIIX4 Power Management device (for ACPI) */ -void piix4_pm_init(u16 bdf, void *arg) -{ - // acpi sci is hardwired to 9 - pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9); - - pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1); - pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */ - pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1); - pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */ -} - -#define PIIX4_ACPI_ENABLE 0xf1 -#define PIIX4_ACPI_DISABLE 0xf0 -#define PIIX4_GPE0_BLK 0xafe0 -#define PIIX4_GPE0_BLK_LEN 4 - -void piix4_fadt_init(u16 bdf, void *arg) -{ - struct fadt_descriptor_rev1 *fadt = arg; - fadt->acpi_enable = PIIX4_ACPI_ENABLE; - fadt->acpi_disable = PIIX4_ACPI_DISABLE; - fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK); - fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN; -} - -#define I440FX_SMRAM 0x72 -#define PIIX_DEVACTB 0x58 -#define PIIX_APMC_EN (1 << 25) - -// This code is hardcoded for PIIX4 Power Management device. -void piix4_apmc_smm_init(u16 bdf, void *arg) -{ - int i440_bdf = pci_find_device(PCI_VENDOR_ID_INTEL - , PCI_DEVICE_ID_INTEL_82441); - if (i440_bdf < 0) - return; - - /* check if SMM init is already done */ - u32 value = pci_config_readl(bdf, PIIX_DEVACTB); - if (value & PIIX_APMC_EN) - return; - - /* enable the SMM memory window */ - pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48); - - smm_save_and_copy(); - - /* enable SMI generation when writing to the APMC register */ - pci_config_writel(bdf, PIIX_DEVACTB, value | PIIX_APMC_EN); - - smm_relocate_and_restore(); - - /* close the SMM memory window and enable normal SMM */ - pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08); -} diff --git a/src/dev-i440fx.h b/src/dev-i440fx.h deleted file mode 100644 index ab5a4d1..0000000 --- a/src/dev-i440fx.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __I440FX_H -#define __I440FX_H - -#include "types.h" // u16 - -void i440fx_bios_make_writable(u16 bdf, void *arg); -void i440fx_bios_make_readonly(u16 bdf, void *arg); -void piix_isa_bridge_init(u16 bdf, void *arg); -void piix_ide_init(u16 bdf, void *arg); -void piix4_pm_init(u16 bdf, void *arg); -void piix4_fadt_init(u16 bdf, void *arg); -void piix4_apmc_smm_init(u16 bdf, void *arg); - -#endif // __I440FX_H diff --git a/src/pciinit.c b/src/pciinit.c index 0bd9b72..ca0d182 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -10,7 +10,6 @@ #include "biosvar.h" // GET_EBDA #include "pci_ids.h" // PCI_VENDOR_ID_INTEL #include "pci_regs.h" // PCI_COMMAND -#include "dev-i440fx.h" #include "xen.h" // usingXen #define PCI_ROM_SLOT 6 @@ -115,7 +114,7 @@ static int pci_bios_allocate_region(u16 bdf, int region_num) return is_64bit; } -void pci_bios_allocate_regions(u16 bdf, void *arg) +static void pci_bios_allocate_regions(u16 bdf, void *arg) { int i; for (i = 0; i < PCI_NUM_REGIONS; i++) { @@ -135,6 +134,26 @@ static int pci_slot_get_pirq(u16 bdf, int irq_num) return (irq_num + slot_addend) & 3; } +/* PIIX3/PIIX4 PCI to ISA bridge */ +static void piix_isa_bridge_init(u16 bdf, void *arg) +{ + int i, irq; + u8 elcr[2]; + + elcr[0] = 0x00; + elcr[1] = 0x00; + for (i = 0; i < 4; i++) { + irq = pci_irqs[i]; + /* set to trigger level */ + elcr[irq >> 3] |= (1 << (irq & 7)); + /* activate irq remapping in PIIX */ + pci_config_writeb(bdf, 0x60 + i, irq); + } + outb(elcr[0], 0x4d0); + outb(elcr[1], 0x4d1); + dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]); +} + static const struct pci_device_id pci_isa_bridge_tbl[] = { /* PIIX3/PIIX4 PCI to ISA bridge */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, @@ -245,6 +264,14 @@ static void storage_ide_init(u16 bdf, void *arg) pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE); } +/* PIIX3/PIIX4 IDE */ +static void piix_ide_init(u16 bdf, void *arg) +{ + pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0 + pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1 + pci_bios_allocate_regions(bdf, NULL); +} + static void pic_ibm_init(u16 bdf, void *arg) { /* PIC, IBM, MPIC & MPIC2 */ @@ -286,6 +313,18 @@ static const struct pci_device_id pci_class_tbl[] = { PCI_DEVICE_END, }; +/* PIIX4 Power Management device (for ACPI) */ +static void piix4_pm_init(u16 bdf, void *arg) +{ + // acpi sci is hardwired to 9 + pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9); + + pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1); + pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */ + pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1); + pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */ +} + static const struct pci_device_id pci_device_tbl[] = { /* PIIX4 Power Management device (for ACPI) */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, diff --git a/src/shadow.c b/src/shadow.c index cb39ddf..169decf 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -9,12 +9,13 @@ #include "pci.h" // pci_config_writeb #include "config.h" // CONFIG_* #include "pci_ids.h" // PCI_VENDOR_ID_INTEL -#include "dev-i440fx.h" #include "xen.h" // usingXen // On the emulators, the bios at 0xf0000 is also at 0xffff0000 #define BIOS_SRC_OFFSET 0xfff00000 +#define I440FX_PAM0 0x59 + // Enable shadowing and copy bios. static void __make_bios_writable_intel(u16 bdf, u32 pam0) @@ -52,7 +53,7 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) , code32flat_end - code32flat_start); } -void +static void make_bios_writable_intel(u16 bdf, u32 pam0) { int reg = pci_config_readb(bdf, pam0); @@ -70,7 +71,7 @@ make_bios_writable_intel(u16 bdf, u32 pam0) __make_bios_writable_intel(bdf, pam0); } -void +static void make_bios_readonly_intel(u16 bdf, u32 pam0) { // Flush any pending writes before locking memory. @@ -93,12 +94,28 @@ make_bios_readonly_intel(u16 bdf, u32 pam0) pci_config_writeb(bdf, pam0, 0x10); } +static void i440fx_bios_make_writable(u16 bdf, void *arg) +{ + make_bios_writable_intel(bdf, I440FX_PAM0); +} + +static void i440fx_bios_make_readonly(u16 bdf, void *arg) +{ + make_bios_readonly_intel(bdf, I440FX_PAM0); +} + static const struct pci_device_id dram_controller_make_writable_tbl[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, i440fx_bios_make_writable), PCI_DEVICE_END }; +static const struct pci_device_id dram_controller_make_readonly_tbl[] = { + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, + i440fx_bios_make_readonly), + PCI_DEVICE_END +}; + // Make the 0xc0000-0x100000 area read/writable. void make_bios_writable(void) @@ -118,12 +135,6 @@ make_bios_writable(void) } } -static const struct pci_device_id dram_controller_make_readonly_tbl[] = { - PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, - i440fx_bios_make_readonly), - PCI_DEVICE_END -}; - // Make the BIOS code segment area (0xf0000) read-only. void make_bios_readonly(void) diff --git a/src/smm.c b/src/smm.c index 7e52892..9db02d7 100644 --- a/src/smm.c +++ b/src/smm.c @@ -10,7 +10,6 @@ #include "config.h" // CONFIG_* #include "ioport.h" // outb #include "pci_ids.h" // PCI_VENDOR_ID_INTEL -#include "dev-i440fx.h" ASM32FLAT( ".global smm_relocation_start\n" @@ -73,7 +72,7 @@ ASM32FLAT( extern u8 smm_relocation_start, smm_relocation_end; extern u8 smm_code_start, smm_code_end; -void +static void smm_save_and_copy(void) { /* save original memory content */ @@ -84,7 +83,7 @@ smm_save_and_copy(void) &smm_relocation_end - &smm_relocation_start); } -void +static void smm_relocate_and_restore(void) { /* init APM status port */ @@ -106,6 +105,37 @@ smm_relocate_and_restore(void) wbinvd(); } +#define I440FX_SMRAM 0x72 +#define PIIX_DEVACTB 0x58 +#define PIIX_APMC_EN (1 << 25) + +// This code is hardcoded for PIIX4 Power Management device. +static void piix4_apmc_smm_init(u16 bdf, void *arg) +{ + int i440_bdf = pci_find_device(PCI_VENDOR_ID_INTEL + , PCI_DEVICE_ID_INTEL_82441); + if (i440_bdf < 0) + return; + + /* check if SMM init is already done */ + u32 value = pci_config_readl(bdf, PIIX_DEVACTB); + if (value & PIIX_APMC_EN) + return; + + /* enable the SMM memory window */ + pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48); + + smm_save_and_copy(); + + /* enable SMI generation when writing to the APMC register */ + pci_config_writel(bdf, PIIX_DEVACTB, value | PIIX_APMC_EN); + + smm_relocate_and_restore(); + + /* close the SMM memory window and enable normal SMM */ + pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08); +} + static const struct pci_device_id smm_init_tbl[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, piix4_apmc_smm_init), diff --git a/src/util.h b/src/util.h index 00433e2..7034d43 100644 --- a/src/util.h +++ b/src/util.h @@ -342,14 +342,8 @@ void bios32_setup(void); // shadow.c void make_bios_writable(void); void make_bios_readonly(void); -void make_bios_writable_intel(u16 bdf, u32 pam0); -void make_bios_readonly_intel(u16 bdf, u32 pam0); void qemu_prep_reset(void); -// smm.c -void smm_save_and_copy(void); -void smm_relocate_and_restore(void); - // pci_region.c // region allocator. pci region allocates the requested region // sequentially with overflow check. @@ -381,7 +375,6 @@ u32 pci_region_size(const struct pci_region *r); // pciinit.c extern const u8 pci_irqs[4]; -void pci_bios_allocate_regions(u16 bdf, void *arg); void pci_setup(void); // smm.c -- 1.7.4.4

1 0

[PATCH] support piix PAM registers in KVM
by Gleb Natapov 19 Jun '11

19 Jun '11

Without this BIOS fails to remap 0xf0000 memory from ROM to RAM so writes to F-segment modify ROM content instead of memory copy. Since QEMU does not reloads ROMs during reset on next boot modified copy of BIOS is used. Signed-off-by: Gleb Natapov <gleb(a)redhat.com> diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 933ad86..0bf435d 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -99,10 +99,6 @@ static void i440fx_update_memory_mappings(PCII440FXState *d) int i, r; uint32_t smram, addr; - if (kvm_enabled()) { - /* FIXME: Support remappings and protection changes. */ - return; - } update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3); for(i = 0; i < 12; i++) { r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3; -- Gleb.

5 13

[PATCH] Enhance seabios splash picture showing ability
by Wayne Xia 18 Jun '11

18 Jun '11

Signed-off-by: Wayne Xia <xiawenc(a)linux.vnet.ibm.com> --- Makefile | 4 +- src/bmp.c | 71 +++++++++++++++++++++++++++++++++ src/bmp.h | 55 ++++++++++++++++++++++++++ src/boot.c | 43 ++++++++++++++++++-- src/bootsplash.c | 114 ++++++++++++++++++++++++++++++++++++++++++------------ 5 files changed, 255 insertions(+), 32 deletions(-) create mode 100644 src/bmp.c create mode 100644 src/bmp.h diff --git a/Makefile b/Makefile index d17f85a..214fe80 100644 --- a/Makefile +++ b/Makefile @@ -15,12 +15,12 @@ SRCBOTH=misc.c pmm.c stacks.c output.c util.c block.c floppy.c ata.c mouse.c \ kbd.c pci.c serial.c clock.c pic.c cdrom.c ps2port.c smp.c resume.c \ pnpbios.c pirtable.c vgahooks.c ramdisk.c pcibios.c blockcmd.c \ usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c \ - virtio-ring.c virtio-pci.c virtio-blk.c apm.c ahci.c + virtio-ring.c virtio-pci.c virtio-blk.c apm.c ahci.c bmp.c SRC16=$(SRCBOTH) system.c disk.c font.c SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c \ - pci_region.c + pci_region.c bmp.c SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c cc-option = $(shell if test -z "`$(1) $(2) -S -o /dev/null -xc \ diff --git a/src/bmp.c b/src/bmp.c new file mode 100644 index 0000000..db91dbe --- /dev/null +++ b/src/bmp.c @@ -0,0 +1,71 @@ +/* +* Basic BMP data process functions. +* Could used to adjust pixel data format, get infomation, etc. +* +* Copyright (C) 2011 Wayne Xia <xiawenc(a)cn.ibm.com> +* +* This work is licensed under the terms of the GNU GPL, version 2 or later. +*/ + +#include "bmp.h" + +void bmp_data_format_proc_24bpp(u8 *src, u8 *dest, int width, int height, + int bytes_per_line_src, int bytes_per_line_dest, u8 switch_flag) +{ + int cy = height; + u8 *pd, *ps, *pd_valid, *ps_lastline; + u8 t; + u8 rgb_switch_flag = switch_flag & SWITCH_RGB; + u8 line_switch_flag = switch_flag & SWITCH_LINE; + while (cy > 0) { + ps = bytes_per_line_src*cy + src - 1; + if (line_switch_flag) { + pd = bytes_per_line_dest * (height - cy + 1) + dest - 1; + } else { + pd = bytes_per_line_dest * cy + dest - 1; + } + ps_lastline = ps-bytes_per_line_src; + pd_valid = pd - (bytes_per_line_dest - bytes_per_line_src); + while (pd > pd_valid) { + *pd = 0; + pd--; + } + while (ps > ps_lastline) { + if (rgb_switch_flag) { + t = *ps; + *ps = *(ps-2); + *(ps-2) = t; + } + *(pd--) = *(ps--); + *(pd--) = *(ps--); + *(pd--) = *(ps--); + } + cy--; + } +} + +int bmp_get_info(u8 *data, int data_size, int *width_p, int *height_p, + int *bpp_p, int *offset_p) +{ + if (data_size < 54) { + return 1; + } + + u16 bmp_filehead = bmp_load2byte(data + 0); + if (bmp_filehead != 0x4d42) { + return 2; + } + u32 bmp_recordsize = bmp_load4byte(data + 2); + if (bmp_recordsize != data_size) { + return 3; + } + u32 bmp_dataoffset = bmp_load4byte(data + 10); + u32 bmp_width = bmp_load4byte(data + 18); + u32 bmp_height = bmp_load4byte(data + 22); + u32 bmp_bpp = bmp_load2byte(data + 28); + *width_p = bmp_width; + *height_p = bmp_height; + *bpp_p = bmp_bpp; + *offset_p = bmp_dataoffset; + return 0; +} diff --git a/src/bmp.h b/src/bmp.h new file mode 100644 index 0000000..ea0258b --- /dev/null +++ b/src/bmp.h @@ -0,0 +1,55 @@ +#ifndef BMP_H +#define BMP_H +#include "types.h" + +#define WIDTHBYTES(bits) (((bits)+31)/32*4) + +typedef u8 BYTE; +typedef u32 BYTE4; + + +typedef struct tagBITMAPFILEHEADER { +BYTE bfType[2]; +BYTE bfSize[4]; +BYTE bfReserved1[2]; +BYTE bfReserved2[2]; +BYTE bfOffBits[4]; +} BITMAPFILEHEADER, tagBITMAPFILEHEADER; + +typedef struct tagBITMAPINFOHEADER { +BYTE biSize[4]; +BYTE biWidth[4]; +BYTE biHeight[4]; +BYTE biPlanes[2]; +BYTE biBitCount[2]; +BYTE biCompression[4]; +BYTE biSizeImage[4]; +BYTE biXPelsPerMeter[4]; +BYTE biYPelsPerMeter[4]; +BYTE biClrUsed[4]; +BYTE biClrImportant[4]; +} BITMAPINFOHEADER, tagBITMAPINFOHEADER; + +typedef struct tagRGBQUAD { +BYTE rgbBlue; +BYTE rgbGreen; +BYTE rgbRed; +BYTE rgbReserved; +} RGBQUAD, tagRGBQUAD; + +#define bmp_load4byte(addr) ((addr)[0] + ((addr)[1]<<8) \ + + ((addr)[2]<<16) + ((addr)[3]<<24)) +#define bmp_load2byte(addr) ((addr)[0] + ((addr)[1]<<8)) + +#define SWITCH_RGB 0x01 +#define SWITCH_LINE 0x02 + +/* src can be equal to dest, if not need to switch the lines from bottom to top, +bytes_per_line_src must be less or eqaul than bytes_per_line_dest */ +void bmp_data_format_proc_24bpp(u8 *src, u8 *dest, int width, int height, + int bytes_per_line_src, int bytes_per_line_dest, u8 switch_flag); + +/* retrieve basic infomation of bmp file */ +int bmp_get_info(u8 *data, int data_size, int *width_p, int *height_p, + int *bpp_p, int *offset_p); +#endif diff --git a/src/boot.c b/src/boot.c index 9a67916..e1e3db4 100644 --- a/src/boot.c +++ b/src/boot.c @@ -372,23 +372,56 @@ boot_add_cbfs(void *data, const char *desc, int prio) static void interactive_bootmenu(void) { - if (! CONFIG_BOOTMENU || ! qemu_cfg_show_boot_menu()) + int filecfg_size; + u8 *filecfg_p = romfile_loadfile("bootsplash.cfg", &filecfg_size); + u8 showflag_normal; + u16 splash_time; + + if (filecfg_p != NULL && filecfg_size >= 4) { + showflag_normal = *filecfg_p; + splash_time = *(filecfg_p+2)+(*(filecfg_p+3)<<8); /* little endian */ + free(filecfg_p); + } else { + showflag_normal = 0; + splash_time = CONFIG_BOOTMENU_WAIT; + } + + /* the user do not want to show the menu, so normally bootup */ + if (!qemu_cfg_show_boot_menu()) { + if (showflag_normal) { + while (get_keystroke(0) >= 0) { + ; + } + enable_bootsplash(); + get_keystroke(splash_time); + disable_bootsplash(); + } return; + } else { + /* user want to show menu, check the if the bios config allow it */ + if (!CONFIG_BOOTMENU) { + return; + } + } + - while (get_keystroke(0) >= 0) + while (get_keystroke(0) >= 0) { ; + } printf("Press F12 for boot menu.\n\n"); enable_bootsplash(); - int scan_code = get_keystroke(CONFIG_BOOTMENU_WAIT); + int scan_code = get_keystroke(splash_time); disable_bootsplash(); - if (scan_code != 0x86) + if (scan_code != 0x86) { /* not F12 */ return; + } - while (get_keystroke(0) >= 0) + while (get_keystroke(0) >= 0) { ; + } printf("Select boot device:\n\n"); wait_threads(); diff --git a/src/bootsplash.c b/src/bootsplash.c index cf1a603..05f88c1 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -12,7 +12,7 @@ #include "jpeg.h" // splash #include "biosvar.h" // SET_EBDA #include "paravirt.h" // romfile_find - +#include "bmp.h" /**************************************************************** * VESA structures @@ -109,7 +109,7 @@ enable_vga_console(void) static int find_videomode(struct vesa_info *vesa_info, struct vesa_mode_info *mode_info - , int width, int height) + , int width, int height, int bpp_req) { dprintf(3, "Finding vesa mode with dimensions %d/%d\n", width, height); u16 *videomodes = SEGOFF_TO_FLATPTR(vesa_info->video_mode_ptr); @@ -135,8 +135,15 @@ find_videomode(struct vesa_info *vesa_info, struct vesa_mode_info *mode_info || mode_info->y_resolution != height) continue; u8 depth = mode_info->bits_per_pixel; - if (depth != 16 && depth != 24 && depth != 32) - continue; + if (bpp_req == 0) { + if (depth != 16 && depth != 24 && depth != 32) { + continue; + } + } else { + if (depth != bpp_req) { + continue; + } + } return videomode; } } @@ -146,15 +153,24 @@ static int BootsplashActive; void enable_bootsplash(void) { - if (!CONFIG_BOOTSPLASH) + if (!CONFIG_BOOTSPLASH) { return; + } dprintf(3, "Checking for bootsplash\n"); + u8 type = 0; /* 0 means jpg, 1 means bmp, default is 0=jpg */ int filesize; u8 *filedata = romfile_loadfile("bootsplash.jpg", &filesize); - if (!filedata) - return; + if (!filedata) { + filedata = romfile_loadfile("bootsplash.bmp", &filesize); + if (!filedata) { + return; + } + type = 1; + } + dprintf(3, "start showing bootsplash\n"); - u8 *picture = NULL; + u8 *picture = NULL; /* data buff used to be flushded to the video buff */ + u8 *picture_post = NULL; /* another buff, used to do some post process */ struct vesa_info *vesa_info = malloc_tmplow(sizeof(*vesa_info)); struct vesa_mode_info *mode_info = malloc_tmplow(sizeof(*mode_info)); struct jpeg_decdata *jpeg = jpeg_alloc(); @@ -184,20 +200,45 @@ enable_bootsplash(void) vesa_info->vesa_version>>8, vesa_info->vesa_version&0xff, vendor, product); - // Parse jpeg and get image size. - dprintf(5, "Decoding bootsplash.jpg\n"); - int ret = jpeg_decode(jpeg, filedata); - if (ret) { - dprintf(1, "jpeg_decode failed with return code %d...\n", ret); - goto done; + int ret, width, height; + int bpp_require = 0; + int data_offset = 0; + u8 post_flag = 0; + if (type == 0) { + /* Parse jpeg and get image size. */ + dprintf(5, "Decoding bootsplash.jpg\n"); + ret = jpeg_decode(jpeg, filedata); + if (ret) { + dprintf(1, "jpeg_decode failed with return code %d...\n", ret); + goto done; + } + jpeg_get_size(jpeg, &width, &height); + bpp_require = 24;/* for better vision effect, use 24 bpp mode */ + } else { + /* Parse jpeg and get image size. */ + dprintf(5, "retrieve information of bootsplash.bmp file\n"); + int bpp_src; + ret = bmp_get_info(filedata, filesize, &width, &height, + &bpp_src, &data_offset); + if (ret) { + dprintf(1, "retrieve bmp info failed with ret code %d...\n", ret); + goto done; + } + if (bpp_src != 24) { + dprintf(1, "only support 24bpp, now the bpp is %d...\n", bpp_src); + goto done; + } + bpp_require = 24; } - int width, height; - jpeg_get_size(jpeg, &width, &height); // Try to find a graphics mode with the corresponding dimensions. - int videomode = find_videomode(vesa_info, mode_info, width, height); - if (videomode < 0) + int videomode = find_videomode(vesa_info, mode_info, width, height, + bpp_require); + if (videomode < 0) { + dprintf(1, "failed to find a videomode with %dx%d %dbpp (0=any).\n", + width, height, bpp_require); goto done; + } void *framebuffer = mode_info->phys_base_ptr; int depth = mode_info->bits_per_pixel; dprintf(3, "mode: %04x\n", videomode); @@ -206,17 +247,40 @@ enable_bootsplash(void) dprintf(3, "bits per pixel: %d\n", depth); // Allocate space for image and decompress it. - int imagesize = width * height * (depth / 8); + int imagesize = height * mode_info->bytes_per_scanline; picture = malloc_tmphigh(imagesize); if (!picture) { warn_noalloc(); goto done; } - dprintf(5, "Decompressing bootsplash.jpg\n"); - ret = jpeg_show(jpeg, picture, width, height, depth); - if (ret) { - dprintf(1, "jpeg_show failed with return code %d...\n", ret); - goto done; + + if (type == 0) { + dprintf(5, "Decompressing bootsplash.data\n"); + ret = jpeg_show(jpeg, picture, width, height, depth); + if (ret) { + dprintf(1, "jpeg_show failed with return code %d...\n", ret); + goto done; + } + picture_post = picture; + post_flag |= SWITCH_RGB; + if (depth == 24 && mode_info->bytes_per_scanline >= width * 24 / 8) { + bmp_data_format_proc_24bpp(picture_post, picture, width, height, + width * 24 / 8, mode_info->bytes_per_scanline, post_flag); + } + } else { + picture_post = malloc_tmphigh(imagesize); + if (!picture_post) { + warn_noalloc(); + goto done; + } + + memcpy(picture_post, filedata+data_offset, filesize-data_offset); + post_flag |= SWITCH_LINE; + if (depth == 24 && mode_info->bytes_per_scanline >= width * 24 / 8) { + bmp_data_format_proc_24bpp(picture_post, picture, width, height, + width * 24 / 8, mode_info->bytes_per_scanline, post_flag); + } + free(picture_post); } /* Switch to graphics mode */ @@ -231,7 +295,7 @@ enable_bootsplash(void) } /* Show the picture */ - dprintf(5, "Showing bootsplash.jpg\n"); + dprintf(5, "Showing bootsplash picture\n"); iomemcpy(framebuffer, picture, imagesize); dprintf(5, "Bootsplash copy complete\n"); BootsplashActive = 1; -- 1.7.6-rc1

2 1

introduce a patch to enhance seabios splash picture showing ability
by Wayne Xia 18 Jun '11

18 Jun '11

Hello, guys, Sorry to take u time again. I made a patch for sea-bios, want to let the bios show a logo picture when KVM start. The reason and details for this patch is described below, which was sent in a mail a few days before: Patch description: ****************************************************** There is suggestion to let KVM be able to show a logo when it start up. Although the sea-bios already included a mechanism to show "bootsplash.jpg" when it was configured with "menu=on" option, it would not show it when the system was normally boot up, so I would like do some modification in the sea-bios code to let the bios showing it without "menu" option, also make this function configurable by the emulator. I tried the tiny jpeg decoder originally included, it seems there will be some observable visual quality lose and if the VESA is in 24BPP mode, the picture data would not be copied correctly for the reason that the byte number per line of that mode is not equal to 3*width, So I would like add some function to fix this, and also added some function to show 24bpp BMP file instead of JPEG as an option to get better visual effect. Following is what I did in details: 1 in the "boot.c", function "interactive_bootmenu", add codes to "romfile_loadfile" the "bootsplash.cfg" file. From it, the seabios get two configuration data : first is whether it should show the picture without menu enabled, second is how long it should show it. if this file loading failed, the sea-bios would act as before. 2 in the "bootsplash.c", function "enable_bootsplash(void)", add codes to try "romfile_loadfile" the "bootsplash.bmp", besides "bootsplash.jpg". Add a function to fix the problem when Bytes per line of VESA mode is not equal to picture width * 3. Also add additional code to show the BMP file instead of JPEG. 3 ADD "bmp.c" and "bmp.h" to support above code. ***************************************************** I didn't found the maintainer of seabios, could anyone help review about it, or help notice the maintainer? Many thanks. -- Best Regards Wayne Xia mail:xiawenc@cn.ibm.com tel:86-010-82450803

2 1

[PATCH] Boot up with a splash picture configurable by qemu
by Wayne Xia 16 Jun '11

16 Jun '11

From: Wayne Xia <xiawenc(a)cn.ibm.com> --- Makefile | 4 +- src/bmp.c | 69 ++++++++++++++++++++++++++++++++++ src/bmp.h | 51 +++++++++++++++++++++++++ src/boot.c | 37 ++++++++++++++++-- src/bootsplash.c | 109 +++++++++++++++++++++++++++++++++++++++++------------ 5 files changed, 239 insertions(+), 31 deletions(-) create mode 100644 src/bmp.c create mode 100644 src/bmp.h diff --git a/Makefile b/Makefile index d17f85a..214fe80 100644 --- a/Makefile +++ b/Makefile @@ -15,12 +15,12 @@ SRCBOTH=misc.c pmm.c stacks.c output.c util.c block.c floppy.c ata.c mouse.c \ kbd.c pci.c serial.c clock.c pic.c cdrom.c ps2port.c smp.c resume.c \ pnpbios.c pirtable.c vgahooks.c ramdisk.c pcibios.c blockcmd.c \ usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c \ - virtio-ring.c virtio-pci.c virtio-blk.c apm.c ahci.c + virtio-ring.c virtio-pci.c virtio-blk.c apm.c ahci.c bmp.c SRC16=$(SRCBOTH) system.c disk.c font.c SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c \ - pci_region.c + pci_region.c bmp.c SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c cc-option = $(shell if test -z "`$(1) $(2) -S -o /dev/null -xc \ diff --git a/src/bmp.c b/src/bmp.c new file mode 100644 index 0000000..b2a2333 --- /dev/null +++ b/src/bmp.c @@ -0,0 +1,69 @@ +//BMP data process and raw graphic data process functions +#include "bmp.h" + +void bmp_data_format_proc_24bpp(u8* src, u8* dest, int width,int height,int bytes_per_line_src, int bytes_per_line_dest ,u8 switch_flag) +{ + int cy=height; + u8 *pd,*ps,*pd_valid,*ps_lastline; + u8 t; + u8 rgb_switch_flag = switch_flag & SWITCH_RGB; + u8 line_switch_flag = switch_flag & SWITCH_LINE; + while (cy>0) + { + ps=bytes_per_line_src*cy+src-1; + if (line_switch_flag) { + pd=bytes_per_line_dest*(height-cy+1)+dest-1; + } + else { + pd=bytes_per_line_dest*cy+dest-1; + } + ps_lastline=ps-bytes_per_line_src; + pd_valid=pd-(bytes_per_line_dest-bytes_per_line_src); + while (pd>pd_valid) + { + *pd=0; + pd--; + } + while (ps>ps_lastline) + { + if (rgb_switch_flag) + { + t=*ps; + *ps=*(ps-2); + *(ps-2)=t; + } + *(pd--)=*(ps--); + *(pd--)=*(ps--); + *(pd--)=*(ps--); + } + cy--; + } +} + +int bmp_get_info(u8* data, int data_size, int* width_p, int* height_p, int* bpp_p, int* offset_p) +{ + if (data_size<54) + { + return 1; + } + + u16 bmp_filehead =bmp_load2byte(data+0); + if (bmp_filehead != 0x4d42) + { + return 2; + } + u32 bmp_recordsize =bmp_load4byte(data+2); + if (bmp_recordsize != data_size) + { + return 3; + } + u32 bmp_dataoffset =bmp_load4byte(data+10); + u32 bmp_width =bmp_load4byte(data+18); + u32 bmp_height =bmp_load4byte(data+22); + u32 bmp_bpp =bmp_load2byte(data+28); + *width_p =bmp_width; + *height_p =bmp_height; + *bpp_p =bmp_bpp; + *offset_p =bmp_dataoffset; + return 0; +} diff --git a/src/bmp.h b/src/bmp.h new file mode 100644 index 0000000..60045f9 --- /dev/null +++ b/src/bmp.h @@ -0,0 +1,51 @@ +#ifndef BMP_H +#define BMP_H +#include "types.h" + +#define WIDTHBYTES(bits) (((bits)+31)/32*4) + +typedef u8 BYTE; +typedef u32 BYTE4; + + +typedef struct tagBITMAPFILEHEADER { +BYTE bfType[2]; +BYTE bfSize[4]; +BYTE bfReserved1[2]; +BYTE bfReserved2[2]; +BYTE bfOffBits[4]; +} BITMAPFILEHEADER,tagBITMAPFILEHEADER; + +typedef struct tagBITMAPINFOHEADER{ +BYTE biSize[4]; +BYTE biWidth[4]; +BYTE biHeight[4]; +BYTE biPlanes[2]; +BYTE biBitCount[2]; +BYTE biCompression[4]; +BYTE biSizeImage[4]; +BYTE biXPelsPerMeter[4]; +BYTE biYPelsPerMeter[4]; +BYTE biClrUsed[4]; +BYTE biClrImportant[4]; +} BITMAPINFOHEADER,tagBITMAPINFOHEADER; + +typedef struct tagRGBQUAD { +BYTE rgbBlue; +BYTE rgbGreen; +BYTE rgbRed; +BYTE rgbReserved; +} RGBQUAD,tagRGBQUAD; + +#define bmp_load4byte(addr) (addr)[0]+((addr)[1]<<8)+((addr)[2]<<16)+((addr)[3]<<24) +#define bmp_load2byte(addr) (addr)[0]+((addr)[1]<<8) + +#define SWITCH_RGB 0x01 +#define SWITCH_LINE 0x02 + +//src can be equal to dest, if do not need to switch the lines from bottom to top +//bytes_per_line_src must be less or eqaul than bytes_per_line_dest +void bmp_data_format_proc_24bpp(u8* src, u8* dest, int width,int height,int bytes_per_line_src, int bytes_per_line_dest ,u8 switch_flag); + +int bmp_get_info(u8* data, int data_size, int* width_p, int* height_p, int* bpp_p, int* offset_p); +#endif diff --git a/src/boot.c b/src/boot.c index 9a67916..676c522 100644 --- a/src/boot.c +++ b/src/boot.c @@ -372,16 +372,45 @@ boot_add_cbfs(void *data, const char *desc, int prio) static void interactive_bootmenu(void) { - if (! CONFIG_BOOTMENU || ! qemu_cfg_show_boot_menu()) - return; + int filecfg_size; + u8 *filecfg_p = romfile_loadfile("bootsplash.cfg", &filecfg_size); + u8 showflag_normal; + u16 splash_time; + + if (filecfg_p != NULL && filecfg_size>=4) { + showflag_normal =*filecfg_p; + splash_time =*(filecfg_p+2)+(*(filecfg_p+3)<<8); //little endian + free (filecfg_p); + } + else { + showflag_normal =0; + splash_time =CONFIG_BOOTMENU_WAIT; + } + + if (! qemu_cfg_show_boot_menu()) { //the user do not want to show the menu, so normally bootup + if (showflag_normal) { + while (get_keystroke(0) >= 0) + ; + enable_bootsplash(); + get_keystroke(splash_time); + disable_bootsplash(); + + } + return; + } + else { + if (! CONFIG_BOOTMENU) //user want to show menu, check the if the bios config allow it + return; + } + while (get_keystroke(0) >= 0) - ; + ; printf("Press F12 for boot menu.\n\n"); enable_bootsplash(); - int scan_code = get_keystroke(CONFIG_BOOTMENU_WAIT); + int scan_code = get_keystroke(splash_time); disable_bootsplash(); if (scan_code != 0x86) /* not F12 */ diff --git a/src/bootsplash.c b/src/bootsplash.c index cf1a603..0adef01 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -12,7 +12,7 @@ #include "jpeg.h" // splash #include "biosvar.h" // SET_EBDA #include "paravirt.h" // romfile_find - +#include "bmp.h" /**************************************************************** * VESA structures @@ -109,7 +109,7 @@ enable_vga_console(void) static int find_videomode(struct vesa_info *vesa_info, struct vesa_mode_info *mode_info - , int width, int height) + , int width, int height, int bpp_req) { dprintf(3, "Finding vesa mode with dimensions %d/%d\n", width, height); u16 *videomodes = SEGOFF_TO_FLATPTR(vesa_info->video_mode_ptr); @@ -135,8 +135,14 @@ find_videomode(struct vesa_info *vesa_info, struct vesa_mode_info *mode_info || mode_info->y_resolution != height) continue; u8 depth = mode_info->bits_per_pixel; - if (depth != 16 && depth != 24 && depth != 32) - continue; + if (bpp_req == 0) { + if (depth != 16 && depth != 24 && depth != 32) + continue; + } + else { + if (depth != bpp_req) + continue; + } return videomode; } } @@ -149,12 +155,20 @@ enable_bootsplash(void) if (!CONFIG_BOOTSPLASH) return; dprintf(3, "Checking for bootsplash\n"); + u8 type=0;//0 means jpg, 1 means bmp, default is 0=jpg int filesize; u8 *filedata = romfile_loadfile("bootsplash.jpg", &filesize); - if (!filedata) - return; + if (!filedata) { + filedata = romfile_loadfile("bootsplash.bmp", &filesize); + if (!filedata) { + return; + } + type =1; + } + //dprintf(3, "start showing bootsplash\n"); - u8 *picture = NULL; + u8 *picture = NULL; //data buff used to be flushded to the video buff + u8 *picture_post = NULL; //another buff, used to do some post process, such as line sequence reverse struct vesa_info *vesa_info = malloc_tmplow(sizeof(*vesa_info)); struct vesa_mode_info *mode_info = malloc_tmplow(sizeof(*mode_info)); struct jpeg_decdata *jpeg = jpeg_alloc(); @@ -184,20 +198,43 @@ enable_bootsplash(void) vesa_info->vesa_version>>8, vesa_info->vesa_version&0xff, vendor, product); - // Parse jpeg and get image size. - dprintf(5, "Decoding bootsplash.jpg\n"); - int ret = jpeg_decode(jpeg, filedata); - if (ret) { - dprintf(1, "jpeg_decode failed with return code %d...\n", ret); - goto done; + int ret, width, height; + int bpp_require=0; + int data_offset=0; + u8 post_flag=0; + if (type == 0) { + // Parse jpeg and get image size. + dprintf(5, "Decoding bootsplash.jpg\n"); + ret = jpeg_decode(jpeg, filedata); + if (ret) { + dprintf(1, "jpeg_decode failed with return code %d...\n", ret); + goto done; + } + jpeg_get_size(jpeg, &width, &height); + bpp_require =24;//for better vision effect, although there are 16 bpp mode exist + } + else { + // Parse jpeg and get image size. + dprintf(5, "retrieve information of bootsplash.bmp file\n"); + int bpp_src; + ret=bmp_get_info(filedata, filesize, &width, &height, &bpp_src, &data_offset); + if (ret) { + dprintf(1, "retrieve information from bmp file failed with return code %d...\n", ret); + goto done; + } + if (bpp_src != 24) { + dprintf(1, "only support 24bpp color, now the bmp file's bpp is %d...\n", bpp_src); + goto done; + } + bpp_require =24; } - int width, height; - jpeg_get_size(jpeg, &width, &height); // Try to find a graphics mode with the corresponding dimensions. - int videomode = find_videomode(vesa_info, mode_info, width, height); - if (videomode < 0) - goto done; + int videomode = find_videomode(vesa_info, mode_info, width, height, bpp_require); + if (videomode < 0) { + dprintf(1, "failed to find a videomode with %dx%d %dbpp (0 means any).\n", width, height, bpp_require); + goto done; + } void *framebuffer = mode_info->phys_base_ptr; int depth = mode_info->bits_per_pixel; dprintf(3, "mode: %04x\n", videomode); @@ -206,17 +243,39 @@ enable_bootsplash(void) dprintf(3, "bits per pixel: %d\n", depth); // Allocate space for image and decompress it. - int imagesize = width * height * (depth / 8); + int imagesize = height * mode_info->bytes_per_scanline; picture = malloc_tmphigh(imagesize); if (!picture) { warn_noalloc(); goto done; } - dprintf(5, "Decompressing bootsplash.jpg\n"); - ret = jpeg_show(jpeg, picture, width, height, depth); - if (ret) { - dprintf(1, "jpeg_show failed with return code %d...\n", ret); - goto done; + + if (type == 0) { + dprintf(5, "Decompressing bootsplash.data\n"); + ret = jpeg_show(jpeg, picture, width, height, depth); + if (ret) { + dprintf(1, "jpeg_show failed with return code %d...\n", ret); + goto done; + } + picture_post=picture; + post_flag |= SWITCH_RGB; + if ( depth==24 && mode_info->bytes_per_scanline >= width * 24 /8){ + bmp_data_format_proc_24bpp(picture_post, picture, width, height, width * 24 /8, mode_info->bytes_per_scanline, post_flag); + } + } + else { + picture_post = malloc_tmphigh(imagesize); + if (!picture_post) { + warn_noalloc(); + goto done; + } + + memcpy(picture_post, filedata+data_offset,filesize-data_offset); + post_flag |= SWITCH_LINE; + if ( depth==24 && mode_info->bytes_per_scanline >= width * 24 /8){ + bmp_data_format_proc_24bpp(picture_post, picture, width, height, width * 24 /8, mode_info->bytes_per_scanline, post_flag); + } + free(picture_post); } /* Switch to graphics mode */ @@ -231,7 +290,7 @@ enable_bootsplash(void) } /* Show the picture */ - dprintf(5, "Showing bootsplash.jpg\n"); + dprintf(5, "Showing bootsplash picture\n"); iomemcpy(framebuffer, picture, imagesize); dprintf(5, "Bootsplash copy complete\n"); BootsplashActive = 1; -- 1.7.1

1 0

Want to introduce a feature to let SeaBios Show a bootflash picture when system start up normally
by wayne 15 Jun '11

15 Jun '11

Hello all, There is suggestion to let KVM be able to show a logo when it start up. Although the sea-bios already included a mechanism to try show "bootsplash.jpg" when it was configured with "menu=on" option, but it would not show it when the system was normally boot up, so I would like do some modification in the sea-bios code to let the bios showing the picture when the system boot up. I tried the tiny jpeg decoder originally included, it seems there will be some observable visual quality lose and if the VESA is in 24BPP mode, the picture data would not be copied correctly for the reason that the byte number per line of that mode is not equal to 3*width, So I want to add some function to fix this, and also added some function to show 24bpp BMP file instead of JPEG as an option to get better visual effect. Following is what I want to do: 1 in the "boot.c", function "interactive_bootmenu", add codes to "romfile_loadfile" the "bootsplash.cfg" file. From it, the seabios get two configuration data : first is should it show the picture without menu enabled, second is how long it should show it. if load file failed, the sea-bios would act as before. 2 in the "bootsplash.c", function "enable_bootsplash(void)", add codes to try "romfile_loadfile" the "bootsplash.bmp", besides "bootsplash.jpg". Add a function to fix the problem when Bytes per line of VESA mode is not equal to picture width * 3. Also add additional code to show the BMP file instead of JPEG. 3 ADD "bmp.c" and "bmp.h" to support above code. Could this be acceptable? -- Best Regards Wayne Xia mail:xiawenc@cn.ibm.com tel:86-010-82450803

1 0

[PATCH] Correct fseg allocation for SMBIOS tables.
by Ian Campbell 14 Jun '11

14 Jun '11

Anthony Perard noticed that grub was unhappy because it sees no low memory and that his e820 table was missing the first entry. He then pointed out this rather glaring error in the allocation of space for the SMBIOS tables. I've no idea why I didn't see this failure. Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> Tested-by: Anthony Perard <anthony.perard(a)citrix.com> --- src/biostables.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/biostables.c b/src/biostables.c index 761b260..d8b5067 100644 --- a/src/biostables.c +++ b/src/biostables.c @@ -95,7 +95,7 @@ copy_smbios(void *pos) return; if (checksum(pos+0x10, p->length-0x10) != 0) return; - struct smbios_entry_point *newpos = malloc_fseg(sizeof(p->length)); + struct smbios_entry_point *newpos = malloc_fseg(p->length); if (!newpos) { warn_noalloc(); return; -- 1.7.2.5

2 1

[patch] Add IDE_TO_AHCI config
by Chuang, Alex 13 Jun '11

13 Jun '11

Hi, I add one config 'IDE_TO_AHCI' in 'src\Kconfig' and modify 'src\ata.c'. Please help me to review and check-in. This 'IDE_TO_AHCI' function can let SeaBIOS handle AHCI controller as IDE controller when 'ATA' enable, and also let Windows OS to load AHCI inbox driver or chipset vender's AHCI driver. In other words, it means that SATA Hard Disk ran as IDE mode in SeaBIOS but AHCI mode in Windows OS. Attached file: A.patch B.patch. Signed-off-by: Alex Chuang <Alex.Chuang(a)amd.com> Best regards, Alex

3 8

[RfC PATCH 0/2] pci: two pass initialization
by Gerd Hoffmann 07 Jun '11

07 Jun '11

Hi, This patch set switches seabios to a two-pass pci initialization. The first pass figures the memory requirements which are then used by the second pass to pack the regions. I've splitted it into two patches to make it easy to check out. The first patch does all the calculations and prints what it would do to the debug log. The second patch switches the new allocation code live. The patches have been tested with the upcoming q35 emulation for qemu. They are based on the q35 seabios too, but rebasing to master shouldn't be hard. Below you can see the allocations created by the patch. Comments? cheers, Gerd ========== /proc/iomem ============== 00000000-00000fff : reserved 00001000-0009e7ff : System RAM 0009e800-0009ffff : reserved 000c0000-000c8bff : Video ROM 000c9000-000c97ff : Adapter ROM 000f0000-000fffff : reserved 000f0000-000fffff : System ROM 00100000-3fffcfff : System RAM 01000000-014e5a17 : Kernel code 014e5a18-01ba42ef : Kernel data 01ce4000-01f474e3 : Kernel bss 3fffd000-3fffffff : reserved e0000000-efffffff : PCI MMCONFIG 0 [00-ff] e0000000-efffffff : reserved fa000000-fbffffff : 0000:00:02.0 fa000000-fbffffff : cirrusfb fc000000-fc3fffff : PCI Bus 0000:0c fc000000-fc0fffff : PCI Bus 0000:0d fc100000-fc1fffff : PCI Bus 0000:0e fc200000-fc2fffff : PCI Bus 0000:0f fc300000-fc3fffff : PCI Bus 0000:10 fc400000-fc4fffff : PCI Bus 0000:01 fc500000-fc5fffff : PCI Bus 0000:02 fc600000-fc6fffff : PCI Bus 0000:03 fc600000-fc6fffff : PCI Bus 0000:04 fc600000-fc6fffff : PCI Bus 0000:05 fc700000-fc7fffff : PCI Bus 0000:06 fc800000-fc8fffff : PCI Bus 0000:07 fc900000-fc9fffff : PCI Bus 0000:08 fca00000-fcafffff : PCI Bus 0000:09 fcb00000-fcbfffff : PCI Bus 0000:0a fcc00000-fccfffff : PCI Bus 0000:0b fdc00000-fdffffff : PCI Bus 0000:0c fdc00000-fdcfffff : PCI Bus 0000:0d fdd00000-fddfffff : PCI Bus 0000:0e fde00000-fdefffff : PCI Bus 0000:0f fdf00000-fdffffff : PCI Bus 0000:10 fe000000-fe0fffff : PCI Bus 0000:01 fe100000-fe1fffff : PCI Bus 0000:02 fe200000-fe2fffff : PCI Bus 0000:03 fe200000-fe2fffff : PCI Bus 0000:04 fe200000-fe2fffff : PCI Bus 0000:05 fe300000-fe3fffff : PCI Bus 0000:06 fe400000-fe4fffff : PCI Bus 0000:07 fe500000-fe5fffff : PCI Bus 0000:08 fe600000-fe6fffff : PCI Bus 0000:09 fe700000-fe7fffff : PCI Bus 0000:0a fe800000-fe8fffff : PCI Bus 0000:0b fe900000-fe90ffff : 0000:00:02.0 fe910000-fe91ffff : 0000:00:03.0 fe920000-fe920fff : 0000:00:02.0 fe920000-fe920fff : cirrusfb fe921000-fe921fff : 0000:00:03.0 fe921000-fe921fff : virtio-pci fe922000-fe922fff : 0000:00:1f.2 fe922000-fe922fff : ahci fec00000-fec00fff : IOAPIC 0 fed00000-fed003ff : HPET 0 fee00000-fee00fff : Local APIC feffc000-feffffff : reserved fffc0000-ffffffff : reserved

12 43

Re: [SeaBIOS] Issues with ASRock E350M1
by Scott Duplichan 06 Jun '11

06 Jun '11

Marshall Buschman wrote: ]Or not! It's back. Same issue as before. ] ]Quoting mbuschman(a)lucidmachines.com: ] ]> Mystery solved - the drive's shipping firmware was causing this ]> behavior - an upgrade to the latest firmware (2.0) resolves this. ]> ]> Thanks! ]> -Marshall Buschman ]> ]> Quoting mbuschman(a)lucidmachines.com: ]> ]>> I should mention that a 16gb Kingston SSD I have works just fine, ]>> as well as a 500gb traditional hard disk. ]>> Looks like this might be a problem with the disk itself. I know the ]>> Sandforce controllers do all kinds of "smart" things like ]>> compressing data to achieve greater throughput. I'll investigate ]>> and see what I can find. Hello Marshall, An SSD drive I bought for boot time testing also has the SandForce sf-1200 controller: http://www.mushkin.com/Digital-Storage/SSDs/MKNSSDCL40GB-DX.aspx I have not noticed any detection problem with it. Let me know if there is any experiment I could do with it. Thanks, Scott

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