SeaBIOS

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3801 discussions

Re: [SeaBIOS] [PATCH] seabios/pci: enable 64 bit bar on seabios
by Gerd Hoffmann 05 Nov '12

05 Nov '12

Hi, > I just want to enable 64 bit bars for KVM usage, seabios 1.7.0 is > used in current qemu-kvm, which not handle 64 bit bars yet. I cloned > seabios code from kernel.org(seems no 64 bit bars supporting), but I > was not taking notice of the tree on http://git.qemu.org/, yes it has > already done 64 bit bars handling. So you may ignore this patch. > > Btw, when will the latest seabios(especially 64 bits bars) be > involved qemu-kvm? qemu 1.2.0 has it (seabios 1.7.1, a git snapshot very close to it to be exact), and qemu-kvm 1.2.0 should have it too. cheers, Gerd

2 1

[PATCH] seabios/pci: enable 64 bit bar on seabios
by Xudong Hao 04 Nov '12

04 Nov '12

64 bit bar sizing and MMIO allocation. The 64 bit window is placed above high memory, top down from the end of guest physical address space. Signed-off-by: Xudong Hao <xudong.hao(a)intel.com> --- src/mtrr.c | 24 +++++++++----- src/pci.h | 2 +- src/pciinit.c | 99 ++++++++++++++++++++++++++++++++++++++------------------ src/util.h | 1 + 4 files changed, 85 insertions(+), 41 deletions(-) diff --git a/src/mtrr.c b/src/mtrr.c index 0548043..05264c4 100644 --- a/src/mtrr.c +++ b/src/mtrr.c @@ -31,12 +31,26 @@ #define MTRR_MEMTYPE_WP 5 #define MTRR_MEMTYPE_WB 6 +int cpu_phys_addr(void) +{ + u32 eax, ebx, ecx, edx; + int phys_bits = 36; + cpuid(0x80000000u, &eax, &ebx, &ecx, &edx); + + if (eax >= 0x80000008) { + /* Get physical bits from leaf 0x80000008 (if available) */ + cpuid(0x80000008u, &eax, &ebx, &ecx, &edx); + phys_bits = eax & 0xff; + } + return phys_bits; +} + void mtrr_setup(void) { if (!CONFIG_MTRR_INIT || CONFIG_COREBOOT || usingXen()) return; - u32 eax, ebx, ecx, edx, cpuid_features; + u32 eax, ebx, ecx, cpuid_features; cpuid(1, &eax, &ebx, &ecx, &cpuid_features); if (!(cpuid_features & CPUID_MTRR)) return; @@ -81,13 +95,7 @@ void mtrr_setup(void) } // Set variable MTRRs - int phys_bits = 36; - cpuid(0x80000000u, &eax, &ebx, &ecx, &edx); - if (eax >= 0x80000008) { - /* Get physical bits from leaf 0x80000008 (if available) */ - cpuid(0x80000008u, &eax, &ebx, &ecx, &edx); - phys_bits = eax & 0xff; - } + int phys_bits = cpu_phys_addr(); u64 phys_mask = ((1ull << phys_bits) - 1); for (i=0; i<vcnt; i++) { wrmsr_smp(MTRRphysBase_MSR(i), 0); diff --git a/src/pci.h b/src/pci.h index a2a5a4c..0fa2ae8 100644 --- a/src/pci.h +++ b/src/pci.h @@ -53,7 +53,7 @@ struct pci_device { u8 secondary_bus; struct { u32 addr; - u32 size; + u64 size; int is64; } bars[PCI_NUM_REGIONS]; diff --git a/src/pciinit.c b/src/pciinit.c index 7d83368..a3a92ae 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -22,6 +22,7 @@ enum pci_region_type { PCI_REGION_TYPE_IO, PCI_REGION_TYPE_MEM, PCI_REGION_TYPE_PREFMEM, + PCI_REGION_TYPE_MEM_64, PCI_REGION_TYPE_COUNT, }; @@ -29,35 +30,40 @@ static const char *region_type_name[] = { [ PCI_REGION_TYPE_IO ] = "io", [ PCI_REGION_TYPE_MEM ] = "mem", [ PCI_REGION_TYPE_PREFMEM ] = "prefmem", + [ PCI_REGION_TYPE_MEM_64 ] = "mem64", }; struct pci_bus { struct { /* pci region stats */ - u32 count[32 - PCI_MEM_INDEX_SHIFT]; - u32 sum, max; + u32 count[64 - PCI_MEM_INDEX_SHIFT]; + u64 sum, max; /* seconday bus region sizes */ u32 size; /* pci region assignments */ - u32 bases[32 - PCI_MEM_INDEX_SHIFT]; - u32 base; + u64 bases[64 - PCI_MEM_INDEX_SHIFT]; + u64 base; } r[PCI_REGION_TYPE_COUNT]; struct pci_device *bus_dev; }; -static int pci_size_to_index(u32 size, enum pci_region_type type) +static u64 pci_size_to_index(u64 size, enum pci_region_type type) { - int index = __fls(size); + u64 index; int shift = (type == PCI_REGION_TYPE_IO) ? PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT; + if (((u32)(size >> 32) & ~0) == 0) + index = (u64)__fls((u32)size); + else + index = (u64)__fls((u32)(size >> 32)) + 32; if (index < shift) index = shift; index -= shift; return index; } -static u32 pci_index_to_size(int index, enum pci_region_type type) +static u64 pci_index_to_size(u64 index, enum pci_region_type type) { int shift = (type == PCI_REGION_TYPE_IO) ? PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT; @@ -69,6 +75,8 @@ static enum pci_region_type pci_addr_to_type(u32 addr) { if (addr & PCI_BASE_ADDRESS_SPACE_IO) return PCI_REGION_TYPE_IO; + if (addr & PCI_BASE_ADDRESS_MEM_TYPE_64) + return PCI_REGION_TYPE_MEM_64; if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH) return PCI_REGION_TYPE_PREFMEM; return PCI_REGION_TYPE_MEM; @@ -330,7 +338,7 @@ static u32 pci_size_roundup(u32 size) } static void -pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size) +pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u64 *size) { u32 ofs = pci_bar(pci, bar); u16 bdf = pci->bdf; @@ -352,9 +360,9 @@ pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size) *size = (~(*val & mask)) + 1; } -static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size) +static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u64 size) { - u32 index; + u64 index; index = pci_size_to_index(size, type); size = pci_index_to_size(index, type); @@ -378,17 +386,27 @@ static void pci_bios_check_devices(struct pci_bus *busses) struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)]; int i; for (i = 0; i < PCI_NUM_REGIONS; i++) { - u32 val, size; + u32 val, val_upper; + u64 size; + u64 size_upper; + u8 is64; + pci_bios_get_bar(pci, i, &val, &size); - if (val == 0) + is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) && + (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) + == PCI_BASE_ADDRESS_MEM_TYPE_64); + + if (is64) { + pci_bios_get_bar(pci, i + 1, &val_upper, &size_upper); + size = (size_upper << 32) | size; + } + size &= ~(size - 1); + if (size == 0) continue; - pci_bios_bus_reserve(bus, pci_addr_to_type(val), size); pci->bars[i].addr = val; pci->bars[i].size = size; - pci->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) && - (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) - == PCI_BASE_ADDRESS_MEM_TYPE_64); + pci->bars[i].is64 = is64; if (pci->bars[i].is64) i++; @@ -410,7 +428,7 @@ static void pci_bios_check_devices(struct pci_bus *busses) if (s->r[type].size < limit) s->r[type].size = limit; s->r[type].size = pci_size_roundup(s->r[type].size); - pci_bios_bus_reserve(parent, type, s->r[type].size); + pci_bios_bus_reserve(parent, type, (u64)s->r[type].size); } dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n", secondary_bus, @@ -423,11 +441,12 @@ static void pci_bios_check_devices(struct pci_bus *busses) #define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1) // Setup region bases (given the regions' size and alignment) -static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end) +static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end, u64 high_start, u64 high_end) { bus->r[PCI_REGION_TYPE_IO].base = 0xc000; int reg1 = PCI_REGION_TYPE_PREFMEM, reg2 = PCI_REGION_TYPE_MEM; + int reg3 = PCI_REGION_TYPE_MEM_64; if (bus->r[reg1].sum < bus->r[reg2].sum) { // Swap regions so larger area is more likely to align well. reg1 = PCI_REGION_TYPE_MEM; @@ -436,7 +455,8 @@ static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end) bus->r[reg2].base = ROOT_BASE(end, bus->r[reg2].sum, bus->r[reg2].max); bus->r[reg1].base = ROOT_BASE(bus->r[reg2].base, bus->r[reg1].sum , bus->r[reg1].max); - if (bus->r[reg1].base < start) + bus->r[reg3].base = ROOT_BASE(high_end, bus->r[reg3].sum, bus->r[reg3].max); + if (bus->r[reg1].base < start || bus->r[reg3].base < high_start) // Memory range requested is larger than available. return -1; return 0; @@ -449,29 +469,34 @@ static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end) static void pci_bios_init_bus_bases(struct pci_bus *bus) { - u32 base, newbase, size; + u64 base, newbase, size; int type, i; for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { - dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type], - bus->r[type].max, bus->r[type].sum, bus->r[type].base); + dprintf(1, " type %s max 0x%08x%08x sum 0x%08x%08x base 0x%08x%08x\n", + region_type_name[type], (u32)(bus->r[type].max >> 32), + (u32)(bus->r[type].max), (u32)(bus->r[type].sum >> 32), + (u32)(bus->r[type].sum), (u32)(bus->r[type].base >> 32), + (u32)(bus->r[type].base)); base = bus->r[type].base; for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) { size = pci_index_to_size(i, type); if (!bus->r[type].count[i]) continue; newbase = base + size * bus->r[type].count[i]; - dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n", - size, bus->r[type].count[i], base, newbase - 1); + dprintf(1, " size 0x%08x%08x: %d bar(s), 0x%08x%08x -> 0x%08x%08x\n", + (u32)(size >> 32), (u32)size, bus->r[type].count[i], + (u32)(base >> 32), (u32)base, (u32)((newbase - 1) >> 32), + (u32)(newbase -1)); bus->r[type].bases[i] = base; base = newbase; } } } -static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size) +static u64 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u64 size) { - u32 index, addr; + u64 index, addr; index = pci_size_to_index(size, type); addr = bus->r[type].bases[index]; @@ -500,7 +525,7 @@ static void pci_bios_map_devices(struct pci_bus *busses) int type; for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { s->r[type].base = pci_bios_bus_get_addr( - parent, type, s->r[type].size); + parent, type, (u64)s->r[type].size); } dprintf(1, "PCI: init bases bus %d (secondary)\n", secondary_bus); pci_bios_init_bus_bases(s); @@ -539,14 +564,21 @@ static void pci_bios_map_devices(struct pci_bus *busses) if (pci->bars[i].addr == 0) continue; + u64 addr_64; int type = pci_addr_to_type(pci->bars[i].addr); - u32 addr = pci_bios_bus_get_addr(bus, type, pci->bars[i].size); - dprintf(1, " bar %d, addr %x, size %x [%s]\n", - i, addr, pci->bars[i].size, region_type_name[type]); + addr_64 = pci_bios_bus_get_addr(bus, type, pci->bars[i].size); + + u32 addr = (u32)addr_64; + u32 addr_upper = (u32)(addr_64 >> 32); + dprintf(1, " bar %d, addr %x, size 0x%08x%08x [%s]\n", + i, addr, (u32)(pci->bars[i].size >> 32), + (u32)(pci->bars[i].size), region_type_name[type]); pci_set_io_region_addr(pci, i, addr); - if (pci->bars[i].is64) + if (pci->bars[i].is64) { + pci_set_io_region_addr(pci, i + 1, addr_upper); i++; + } } } } @@ -569,6 +601,8 @@ pci_setup(void) u32 start = BUILD_PCIMEM_START; u32 end = BUILD_PCIMEM_END; + u64 high_start = RamSizeOver4G + 0x100000000ull; + u64 high_end = 1ull << cpu_phys_addr(); dprintf(1, "=== PCI bus & bridge init ===\n"); if (pci_probe_host() != 0) { @@ -587,7 +621,8 @@ pci_setup(void) } memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1)); pci_bios_check_devices(busses); - if (pci_bios_init_root_regions(&busses[0], start, end) != 0) { + if (pci_bios_init_root_regions(&busses[0], start, end, high_start, + high_end) != 0) { panic("PCI: out of address space\n"); } diff --git a/src/util.h b/src/util.h index eecba8b..4eacb36 100644 --- a/src/util.h +++ b/src/util.h @@ -475,6 +475,7 @@ static inline void free(void *data) { } // mtrr.c +int cpu_phys_addr(void); void mtrr_setup(void); // romlayout.S -- 1.5.5

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Re: [SeaBIOS] [RFC PATCH v3 00/19] ACPI memory hotplug
by Avi Kivity 01 Nov '12

01 Nov '12

On 10/31/2012 12:58 PM, Stefan Hajnoczi wrote: > On Fri, Sep 21, 2012 at 1:17 PM, Vasilis Liaskovitis > <vasilis.liaskovitis(a)profitbricks.com> wrote: >> This is v3 of the ACPI memory hotplug functionality. Only x86_64 target is supported >> for now. > > Hi Vasilis, > Regarding the hot unplug issue we've been discussing, it's possible to > progress this patch series without fully solving that problem upfront. > > Karen Noel suggested that the series could be rolled without the hot > unplug command, so that it's not possible to hit the unsafe case. > This would allow users to hot plug additional memory. They would have > to use virtio-balloon to reduce the memory footprint again. Later, > when the memory region referencing issue has been solved the hot > unplug command can be added. > > Just wanted to mention Karen's idea in case you feel stuck right now. We could introduce hotunplug as an experimental feature so people can test and play with it, and later graduate it to a fully supported feature. -- error compiling committee.c: too many arguments to function

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Re: [SeaBIOS] [Qemu-devel] [RFC PATCH v3 05/19] Implement dimm device abstraction
by Avi Kivity 31 Oct '12

31 Oct '12

On 10/31/2012 02:18 PM, Stefan Hajnoczi wrote: >> >> IMO we should use the same mechanism as proposed for other devices: >> address_space_map() should grab a reference on the dimm device, and >> address_space_unmap() can release it. This way device destruction will >> be deferred as soon as all devices complete I/O. >> >> We will have to be careful with network receive buffers though, since >> they can be held indefinitely. > > Network receive buffers aren't mapped. Net receive is not zero-copy. > For example, virtio-net does virtqueue_pop() inside > virtio_net_receive(). > > I don't see a problem with networking. What about vhost-net? But that is managed separately with a MemoryListener. -- error compiling committee.c: too many arguments to function

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Re: [SeaBIOS] [Qemu-devel] [RFC PATCH v3 05/19] Implement dimm device abstraction
by Avi Kivity 31 Oct '12

31 Oct '12

On 10/24/2012 10:06 AM, liu ping fan wrote: > On Tue, Oct 23, 2012 at 8:25 PM, Stefan Hajnoczi <stefanha(a)gmail.com> wrote: >> On Fri, Sep 21, 2012 at 01:17:21PM +0200, Vasilis Liaskovitis wrote: >>> +static void dimm_populate(DimmDevice *s) >>> +{ >>> + DeviceState *dev= (DeviceState*)s; >>> + MemoryRegion *new = NULL; >>> + >>> + new = g_malloc(sizeof(MemoryRegion)); >>> + memory_region_init_ram(new, dev->id, s->size); >>> + vmstate_register_ram_global(new); >>> + memory_region_add_subregion(get_system_memory(), s->start, new); >>> + s->mr = new; >>> +} >>> + >>> +static void dimm_depopulate(DimmDevice *s) >>> +{ >>> + assert(s); >>> + vmstate_unregister_ram(s->mr, NULL); >>> + memory_region_del_subregion(get_system_memory(), s->mr); >>> + memory_region_destroy(s->mr); >>> + s->mr = NULL; >>> +} >> >> How is dimm hot unplug protected against callers who currently have RAM >> mapped (from cpu_physical_memory_map())? >> >> Emulated devices call cpu_physical_memory_map() directly or indirectly >> through DMA emulation code. The RAM pointer may be held for arbitrary >> lengths of time, across main loop iterations, etc. >> >> It's not clear to me that it is safe to unplug a DIMM that has network >> or disk I/O buffers, for example. We also need to be robust against >> malicious guests who abuse the hotplug lifecycle. QEMU should never be >> left with dangling pointers. >> > Not sure about the block layer. But I think those thread are already > out of big lock, so there should be a MemoryListener to catch the > RAM-unplug event, and if needed, bdrv_flush. IMO we should use the same mechanism as proposed for other devices: address_space_map() should grab a reference on the dimm device, and address_space_unmap() can release it. This way device destruction will be deferred as soon as all devices complete I/O. We will have to be careful with network receive buffers though, since they can be held indefinitely. -- error compiling committee.c: too many arguments to function

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Re: [SeaBIOS] [RFC PATCH v3 00/19] ACPI memory hotplug
by Stefan Hajnoczi 31 Oct '12

31 Oct '12

On Fri, Sep 21, 2012 at 1:17 PM, Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> wrote: > This is v3 of the ACPI memory hotplug functionality. Only x86_64 target is supported > for now. Hi Vasilis, Regarding the hot unplug issue we've been discussing, it's possible to progress this patch series without fully solving that problem upfront. Karen Noel suggested that the series could be rolled without the hot unplug command, so that it's not possible to hit the unsafe case. This would allow users to hot plug additional memory. They would have to use virtio-balloon to reduce the memory footprint again. Later, when the memory region referencing issue has been solved the hot unplug command can be added. Just wanted to mention Karen's idea in case you feel stuck right now. Stefan

1 0

Re: [SeaBIOS] [PATCH] ACPI: Remove unnecessary Return(One) calls from DSDT.
by Marc Jones 29 Oct '12

29 Oct '12

On Mon, Oct 29, 2012 at 10:17 AM, Marc Jones <marc.jones(a)se-eng.com> wrote: > Acked-by: Marc Jones <marc.jones(a)se-eng.com> > > On Sat, Oct 27, 2012 at 7:33 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: >> Recent iasl compilers warn about spurious return calls. Remove extra >> return calls from the GPE event methods. >> >> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> >> --- >> src/acpi-dsdt.dsl | 20 ++------------------ >> 1 file changed, 2 insertions(+), 18 deletions(-) >> >> diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl >> index d2575a5..284d70d 100644 >> --- a/src/acpi-dsdt.dsl >> +++ b/src/acpi-dsdt.dsl >> @@ -559,7 +559,6 @@ DefinitionBlock ( >> PCNT(Local0, 3) >> } >> } >> - Return(One) >> } >> >> } >> @@ -729,7 +728,6 @@ DefinitionBlock ( >> } >> Increment(Local0) >> } >> - Return(One) >> } >> } >> >> @@ -743,54 +741,40 @@ DefinitionBlock ( >> Name(_HID, "ACPI0006") >> >> Method(_L00) { >> - Return(0x01) >> } >> Method(_E01) { >> // PCI hotplug event >> - Return(\_SB.PCI0.PCNF()) >> + \_SB.PCI0.PCNF() >> } >> Method(_E02) { >> // CPU hotplug event >> - Return(\_SB.PRSC()) >> + \_SB.PRSC() >> } >> Method(_L03) { >> - Return(0x01) >> } >> Method(_L04) { >> - Return(0x01) >> } >> Method(_L05) { >> - Return(0x01) >> } >> Method(_L06) { >> - Return(0x01) >> } >> Method(_L07) { >> - Return(0x01) >> } >> Method(_L08) { >> - Return(0x01) >> } >> Method(_L09) { >> - Return(0x01) >> } >> Method(_L0A) { >> - Return(0x01) >> } >> Method(_L0B) { >> - Return(0x01) >> } >> Method(_L0C) { >> - Return(0x01) >> } >> Method(_L0D) { >> - Return(0x01) >> } >> Method(_L0E) { >> - Return(0x01) >> } >> Method(_L0F) { >> - Return(0x01) >> } >> } >> } >> -- >> 1.7.11.7 >> >> >> _______________________________________________ >> SeaBIOS mailing list >> SeaBIOS(a)seabios.org >> http://www.seabios.org/mailman/listinfo/seabios -- http://se-eng.com

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doe's seabios support retry booting from other disk if boot from one disk failed
by Eli 29 Oct '12

29 Oct '12

hi all: Does anyone know that if seabiso support booting from other disk if boot from one failed ? For instance, the PC BIOS boot specification allows only one disk to be bootable. If boot from disk fails for some reason, the BIOS won't retry booting from other disk. It still can try to boot from floppy or net, though.I want to know that if seabios support retry booting from other disk? Thanks Eli.

4 4

[PATCH v2 0/6] add F11 shortcut for network boot
by Paolo Bonzini 29 Oct '12

29 Oct '12

This series adds a shortcut for network boot, similar to what is present on bare-metal machines. F11 will prioritize BCV/BEV entries for network devices over all the other items of the boot list. After testing with a more recent QEMU I found that it deploys a BCV ROM that breaks network boot. So this series has two extra patches that track the PCI class for boot entries; this is then used to filter boot entries for network boot. A better choice of priorities for BCV and BEV is also implemented (patch 3). After Peter Stuge's prod, I reorganized interactive_bootmenu to use a switch statement, and split the reindentation away in a separate patch. Paolo Paolo Bonzini (6): boot: change definition of IPL_TYPE_* constants boot: track the PCI class of BCV/BEV boot entries boot: bump priority of storage-device option ROMs boot: reorganize interactive_bootmenu boot: wait for key release before continuing boot boot: add F11 shortcut for network boot src/boot.c | 134 ++++++++++++++++++++++++++++++++++++------------------- src/boot.h | 4 +- src/optionroms.c | 8 ++-- 3 file modificati, 94 inserzioni(+), 52 rimozioni(-) -- 1.7.12.1

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[PATCH 0/4] EDID support in bochs vgabios(take 3)
by Hiroshi Miura 28 Oct '12

28 Oct '12

The rework of EDID support in bochs vgabios Now populate EDID block in init You can configure it by CONFIG_VGA_EDID staff. Developer can easily add modes/dtd in bochs_edid_modes[] and bochs_edid_dtds[], and validation code select a best resolution for users. Hiroshi Miura (4): vgasrc: Add skeleton for VBE function 15h (VBE/DDC Standard) add VGA_EDID staff bochsvga: Implement vbe 15h function bochsvga: validate EDID resolution in init Makefile | 3 +- src/vbe.h | 5 ++ vgasrc/Kconfig | 8 +++ vgasrc/bochsedid.c | 193 ++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/bochsedid.h | 143 ++++++++++++++++++++++++++++++++++++++ vgasrc/bochsvga.c | 9 ++- vgasrc/stdvga.c | 11 +++ vgasrc/stdvga.h | 2 + vgasrc/vbe.c | 39 +++++++++++ vgasrc/vgahw.h | 13 ++++ 10 files changed, 424 insertions(+), 2 deletions(-) create mode 100644 vgasrc/bochsedid.c create mode 100644 vgasrc/bochsedid.h -- 1.7.9.5

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