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Re: [SeaBIOS] [Qemu-devel] [RFC PATCH v4 13/30] piix_pci and pc_piix: refactor
by Vasilis Liaskovitis 16 Jan '13

16 Jan '13

Hi, On Wed, Jan 16, 2013 at 03:20:40PM +0800, Hu Tao wrote: > Hi Vasilis, > > On Tue, Dec 18, 2012 at 01:41:41PM +0100, Vasilis Liaskovitis wrote: > > Refactor code so that chipset initialization is similar to q35. This will > > allow memory map initialization at chipset qdev init time for both > > machines, as well as more similar code structure overall. > > > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > > --- > > hw/pc_piix.c | 57 ++++++++++++--- > > hw/piix_pci.c | 225 ++++++++++++++------------------------------------------- > > 2 files changed, 100 insertions(+), 182 deletions(-) > > > > diff --git a/hw/pc_piix.c b/hw/pc_piix.c > > index 19e342a..6a9b508 100644 > > --- a/hw/pc_piix.c > > +++ b/hw/pc_piix.c > > @@ -47,6 +47,7 @@ > > #ifdef CONFIG_XEN > > # include <xen/hvm/hvm_info_table.h> > > #endif > > +#include "piix_pci.h" > > Can't find this file. Did you forget to add this file to git? sorry, you are right. Below is the corrected patch with the missing header Refactor code so that chipset initialization is similar to q35. This will allow memory map initialization at chipset qdev init time for both machines, as well as more similar code structure overall. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/pc_piix.c | 57 ++++++++++++--- hw/piix_pci.c | 225 ++++++++++++++------------------------------------------- hw/piix_pci.h | 116 +++++++++++++++++++++++++++++ 3 files changed, 216 insertions(+), 182 deletions(-) create mode 100644 hw/piix_pci.h diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 19e342a..6a9b508 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -47,6 +47,7 @@ #ifdef CONFIG_XEN # include <xen/hvm/hvm_info_table.h> #endif +#include "piix_pci.h" #define MAX_IDE_BUS 2 @@ -85,6 +86,8 @@ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *pci_memory; MemoryRegion *rom_memory; void *fw_cfg = NULL; + I440FXState *i440fx_host; + PIIX3State *piix3; pc_cpus_init(cpu_model); @@ -127,21 +130,53 @@ static void pc_init1(MemoryRegion *system_memory, } if (pci_enabled) { - pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, - system_memory, system_io, ram_size, - below_4g_mem_size, - 0x100000000ULL - below_4g_mem_size, - 0x100000000ULL + above_4g_mem_size, - (sizeof(hwaddr) == 4 - ? 0 - : ((uint64_t)1 << 62)), - pci_memory, ram_memory); + i440fx_host = I440FX_HOST_DEVICE(qdev_create(NULL, + TYPE_I440FX_HOST_DEVICE)); + i440fx_host->mch.ram_memory = ram_memory; + i440fx_host->mch.pci_address_space = pci_memory; + i440fx_host->mch.system_memory = get_system_memory(); + i440fx_host->mch.address_space_io = get_system_io();; + i440fx_host->mch.below_4g_mem_size = below_4g_mem_size; + i440fx_host->mch.above_4g_mem_size = above_4g_mem_size; + + qdev_init_nofail(DEVICE(i440fx_host)); + i440fx_state = &i440fx_host->mch; + pci_bus = i440fx_host->parent_obj.bus; + /* Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. */ + if (xen_enabled()) { + piix3 = DO_UPCAST(PIIX3State, dev, + pci_create_simple_multifunction(pci_bus, -1, true, + "PIIX3-xen")); + pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, + piix3, XEN_PIIX_NUM_PIRQS); + } else { + piix3 = DO_UPCAST(PIIX3State, dev, + pci_create_simple_multifunction(pci_bus, -1, true, + "PIIX3")); + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, piix3, + PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); + } + piix3->pic = gsi; + isa_bus = DO_UPCAST(ISABus, qbus, + qdev_get_child_bus(&piix3->dev.qdev, "isa.0")); + + piix3_devfn = piix3->dev.devfn; + + ram_size = ram_size / 8 / 1024 / 1024; + if (ram_size > 255) { + ram_size = 255; + } + i440fx_state->dev.config[0x57] = ram_size; } else { pci_bus = NULL; - i440fx_state = NULL; isa_bus = isa_bus_new(NULL, system_io); no_hpet = 1; } + isa_bus_irqs(isa_bus, gsi); if (kvm_irqchip_in_kernel()) { @@ -157,7 +192,7 @@ static void pc_init1(MemoryRegion *system_memory, gsi_state->i8259_irq[i] = i8259[i]; } if (pci_enabled) { - ioapic_init_gsi(gsi_state, "i440fx"); + ioapic_init_gsi(gsi_state, NULL); } pc_register_ferr_irq(gsi[13]); diff --git a/hw/piix_pci.c b/hw/piix_pci.c index ba1b3de..7ca3c73 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -31,70 +31,15 @@ #include "range.h" #include "xen.h" #include "pam.h" +#include "piix_pci.h" -/* - * I440FX chipset data sheet. - * http://download.intel.com/design/chipsets/datashts/29054901.pdf - */ - -typedef struct I440FXState { - PCIHostState parent_obj; -} I440FXState; - -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ -#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ -#define XEN_PIIX_NUM_PIRQS 128ULL -#define PIIX_PIRQC 0x60 - -typedef struct PIIX3State { - PCIDevice dev; - - /* - * bitmap to track pic levels. - * The pic level is the logical OR of all the PCI irqs mapped to it - * So one PIC level is tracked by PIIX_NUM_PIRQS bits. - * - * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with - * pic_irq * PIIX_NUM_PIRQS + pirq - */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 -#error "unable to encode pic state in 64bit in pic_levels." -#endif - uint64_t pic_levels; - - qemu_irq *pic; - - /* This member isn't used. Just for save/load compatibility */ - int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; -} PIIX3State; - -struct PCII440FXState { - PCIDevice dev; - MemoryRegion *system_memory; - MemoryRegion *pci_address_space; - MemoryRegion *ram_memory; - MemoryRegion pci_hole; - MemoryRegion pci_hole_64bit; - PAMMemoryRegion pam_regions[13]; - MemoryRegion smram_region; - uint8_t smm_enabled; -}; - - -#define I440FX_PAM 0x59 -#define I440FX_PAM_SIZE 7 -#define I440FX_SMRAM 0x72 - -static void piix3_set_irq(void *opaque, int pirq, int level); -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); static void piix3_write_config_xen(PCIDevice *dev, uint32_t address, uint32_t val, int len); /* return the global irq number corresponding to a given device irq pin. We could also use the bus number to have a more precise mapping. */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) { int slot_addend; slot_addend = (pci_dev->devfn >> 3) - 1; @@ -180,149 +125,86 @@ static const VMStateDescription vmstate_i440fx = { } }; -static int i440fx_pcihost_initfn(SysBusDevice *dev) +static void i440fx_pcihost_initfn(Object *obj) { - PCIHostState *s = PCI_HOST_BRIDGE(dev); + I440FXState *s = I440FX_HOST_DEVICE(obj); + object_initialize(&s->mch, TYPE_I440FX_PCI_DEVICE); + object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); +} - memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s, - "pci-conf-idx", 4); - sysbus_add_io(dev, 0xcf8, &s->conf_mem); - sysbus_init_ioports(&s->busdev, 0xcf8, 4); +static int i440fx_pcihost_init(SysBusDevice *dev) +{ + PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); + I440FXState *s = I440FX_HOST_DEVICE(&dev->qdev); + PCIBus *b; + + memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci, + "pci-conf-idx", 4); + sysbus_add_io(dev, 0xcf8, &pci->conf_mem); + sysbus_init_ioports(&pci->busdev, 0xcf8, 4); + memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci, + "pci-conf-data", 4); - memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s, - "pci-conf-data", 4); - sysbus_add_io(dev, 0xcfc, &s->data_mem); - sysbus_init_ioports(&s->busdev, 0xcfc, 4); + sysbus_add_io(dev, 0xcfc, &pci->data_mem); + sysbus_init_ioports(&pci->busdev, 0xcfc, 4); + + b = pci_bus_new(&s->parent_obj.busdev.qdev, NULL, s->mch.pci_address_space, + s->mch.address_space_io, 0); + s->parent_obj.bus = b; + qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); + qdev_init_nofail(DEVICE(&s->mch)); return 0; } static int i440fx_initfn(PCIDevice *dev) { - PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); + int i; + PCII440FXState *f = DO_UPCAST(PCII440FXState, dev, dev); + hwaddr pci_hole64_size; - d->dev.config[I440FX_SMRAM] = 0x02; + f->dev.config[I440FX_SMRAM] = 0x02; - cpu_smm_register(&i440fx_set_smm, d); - return 0; -} + cpu_smm_register(&i440fx_set_smm, f); -static PCIBus *i440fx_common_init(const char *device_name, - PCII440FXState **pi440fx_state, - int *piix3_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - hwaddr pci_hole_start, - hwaddr pci_hole_size, - hwaddr pci_hole64_start, - hwaddr pci_hole64_size, - MemoryRegion *pci_address_space, - MemoryRegion *ram_memory) -{ - DeviceState *dev; - PCIBus *b; - PCIDevice *d; - PCIHostState *s; - PIIX3State *piix3; - PCII440FXState *f; - unsigned i; - - dev = qdev_create(NULL, "i440FX-pcihost"); - s = PCI_HOST_BRIDGE(dev); - s->address_space = address_space_mem; - b = pci_bus_new(dev, NULL, pci_address_space, - address_space_io, 0); - s->bus = b; - object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); - qdev_init_nofail(dev); - - d = pci_create_simple(b, 0, device_name); - *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); - f = *pi440fx_state; - f->system_memory = address_space_mem; - f->pci_address_space = pci_address_space; - f->ram_memory = ram_memory; + pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : + ((uint64_t)1 << 62)); memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space, - pci_hole_start, pci_hole_size); - memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); + f->below_4g_mem_size, + 0x100000000LL - f->below_4g_mem_size); + memory_region_add_subregion(f->system_memory, f->below_4g_mem_size, + &f->pci_hole); memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64", f->pci_address_space, - pci_hole64_start, pci_hole64_size); + 0x100000000LL + f->above_4g_mem_size, + pci_hole64_size); if (pci_hole64_size) { - memory_region_add_subregion(f->system_memory, pci_hole64_start, + memory_region_add_subregion(f->system_memory, + 0x100000000LL + f->above_4g_mem_size, &f->pci_hole_64bit); } + memory_region_init_alias(&f->smram_region, "smram-region", f->pci_address_space, 0xa0000, 0x20000); memory_region_add_subregion_overlap(f->system_memory, 0xa0000, &f->smram_region, 1); memory_region_set_enabled(&f->smram_region, false); + init_pam(f->ram_memory, f->system_memory, f->pci_address_space, &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); for (i = 0; i < 12; ++i) { init_pam(f->ram_memory, f->system_memory, f->pci_address_space, - &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, + &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } - - /* Xen supports additional interrupt routes from the PCI devices to - * the IOAPIC: the four pins of each PCI device on the bus are also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. */ - if (xen_enabled()) { - piix3 = DO_UPCAST(PIIX3State, dev, - pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); - pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); - } else { - piix3 = DO_UPCAST(PIIX3State, dev, - pci_create_simple_multifunction(b, -1, true, "PIIX3")); - pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, - PIIX_NUM_PIRQS); - pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); - } - piix3->pic = pic; - *isa_bus = DO_UPCAST(ISABus, qbus, - qdev_get_child_bus(&piix3->dev.qdev, "isa.0")); - - *piix3_devfn = piix3->dev.devfn; - - ram_size = ram_size / 8 / 1024 / 1024; - if (ram_size > 255) - ram_size = 255; - (*pi440fx_state)->dev.config[0x57]=ram_size; - + f->dev.config[0x57] = f->below_4g_mem_size; i440fx_update_memory_mappings(f); - return b; -} - -PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - hwaddr pci_hole_start, - hwaddr pci_hole_size, - hwaddr pci_hole64_start, - hwaddr pci_hole64_size, - MemoryRegion *pci_memory, MemoryRegion *ram_memory) - -{ - PCIBus *b; - - b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic, - address_space_mem, address_space_io, ram_size, - pci_hole_start, pci_hole_size, - pci_hole64_start, pci_hole64_size, - pci_memory, ram_memory); - return b; + return 0; } /* PIIX3 PCI to ISA bridge */ -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { qemu_set_irq(piix3->pic[pic_irq], !!(piix3->pic_levels & @@ -347,13 +229,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) piix3_set_irq_pic(piix3, pic_irq); } -static void piix3_set_irq(void *opaque, int pirq, int level) +void piix3_set_irq(void *opaque, int pirq, int level) { PIIX3State *piix3 = opaque; piix3_set_irq_level(piix3, pirq, level); } -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) +PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 = opaque; int irq = piix3->dev.config[PIIX_PIRQC + pin]; @@ -550,7 +432,7 @@ static void i440fx_class_init(ObjectClass *klass, void *data) } static const TypeInfo i440fx_info = { - .name = "i440FX", + .name = TYPE_I440FX_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCII440FXState), .class_init = i440fx_class_init, @@ -561,15 +443,16 @@ static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = i440fx_pcihost_initfn; + k->init = i440fx_pcihost_init; dc->fw_name = "pci"; dc->no_user = 1; } static const TypeInfo i440fx_pcihost_info = { - .name = "i440FX-pcihost", + .name = TYPE_I440FX_HOST_DEVICE, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(I440FXState), + .instance_init = i440fx_pcihost_initfn, .class_init = i440fx_pcihost_class_init, }; diff --git a/hw/piix_pci.h b/hw/piix_pci.h new file mode 100644 index 0000000..26b3fa0 --- /dev/null +++ b/hw/piix_pci.h @@ -0,0 +1,116 @@ +/* + * piix_pci.h + * + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> + * VA Linux Systems Japan K.K. + * Copyright (C) 2012 Jason Baron <jbaron(a)redhat.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/> + */ + +#ifndef HW_I440FX_H +#define HW_I440FX_H + +#include "hw.h" +#include "range.h" +#include "isa.h" +#include "sysbus.h" +#include "pc.h" +#include "apm.h" +#include "apic.h" +#include "pci.h" +#include "pcie_host.h" +#include "acpi.h" +#include "pam.h" +#include "dimm.h" + +/* + * I440FX chipset data sheet. + * http://download.intel.com/design/chipsets/datashts/29054901.pdf + */ +#define I440FX_PCI_HOLE_START 0xe0000000 + +#define TYPE_I440FX_HOST_DEVICE "i440FX-pcihost" +#define I440FX_HOST_DEVICE(obj) \ + OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_HOST_DEVICE) + +#define TYPE_I440FX_PCI_DEVICE "i440FX" +#define I440FX_PCI_DEVICE(obj) \ + OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) + +typedef struct PCII440FXState { + PCIDevice dev; + MemoryRegion *system_memory; + MemoryRegion *pci_address_space; + MemoryRegion *ram_memory; + MemoryRegion *address_space_io; + PAMMemoryRegion pam_regions[13]; + MemoryRegion pci_hole; + MemoryRegion pci_hole_64bit; + MemoryRegion smram_region; + uint8_t smm_enabled; + ram_addr_t below_4g_mem_size; + ram_addr_t above_4g_mem_size; + /* i440fx allows for 1 DRAM channels x 8 DRAM ranks */ + DimmBus *dram_channel0; + /* paravirtual memory bus */ + DimmBus *pv_dram_channel; + void *fw_cfg; +} PCII440FXState; + +typedef struct I440FXState { + PCIHostState parent_obj; + PCII440FXState mch; +} I440FXState; + +#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ +#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ +#define XEN_PIIX_NUM_PIRQS 128ULL +#define PIIX_PIRQC 0x60 + +typedef struct PIIX3State { + PCIDevice dev; + + /* + * bitmap to track pic levels. + * The pic level is the logical OR of all the PCI irqs mapped to it + * So one PIC level is tracked by PIIX_NUM_PIRQS bits. + * + * PIRQ is mapped to PIC pins, we track it by + * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with + * pic_irq * PIIX_NUM_PIRQS + pirq + */ +#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#error "unable to encode pic state in 64bit in pic_levels." +#endif + uint64_t pic_levels; + + qemu_irq *pic; + + /* This member isn't used. Just for save/load compatibility */ + int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; +} PIIX3State; + + +int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx); +void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq); +void piix3_set_irq(void *opaque, int pirq, int level); +PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); +hwaddr i440fx_pmc_dimm_offset(DeviceState *dev, uint64_t size); + +#define I440FX_PAM 0x59 +#define I440FX_PAM_SIZE 7 +#define I440FX_SMRAM 0x72 + +#endif /* HW_I440FX_H */ -- 1.7.9

1 0

[RfC PATCH 0/2] move apci ports
by Gerd Hoffmann 15 Jan '13

15 Jan '13

Hi, Currently the acpi (+smbios) io regions are in the middle of the addres space: At 0xb000 and 0xb100. And we start allocating I/O ports at 0xc000. piix additionally has some magic io ports (for cpu + pci hotplug) between 0xae00 and 0xaffff. For q35 I'd like to move the acpi ports out if the way, so we can start allocating io ports at 0x2000 and use the whole 0x2000 -> 0xffff range. This patch series does just that. There is one problem with that though (as you might have guessed from the 'RfC' tag): To simplify things the acpi port move is done for both piix and q35, even though it doesn't buy us much on piix due to the hotplug ports. Programming the piix smbios base register was broken in qemu until very recently (1.4 will be the first release with this fixed). Bummer. So what are our options? (1) Set ACPI_PM_BASE at runtime, continue to use 0xb000 for piix. I'd prefer that one. Looks non-trivial due to apci dependencies and src/smm.c though. (2) Make ACPI_PM_BASE a config option, so we can leave it at 0xb000 by default and allow switching to 0x1000 manually if we know qemu is new enougth to handle it properly. acpi dependency is still there, but as we pipe the aml through cpp anyway it shouldn't be that bad. (3) Your bright idea? cheers, Gerd Gerd Hoffmann (2): move ACPI_PM_BASE from 0xb000 to 0x1000 q35: allocate from ioports from 0x2000 up src/ioport.h | 4 ++-- src/pciinit.c | 6 +++++- src/ssdt-proc.dsl | 2 +- 3 files changed, 8 insertions(+), 4 deletions(-)

2 4

[PATCH RFC] Quite hacky patch to get USB ehci working on bare metal.
by Christian Gmeiner 15 Jan '13

15 Jan '13

Some results can be found here: http://dpaste.com/876523/ Before this patch I got a timeout at Inquiry. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/usb-ehci.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/src/usb-ehci.c b/src/usb-ehci.c index 2676615..0b71935 100644 --- a/src/usb-ehci.c +++ b/src/usb-ehci.c @@ -173,6 +173,34 @@ check_ehci_ports(struct usb_ehci_s *cntl) return hub.devcount; } +static int ehci_set_async_schedule(struct usb_ehci_s *ehcic, int enable) +{ + dprintf(7, "%s: enable %d\n", __func__, enable); + + // Set async schedule status. + u32 cmd = readl(&ehcic->regs->usbcmd); + if (enable) + cmd |= CMD_ASE; + else + cmd &= ~CMD_ASE; + + writel(&ehcic->regs->usbcmd, cmd); + + /* Wait for the controller to accept async schedule status. + * This shouldn't take too long, but we should timeout nevertheless. + */ + enable = enable ? STS_ASS : 0; + int timeout = 100; /* time out after 100ms */ + while (((readl(&ehcic->regs->usbsts) & STS_ASS) != enable) + && timeout--) + mdelay(1); + if (timeout < 0) { + dprintf(7, "ehci async schedule status change timed out.\n"); + return 1; + } + return 0; +} + /**************************************************************** * Setup @@ -410,6 +438,8 @@ ehci_desc2pipe(struct ehci_pipe *pipe, struct usbdevice_s *usbdev | QH_TOGGLECONTROL); else if (eptype == USB_ENDPOINT_XFER_INT) pipe->qh.info2 |= (0x01 << QH_SMASK_SHIFT) | (0x1c << QH_CMASK_SHIFT); + else if (eptype == USB_ENDPOINT_XFER_BULK) + pipe->qh.info1 |= QH_TOGGLECONTROL; } static struct usb_pipe * @@ -561,6 +591,9 @@ ehci_wait_td(struct ehci_pipe *pipe, struct ehci_qtd *td, int timeout) static int fillTDbuffer(struct ehci_qtd *td, u16 maxpacket, const void *buf, int bytes) { + dprintf(1, "%s\t", __func__); + hexdump(buf, bytes); + u32 dest = (u32)buf; u32 *pos = td->buf; while (bytes) { @@ -649,9 +682,19 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize) if (! CONFIG_USB_EHCI) return -1; struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe); - dprintf(7, "ehci_send_bulk qh=%p dir=%d data=%p size=%d\n" + dprintf(1, "ehci_send_bulk qh=%p dir=%d data=%p size=%d\n" , &pipe->qh, dir, data, datasize); + dprintf(1, "data:"); + hexdump(data, datasize); + + + struct usb_ehci_s *ehcic = container_of( + GET_LOWFLAT(pipe->pipe.cntl), struct usb_ehci_s, usb); + + // stop async schedule + ehci_set_async_schedule(ehcic, 0); + // Allocate 4 tds on stack (with required alignment) u8 tdsbuf[sizeof(struct ehci_qtd) * STACKQTDS + EHCI_QTD_ALIGN - 1]; struct ehci_qtd *tds = (void*)ALIGN((u32)tdsbuf, EHCI_QTD_ALIGN); @@ -661,12 +704,17 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize) u16 maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket); int tdpos = 0; + struct ehci_qtd *last = &tds[0]; + int num = 0; + int chgm; + while (datasize) { struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; +/* int ret = ehci_wait_td(pipe, td, 5000); if (ret) return -1; - +*/ struct ehci_qtd *nexttd_fl = MAKE_FLATPTR(GET_SEG(SS) , &tds[tdpos % STACKQTDS]); @@ -677,9 +725,29 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize) td->token = (ehci_explen(transfer) | QTD_STS_ACTIVE | (dir ? QTD_PID_IN : QTD_PID_OUT) | ehci_maxerr(3)); + /* dump td buf */ + dprintf(1, "td #%d buf\t", num); + for (chgm = 0; chgm < ARRAY_SIZE(td->buf); chgm++) { + dprintf(1, "\tpointer %d: 0x%08x\n", chgm, td->buf[chgm]); + + if (td->buf[chgm] != 0) { + hexdump((const void *)td->buf[chgm], transfer); + } + } + data += transfer; datasize -= transfer; + num++; } + + dprintf(1, "ehci_send_bulk needs %d td's\n", num); + + /* update based on endpoint toggle */ + tds[0].token |= (pipe->pipe.toogle?QTD_TOGGLE:0); + pipe->qh.token|= (pipe->pipe.toogle?QTD_TOGGLE:0); + + ehci_set_async_schedule(ehcic, 1); + int i; for (i=0; i<STACKQTDS; i++) { struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; @@ -688,6 +756,11 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize) return -1; } + ehci_set_async_schedule(ehcic, 0); + + /* update endpoint toggle based on device */ + pipe->pipe.toogle = (last->token & QTD_TOGGLE) >> 31; + return 0; } -- 1.7.12.2.421.g261b511

2 2

[PATCH RFC] usb-ehci: maintain toggle state
by Christian Gmeiner 15 Jan '13

15 Jan '13

This fixes/improves the ehci driver on bare metal. The current logic in ehci_send_bulk(..) looks wired... but he.. this patch is RFC :) Before patch: Option rom sizing returned 0 0 \0f7a6000/ End thread \0f7a4000/ End thread \0f7a3000/ End thread |0f7a2000| ata_reset exit status=50 |0f7a2000| send_cmd : read error (status=51 err=04) |0f7a2000| ata0-0: SFCF4096H3BK2SA-I-Q1-233-SMA ATA-5 Hard-Disk (3919 MiBytes) |0f7a2000| Registering bootable: ata0-0: SFCF4096H3BK2SA-I-Q1-233-SMA ATA-5 Hard-Disk (3919 MiBytes) (type:2 prio:103 data:fdb10) |0f7a2000| ata_detect resetresult=604f \0f7a2000/ End thread |0f7a5000| set_address 0x0f7a8d10 |0f7a5000| ehci_control 0x0f7a8950 (dir=0 cmd=8 data=0) |0f7a5000| config_usb: 0x0f7a8950 |0f7a5000| ehci_control 0x0f7a8950 (dir=128 cmd=8 data=8) |0f7a5000| device rev=0200 cls=00 sub=00 proto=00 size=40 |0f7a5000| ehci_control 0x0f7a8950 (dir=128 cmd=8 data=9) |0f7a5000| ehci_control 0x0f7a8950 (dir=128 cmd=8 data=39) |0f7a5000| ehci_control 0x0f7a8950 (dir=0 cmd=8 data=0) |0f7a5000| ehci_control 0x0f7a8950 (dir=128 cmd=8 data=1) |0f7a5000| WARNING - Timeout at ehci_wait_td:544! |0f7a5000| ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=f7a5c80 td=0x0f7a5c80 status=d0d80 |0f7a5000| USB transmission failed |0f7a5000| Unable to configure USB MSC drive. |0f7a5000| Unable to configure USB MSC device. \0f7a5000/ End thread \0f7a7000/ End thread All threads complete. Mapping hd drive 0x000fdb10 to 0 drive 0x000fdb10: PCHS=7964/16/63 translation=large LCHS=995/128/63 s=8027712 finalize PMM malloc finalize Space available for UMB: 000c0000-000ef000 usb transfer log: http://dpaste.com/869037/ After patch: \0f7a6000/ End thread \0f7a4000/ End thread \0f7a3000/ End thread |0f7a2000| ata_reset exit status=50 |0f7a2000| send_cmd : read error (status=51 err=04) |0f7a2000| ata0-0: SFCF4096H3BK2SA-I-Q1-233-SMA ATA-5 Hard-Disk (3919 MiBytes) |0f7a2000| Registering bootable: ata0-0: SFCF4096H3BK2SA-I-Q1-233-SMA ATA-5 Hard-Disk (3919 MiBytes) (type:2 prio:103 data:fdb10) |0f7a2000| ata_detect resetresult=604f \0f7a2000/ End thread |0f7a5000| set_address 0x0f7a8ce0 |0f7a5000| ehci_control 0x0f7a88d0 (dir=0 cmd=8 data=0) |0f7a5000| config_usb: 0x0f7a88d0 |0f7a5000| ehci_control 0x0f7a88d0 (dir=128 cmd=8 data=8) |0f7a5000| device rev=0200 cls=00 sub=00 proto=00 size=40 |0f7a5000| ehci_control 0x0f7a88d0 (dir=128 cmd=8 data=9) |0f7a5000| ehci_control 0x0f7a88d0 (dir=128 cmd=8 data=39) |0f7a5000| ehci_control 0x0f7a88d0 (dir=0 cmd=8 data=0) |0f7a5000| ehci_control 0x0f7a88d0 (dir=128 cmd=8 data=1) |0f7a5000| USB MSC vendor='' product='STD USB 1GB' rev='0.00' type=0 removable=1 |0f7a5000| scsi_is_ready (drive=0x000fdae0) |0f7a5000| USB MSC blksize=512 sectors=2005575 |0f7a5000| Registering bootable: USB MSC Drive STD USB 1GB 0.00 (type:2 prio:103 data:fdae0) \0f7a5000/ End thread \0f7a7000/ End thread All threads complete. Mapping hd drive 0x000fdb10 to 0 drive 0x000fdb10: PCHS=7964/16/63 translation=large LCHS=995/128/63 s=8027712 Mapping hd drive 0x000fdae0 to 1 drive 0x000fdae0: PCHS=0/0/0 translation=lba LCHS=994/32/63 s=2005575 finalize PMM malloc finalize ubs transfer log: http://dpaste.com/869023/ Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/usb-ehci.c | 15 ++++++++++++++- src/usb.h | 1 + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/usb-ehci.c b/src/usb-ehci.c index 2676615..3eefd85 100644 --- a/src/usb-ehci.c +++ b/src/usb-ehci.c @@ -410,6 +410,8 @@ ehci_desc2pipe(struct ehci_pipe *pipe, struct usbdevice_s *usbdev | QH_TOGGLECONTROL); else if (eptype == USB_ENDPOINT_XFER_INT) pipe->qh.info2 |= (0x01 << QH_SMASK_SHIFT) | (0x1c << QH_CMASK_SHIFT); + else if (eptype == USB_ENDPOINT_XFER_BULK) + pipe->qh.info1 |= QH_TOGGLECONTROL; } static struct usb_pipe * @@ -661,12 +663,15 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize) u16 maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket); int tdpos = 0; + struct ehci_qtd *last = &tds[0]; + while (datasize) { struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; +/* int ret = ehci_wait_td(pipe, td, 5000); if (ret) return -1; - +*/ struct ehci_qtd *nexttd_fl = MAKE_FLATPTR(GET_SEG(SS) , &tds[tdpos % STACKQTDS]); @@ -680,6 +685,11 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize) data += transfer; datasize -= transfer; } + + /* update based on endpoint toggle */ + tds[0].token |= (pipe->pipe.toogle?QTD_TOGGLE:0); + pipe->qh.token|= (pipe->pipe.toogle?QTD_TOGGLE:0); + int i; for (i=0; i<STACKQTDS; i++) { struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS]; @@ -688,6 +698,9 @@ ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize) return -1; } + /* update endpoint toggle based on device */ + pipe->pipe.toogle = (last->token & QTD_TOGGLE) >> 31; + return 0; } diff --git a/src/usb.h b/src/usb.h index a43e829..d272306 100644 --- a/src/usb.h +++ b/src/usb.h @@ -14,6 +14,7 @@ struct usb_pipe { u8 ep; u8 devaddr; u8 speed; + u8 toogle; u16 maxpacket; u8 eptype; }; -- 1.7.12.2.421.g261b511

1 1

handle_hwpic1 irq=0 - what's going on?
by Christian Gmeiner 14 Jan '13

14 Jan '13

All threads complete. Mapping hd drive 0x000fdb10 to 0 drive 0x000fdb10: PCHS=0/0/0 translation=lba LCHS=974/255/63 s=15663104 finalize PMM malloc finalize Space available for UMB: 000c0000-000ef000 Returned 57344 bytes of ZoneHigh e820 map has 5 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000000f7be000 = 1 RAM 4: 000000000f7be000 - 000000000f7e0000 = 2 RESERVED Jump to int19 enter handle_19: NULL Booting from Hard Disk... ehci_send_bulk qh=0x000ef680 dir=0 data=0x000eff50 size=31 data: 00000000:handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 handle_hwpic1 irq=0 -- Christian Gmeiner, MSc

1 0

Re: [SeaBIOS] Setting cursor position from initial SeaBIOS boot screen + changing cursor color
by Kevin O'Connor 12 Jan '13

12 Jan '13

On Sat, Jan 12, 2013 at 05:40:19AM -0500, Robert Butler wrote: > As a bit of personal hobby, I've recently started studying SeaBIOS in the > hopes of making it behave in a more "life-like" manner (see: VMware's BIOS). I'm not sure what you are referring to by "life-like". Can you elaborate on the features you'd like to add? > However, I seem to be at > a bit of a loss for where to start looking for information on the API that I > can use inside SeaBIOS, though. Can someone point me in the right direction? > Perhaps someone can link > me to an html page (or PDF, even) or something that gives me an idea what I > can use during BIOS initialization? If you're looking for the BIOS API then I suggest taking a look at Ralph Brown's Interrupt List (RBIL). I have links to that and other resources at: http://www.seabios.org/Developer_links If you're attempting to add code to SeaBIOS, then you can generally just interact directly with the desired functions and variables. > Is there ANY information out there that I can use while doing this? > > I mostly need access to the following: > > * The cursor's x/y position > > * Foreground and background text color These are part of the VGA BIOS - you can look up the interrupt 0x10 functions in RBIL. There's also a vgabios implementation in seabios itself in the vgasrc/ directory. One can get a feel for what's supported by looking through that code. > * Low + Extended memory information Also available via the BIOS interface (see RBIL interrupt 0x15) and internally available via the RamSize variable. > * Installed disk information Available via BIOS interface (see RBIL interrupt 0x13) and via various functions internally (eg, see src/block.c). [...] > --- > This email and any files attached to it may be confidential and intended solely for the use of the individual or entity to whom they are addressed. > If you have received this email in error please notify iss(a)psiglenmere.com. [...] Your email went to a list with wide distribution and multiple archives, so this notice doesn't make any sense. -Kevin

1 0

[PATCH] vgabios: implement AX=1120H..1124H functions
by Paolo Bonzini 12 Jan '13

12 Jan '13

These function only have to set INT 1Fh and INT 43h, and set the BDA height + number of rows. I could not find out whether AX=1120h should also set the character height to 8. I think not, because INT 43h might still point to 14- or 16-pixel high characters and in this case INT 1Fh will not be used at all. Signed-off-by: Paolo Bonzini <pbonzini(a)redhat.com> --- vgasrc/vgabios.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index b13d274..afaf018 100644 --- a/vgasrc/vgabios.c +++ b/vgasrc/vgabios.c @@ -797,6 +797,61 @@ handle_101114(struct bregs *regs) } static void +handle_101120(struct bregs *regs) +{ + SET_IVT(0x1f, SEGOFF(regs->es, regs->bp)); +} + +void +load_gfx_font(u16 seg, u16 off, u8 height, u8 bl, u8 dl) +{ + u8 rows; + + SET_IVT(0x43, SEGOFF(seg, off)); + switch(bl) { + case 0: + rows = dl; + break; + case 1: + rows = 14; + break; + case 3: + rows = 43; + break; + case 2: + default: + rows = 25; + break; + } + SET_BDA(video_rows, rows - 1); + SET_BDA(char_height, height); +} + +static void +handle_101121(struct bregs *regs) +{ + load_gfx_font(regs->es, regs->bp, regs->cx, regs->bl, regs->dl); +} + +static void +handle_101122(struct bregs *regs) +{ + load_gfx_font(get_global_seg(), (u32)vgafont14, 14, regs->bl, regs->dl); +} + +static void +handle_101123(struct bregs *regs) +{ + load_gfx_font(get_global_seg(), (u32)vgafont8, 8, regs->bl, regs->dl); +} + +static void +handle_101124(struct bregs *regs) +{ + load_gfx_font(get_global_seg(), (u32)vgafont16, 16, regs->bl, regs->dl); +} + +static void handle_101130(struct bregs *regs) { switch (regs->bh) { @@ -867,6 +922,11 @@ handle_1011(struct bregs *regs) case 0x12: handle_101112(regs); break; case 0x14: handle_101114(regs); break; case 0x30: handle_101130(regs); break; + case 0x20: handle_101120(regs); break; + case 0x21: handle_101121(regs); break; + case 0x22: handle_101122(regs); break; + case 0x23: handle_101123(regs); break; + case 0x24: handle_101124(regs); break; default: handle_1011XX(regs); break; } } -- 1.8.1

2 3

[Resend][Seabios PATCH] don't boot from un-selected devices
by Amos Kong 12 Jan '13

12 Jan '13

Current seabios will try to boot from selected devices first, if they are all failed, seabios will also try to boot from un-selected devices. For example: @ qemu-kvm -boot order=n,menu=on ... Guest will boot from network first, if it's failed, guest will try to boot from other un-selected devices (floppy, cdrom, disk) one by one. Sometimes, user don't want to boot from some devices. This patch changes seabios to boot only from selected devices. If user choose first boot device from menu, then seabios will try all the devices, even some of them are not selected. Signed-off-by: Amos Kong <akong(a)redhat.com> --- Resend for CCing seabios maillist. --- src/boot.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/boot.c b/src/boot.c index 3ca7960..ee810ac 100644 --- a/src/boot.c +++ b/src/boot.c @@ -424,6 +424,10 @@ interactive_bootmenu(void) maxmenu++; printf("%d. %s\n", maxmenu , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); + /* If user chooses first boot device from menu, we will treat + all the devices as selected. */ + if (pos->priority == DEFAULT_PRIO) + pos->priority = DEFAULT_PRIO - 1; pos = pos->next; } @@ -490,7 +494,10 @@ boot_prep(void) // Map drives and populate BEV list struct bootentry_s *pos = BootList; - while (pos) { + + /* The priority of un-selected device is not changed, + we only boot from user selected devices. */ + while (pos && pos->priority != DEFAULT_PRIO) { switch (pos->type) { case IPL_TYPE_BCV: call_bcv(pos->vector.seg, pos->vector.offset); @@ -513,10 +520,6 @@ boot_prep(void) } pos = pos->next; } - - // If nothing added a floppy/hd boot - add it manually. - add_bev(IPL_TYPE_FLOPPY, 0); - add_bev(IPL_TYPE_HARDDISK, 0); } -- 1.7.1

5 14

Setting cursor position from initial SeaBIOS boot screen + changing cursor color
by Robert Butler 12 Jan '13

12 Jan '13

Good morning/evening/afternoon/night, As a bit of personal hobby, I've recently started studying SeaBIOS in the hopes of making it behave in a more "life-like" manner (see: VMware's BIOS). However, I seem to be at a bit of a loss for where to start looking for information on the API that I can use inside SeaBIOS, though. Can someone point me in the right direction? Perhaps someone can link me to an html page (or PDF, even) or something that gives me an idea what I can use during BIOS initialization? Is there ANY information out there that I can use while doing this? I mostly need access to the following: * The cursor's x/y position * Foreground and background text color * Low + Extended memory information * Installed disk information Is the above information even available to me at start up like that? Thanks in advance! - Robert --- This email and any files attached to it may be confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify iss(a)psiglenmere.com. This message may contain confidential information and is intended only for the individual named. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately by e-mail if you have received this e-mail by mistake and delete this e-mail from your system. If you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited.

1 0

Re: [SeaBIOS] [RFC PATCH v4 00/30] ACPI memory hotplug
by Vasilis Liaskovitis 10 Jan '13

10 Jan '13

> > > > IIRC q35 supports memory hotplug natively (picked up in some > > discussion). Is that correct? > > > From previous discussion I also understand that q35 supports native hotplug. > Sections 5.1 and 5.2 of the spec describe the MCH registers but the native > memory hotplug specifics are not yet clear to me. Any pointers from the > spec are welcome. Ping. Could anyone who's familiar with the q35 spec provide some pointers on native memory hotplug details in the spec? I see pcie hotplug registers but can't find memory hotplug interface details. If I am not mistaken, the spec is here: http://www.intel.com/design/chipsets/datashts/316966.htm Is the q35 memory hotplug support supposed to be an shpc-like interface geared towards memory slots instead of pci slots? thanks, - Vasilis

1 0

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