SeaBIOS

seabios@seabios.org

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3802 discussions

"ata_piix device not availabile cannot reserve io" issue
by Riccardo Schirone 15 Jul '13

15 Jul '13

Hi, i use seabios on qemu with Linux as guest OS and i am not able to boot my machine because kernel says ata_piix 0000:00:01.1: device not available (can't reserve [io 0x0000-0x0007]) i try with qemu v1.5.50 and v.1.4.2 and i have the same error. Bisecting seabios i found that the error was introduced with this commit 76e58028d28e78431f9de3cee0b3c88d807fa39d - acpi: Eliminate BDAT parameter passing to DSDT code. the last good commit is: 3f8d735dd85edc9fc4da8d4018925012a8626877 - Rename src/ssdt-susp.dsl to src/ssdt-misc.dsl.

1 0

[PATCHv2] pci: load memory window setup from host
by Michael S. Tsirkin 15 Jul '13

15 Jul '13

Load memory window setup for pci from host. This makes it possible for host to make sure setup matches hardware exactly: especially important for when ACPI tables are loaded from host. This will also make it easier to add more chipsets down the road. Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- Changes from v1: - fix bug in 64 bit range check - address Kevin's comments: move file load into pciinit.c dont reorder initialization sizeof style fix src/pciinit.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 75 insertions(+), 16 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index bb9355f..a4a5bf5 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -13,6 +13,7 @@ #include "config.h" // CONFIG_* #include "memmap.h" // add_e820 #include "paravirt.h" // RamSize +#include "byteorder.h" // le64_to_cpu #include "dev-q35.h" /* PM Timer ticks per second (HZ) */ @@ -61,6 +62,13 @@ struct pci_bus { struct pci_device *bus_dev; }; +struct pci_mem { + u64 start32; + u64 end32; + u64 start64; + u64 end64; +}; + static u32 pci_bar(struct pci_device *pci, int region_num) { if (region_num != PCI_ROM_SLOT) { @@ -361,6 +369,8 @@ static void pci_enable_default_vga(void) void i440fx_mem_addr_setup(struct pci_device *dev, void *arg) { + if (arg) + /* use supplied memory */; if (RamSize <= 0x80000000) pcimem_start = 0x80000000; else if (RamSize <= 0xc0000000) @@ -383,8 +393,9 @@ void mch_mem_addr_setup(struct pci_device *dev, void *arg) pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower); add_e820(addr, size, E820_RESERVED); - /* setup pci i/o window (above mmconfig) */ - pcimem_start = addr + size; + /* unless done already, setup pci i/o window (above mmconfig) */ + if (!arg) + pcimem_start = addr + size; pci_slot_get_irq = mch_pci_slot_get_irq; } @@ -397,11 +408,11 @@ static const struct pci_device_id pci_platform_tbl[] = { PCI_DEVICE_END }; -static void pci_bios_init_platform(void) +static void pci_bios_init_platform(struct pci_mem *mem) { struct pci_device *pci; foreachpci(pci) { - pci_init_device(pci_platform_tbl, pci, NULL); + pci_init_device(pci_platform_tbl, pci, mem); } } @@ -762,10 +773,14 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) } } -static void pci_bios_map_devices(struct pci_bus *busses) +static void pci_bios_map_devices(struct pci_bus *busses, struct pci_mem *mem) { if (pci_bios_init_root_regions(busses)) { struct pci_region r64_mem, r64_pref; + + if (mem && mem->start64 >= mem->end64) + panic("PCI: out of 32bit address space\n"); + r64_mem.list = NULL; r64_pref.list = NULL; pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM], @@ -781,14 +796,27 @@ static void pci_bios_map_devices(struct pci_bus *busses) u64 align_mem = pci_region_align(&r64_mem); u64 align_pref = pci_region_align(&r64_pref); - r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); - r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); - pcimem64_start = r64_mem.base; - pcimem64_end = r64_pref.base + sum_pref; + if (mem) { + /* + * Non prefetcheable memory at start of the window, + * prefetcheable memory at the end. + * This way OS has the maximum flexibility for + * allocating the rest of the memory. + */ + r64_mem.base = ALIGN(mem->start64, align_mem); + r64_pref.base = ALIGN_DOWN(mem->end64 - sum_pref + 1, align_pref); + if (sum_pref && r64_pref.base < r64_mem.base + sum_mem) + panic("PCI: out of 64bit address space\n"); + } else { + r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); + r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); + pcimem64_start = r64_mem.base; + pcimem64_end = r64_pref.base + sum_pref; + } pci_region_map_entries(busses, &r64_mem); pci_region_map_entries(busses, &r64_pref); - } else { + } else if (!mem) { // no bars mapped high -> drop 64bit window (see dsdt) pcimem64_start = 0; } @@ -801,11 +829,28 @@ static void pci_bios_map_devices(struct pci_bus *busses) } } +static +struct pci_mem *pci_mem_get(void) +{ + int psize; + struct pci_mem *mem = romfile_loadfile("etc/pci-info", &psize); + if (!mem) + return NULL; + if (psize < sizeof(*mem)) { + free(mem); + return NULL; + } + mem->start32 = le64_to_cpu(mem->start32); + mem->end32 = le64_to_cpu(mem->end32); + mem->start64 = le64_to_cpu(mem->start64); + mem->end64 = le64_to_cpu(mem->end64); + return mem; +} + /**************************************************************** * Main setup code ****************************************************************/ - void pci_setup(void) { @@ -823,25 +868,39 @@ pci_setup(void) dprintf(1, "=== PCI device probing ===\n"); pci_probe_devices(); - pcimem_start = RamSize; - pci_bios_init_platform(); + struct pci_mem *mem = pci_mem_get(); + + if (mem) { + pcimem_start = mem->start32; + pcimem_end = mem->end32; + pcimem64_start = mem->start64; + pcimem64_end = mem->end64; + } else { + pcimem_start = RamSize; + } + + pci_bios_init_platform(mem); dprintf(1, "=== PCI new allocation pass #1 ===\n"); struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1)); if (!busses) { warn_noalloc(); - return; + goto done; } memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1)); if (pci_bios_check_devices(busses)) - return; + goto done; dprintf(1, "=== PCI new allocation pass #2 ===\n"); - pci_bios_map_devices(busses); + pci_bios_map_devices(busses, mem); pci_bios_init_devices(); free(busses); pci_enable_default_vga(); + +done: + if (mem) + free(mem); } -- MST

2 4

[PATCH] PIC code cleanups.
by Kevin O'Connor 14 Jul '13

14 Jul '13

Preface PIC functions with a pic_ to provide a more consistent naming. Convert the irqmask code to a more consistent pic_irqmask_read/write/mask form. Move code from pic.h to pic.c. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/clock.c | 6 ++--- src/csm.c | 7 +++--- src/disk.c | 4 +-- src/floppy.c | 4 +-- src/misc.c | 2 +- src/pic.c | 79 +++++++++++++++++++++++++++++++++++++++++----------------- src/pic.h | 80 +++++++++++------------------------------------------------ src/ps2port.c | 6 ++--- src/resume.c | 4 +-- src/system.c | 4 +-- 10 files changed, 90 insertions(+), 106 deletions(-) diff --git a/src/clock.c b/src/clock.c index 5926a07..2eedab8 100644 --- a/src/clock.c +++ b/src/clock.c @@ -9,7 +9,7 @@ #include "util.h" // debug_enter #include "disk.h" // floppy_tick #include "cmos.h" // inb_cmos -#include "pic.h" // eoi_pic1 +#include "pic.h" // pic_eoi1 #include "bregs.h" // struct bregs #include "biosvar.h" // GET_GLOBAL #include "usb-hid.h" // usb_check_event @@ -583,7 +583,7 @@ handle_08(void) br.flags = F_IF; call16_int(0x1c, &br); - eoi_pic1(); + pic_eoi1(); } @@ -746,5 +746,5 @@ handle_70(void) } done: - eoi_pic2(); + pic_eoi2(); } diff --git a/src/csm.c b/src/csm.c index 4336e16..2886bba 100644 --- a/src/csm.c +++ b/src/csm.c @@ -30,10 +30,11 @@ EFI_COMPATIBILITY16_TABLE csm_compat_table VARFSEG __aligned(16) = { .AcpiRsdPtrPointer = (u32)&csm_rsdp, }; - EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table; EFI_TO_COMPATIBILITY16_BOOT_TABLE *csm_boot_table; +static u16 PICMask = PIC_IRQMASK_DEFAULT; + extern void __csm_return(struct bregs *regs) __noreturn; static void @@ -41,7 +42,7 @@ csm_return(struct bregs *regs) { dprintf(3, "handle_csm returning AX=%04x\n", regs->ax); - pic_save_mask(); + PICMask = pic_irqmask_read(); __csm_return(regs); } @@ -271,7 +272,7 @@ handle_csm(struct bregs *regs) dprintf(3, "handle_csm regs %p AX=%04x\n", regs, regs->ax); - pic_restore_mask(); + pic_irqmask_write(PICMask); switch(regs->ax) { case 0000: handle_csm_0000(regs); break; diff --git a/src/disk.c b/src/disk.c index 0291fe3..975d053 100644 --- a/src/disk.c +++ b/src/disk.c @@ -9,7 +9,7 @@ #include "biosvar.h" // SET_BDA #include "config.h" // CONFIG_* #include "util.h" // debug_enter -#include "pic.h" // eoi_pic2 +#include "pic.h" // pic_eoi2 #include "bregs.h" // struct bregs #include "pci.h" // pci_bdf_to_bus #include "ata.h" // ATA_CB_DC @@ -889,7 +889,7 @@ handle_76(void) { debug_isr(DEBUG_ISR_76); SET_BDA(disk_interrupt_flag, 0xff); - eoi_pic2(); + pic_eoi2(); } // Old Fixed Disk Parameter Table (newer tables are in the ebda). diff --git a/src/floppy.c b/src/floppy.c index 62802ba..83dfaf8 100644 --- a/src/floppy.c +++ b/src/floppy.c @@ -11,7 +11,7 @@ #include "biosvar.h" // SET_BDA #include "util.h" // dprintf #include "cmos.h" // inb_cmos -#include "pic.h" // eoi_pic1 +#include "pic.h" // pic_eoi1 #include "bregs.h" // struct bregs #include "boot.h" // boot_add_floppy #include "pci.h" // pci_to_bdf @@ -679,7 +679,7 @@ handle_0e(void) u8 frs = GET_BDA(floppy_recalibration_status); SET_BDA(floppy_recalibration_status, frs | FRS_IRQ); - eoi_pic1(); + pic_eoi1(); } // Called from int08 handler. diff --git a/src/misc.c b/src/misc.c index def31f8..c84cac8 100644 --- a/src/misc.c +++ b/src/misc.c @@ -71,7 +71,7 @@ handle_75(void) // clear irq13 outb(0, PORT_MATH_CLEAR); // clear interrupt - eoi_pic2(); + pic_eoi2(); // legacy nmi call struct bregs br; memset(&br, 0, sizeof(br)); diff --git a/src/pic.c b/src/pic.c index 3e96bb3..9a3ea0b 100644 --- a/src/pic.c +++ b/src/pic.c @@ -5,12 +5,34 @@ // // This file may be distributed under the terms of the GNU LGPLv3 license. -#include "pic.h" // get_pic1_isr +#include "pic.h" // pic_* #include "util.h" // dprintf #include "config.h" // CONFIG_* +#include "biosvar.h" // SET_IVT + +u16 +pic_irqmask_read(void) +{ + return inb(PORT_PIC1_DATA) | (inb(PORT_PIC2_DATA) << 8); +} + +void +pic_irqmask_write(u16 mask) +{ + outb(mask, PORT_PIC1_DATA); + outb(mask >> 8, PORT_PIC2_DATA); +} void -set_pics(u8 irq0, u8 irq8) +pic_irqmask_mask(u16 off, u16 on) +{ + u8 pic1off = off, pic1on = on, pic2off = off>>8, pic2on = on>>8; + outb((inb(PORT_PIC1_DATA) & ~pic1off) | pic1on, PORT_PIC1_DATA); + outb((inb(PORT_PIC2_DATA) & ~pic2off) | pic2on, PORT_PIC2_DATA); +} + +void +pic_reset(u8 irq0, u8 irq8) { // Send ICW1 (select OCW1 + will send ICW4) outb(0x11, PORT_PIC1_CMD); @@ -25,44 +47,55 @@ set_pics(u8 irq0, u8 irq8) outb(0x01, PORT_PIC1_DATA); outb(0x01, PORT_PIC2_DATA); // Mask all irqs (except cascaded PIC2 irq) - outb(~PIC1_IRQ2, PORT_PIC1_DATA); - outb(~0, PORT_PIC2_DATA); + pic_irqmask_write(PIC_IRQMASK_DEFAULT); } void pic_setup(void) { dprintf(3, "init pic\n"); - set_pics(BIOS_HWIRQ0_VECTOR, BIOS_HWIRQ8_VECTOR); + pic_reset(BIOS_HWIRQ0_VECTOR, BIOS_HWIRQ8_VECTOR); } -// Handler for otherwise unused hardware irqs. -void VISIBLE16 -handle_hwpic1(struct bregs *regs) +void +enable_hwirq(int hwirq, struct segoff_s func) { - dprintf(DEBUG_ISR_hwpic1, "handle_hwpic1 irq=%x\n", get_pic1_isr()); - eoi_pic1(); + pic_irqmask_mask(1 << hwirq, 0); + int vector; + if (hwirq < 8) + vector = BIOS_HWIRQ0_VECTOR + hwirq; + else + vector = BIOS_HWIRQ8_VECTOR + hwirq - 8; + SET_IVT(vector, func); } -void VISIBLE16 -handle_hwpic2(struct bregs *regs) +static u8 +pic_isr1_read(void) { - dprintf(DEBUG_ISR_hwpic2, "handle_hwpic2 irq=%x\n", get_pic2_isr()); - eoi_pic2(); + // 0x0b == select OCW1 + read ISR + outb(0x0b, PORT_PIC1_CMD); + return inb(PORT_PIC1_CMD); } -u8 saved_pic_mask[2] = { ~PIC1_IRQ2, ~0 }; +static u8 +pic_isr2_read(void) +{ + // 0x0b == select OCW1 + read ISR + outb(0x0b, PORT_PIC2_CMD); + return inb(PORT_PIC2_CMD); +} -void -pic_save_mask(void) +// Handler for otherwise unused hardware irqs. +void VISIBLE16 +handle_hwpic1(struct bregs *regs) { - saved_pic_mask[0] = inb(PORT_PIC1_DATA); - saved_pic_mask[1] = inb(PORT_PIC2_DATA); + dprintf(DEBUG_ISR_hwpic1, "handle_hwpic1 irq=%x\n", pic_isr1_read()); + pic_eoi1(); } -void -pic_restore_mask(void) +void VISIBLE16 +handle_hwpic2(struct bregs *regs) { - outb(saved_pic_mask[0], PORT_PIC1_DATA); - outb(saved_pic_mask[1], PORT_PIC2_DATA); + dprintf(DEBUG_ISR_hwpic2, "handle_hwpic2 irq=%x\n", pic_isr2_read()); + pic_eoi2(); } diff --git a/src/pic.h b/src/pic.h index 92cb870..19aecba 100644 --- a/src/pic.h +++ b/src/pic.h @@ -8,7 +8,7 @@ #define __PIC_H #include "ioport.h" // PORT_PIC* -#include "biosvar.h" // SET_IVT +#include "farptr.h" // struct segoff_s // PORT_PIC1 bitdefs #define PIC1_IRQ0 (1<<0) @@ -17,86 +17,36 @@ #define PIC1_IRQ5 (1<<5) #define PIC1_IRQ6 (1<<6) // PORT_PIC2 bitdefs -#define PIC2_IRQ8 (1<<0) -#define PIC2_IRQ12 (1<<4) -#define PIC2_IRQ13 (1<<5) -#define PIC2_IRQ14 (1<<6) +#define PIC2_IRQ8 (1<<8) +#define PIC2_IRQ12 (1<<12) +#define PIC2_IRQ13 (1<<13) +#define PIC2_IRQ14 (1<<14) + +#define PIC_IRQMASK_DEFAULT ((u16)~PIC1_IRQ2) #define BIOS_HWIRQ0_VECTOR 0x08 #define BIOS_HWIRQ8_VECTOR 0x70 static inline void -eoi_pic1(void) +pic_eoi1(void) { // Send eoi (select OCW2 + eoi) outb(0x20, PORT_PIC1_CMD); } static inline void -eoi_pic2(void) +pic_eoi2(void) { // Send eoi (select OCW2 + eoi) outb(0x20, PORT_PIC2_CMD); - eoi_pic1(); -} - -static inline void -unmask_pic1(u8 irq) -{ - outb(inb(PORT_PIC1_DATA) & ~irq, PORT_PIC1_DATA); -} - -static inline void -unmask_pic2(u8 irq) -{ - outb(inb(PORT_PIC2_DATA) & ~irq, PORT_PIC2_DATA); -} - -static inline void -mask_pic1(u8 irq) -{ - outb(inb(PORT_PIC1_DATA) | irq, PORT_PIC1_DATA); -} - -static inline void -mask_pic2(u8 irq) -{ - outb(inb(PORT_PIC2_DATA) | irq, PORT_PIC2_DATA); -} - -static inline u8 -get_pic1_isr(void) -{ - // 0x0b == select OCW1 + read ISR - outb(0x0b, PORT_PIC1_CMD); - return inb(PORT_PIC1_CMD); -} - -static inline u8 -get_pic2_isr(void) -{ - // 0x0b == select OCW1 + read ISR - outb(0x0b, PORT_PIC2_CMD); - return inb(PORT_PIC2_CMD); -} - -static inline void -enable_hwirq(int hwirq, struct segoff_s func) -{ - int vector; - if (hwirq < 8) { - unmask_pic1(1 << hwirq); - vector = BIOS_HWIRQ0_VECTOR + hwirq; - } else { - unmask_pic2(1 << (hwirq - 8)); - vector = BIOS_HWIRQ8_VECTOR + hwirq - 8; - } - SET_IVT(vector, func); + pic_eoi1(); } -void set_pics(u8 irq0, u8 irq8); +u16 pic_irqmask_read(void); +void pic_irqmask_write(u16 mask); +void pic_irqmask_mask(u16 off, u16 on); +void pic_reset(u8 irq0, u8 irq8); void pic_setup(void); -void pic_save_mask(void); -void pic_restore_mask(void); +void enable_hwirq(int hwirq, struct segoff_s func); #endif // pic.h diff --git a/src/ps2port.c b/src/ps2port.c index 9b760fd..cfcd5eb 100644 --- a/src/ps2port.c +++ b/src/ps2port.c @@ -9,7 +9,7 @@ #include "util.h" // dprintf #include "biosvar.h" // GET_LOW #include "ps2port.h" // ps2_kbd_command -#include "pic.h" // eoi_pic1 +#include "pic.h" // pic_eoi1 /**************************************************************** @@ -378,7 +378,7 @@ handle_74(void) process_mouse(v); done: - eoi_pic2(); + pic_eoi2(); } // INT09h : Keyboard Hardware Service Entry Point @@ -408,7 +408,7 @@ handle_09(void) i8042_command(I8042_CMD_KBD_ENABLE, NULL); done: - eoi_pic1(); + pic_eoi1(); } diff --git a/src/resume.c b/src/resume.c index 9466480..48e1bd8 100644 --- a/src/resume.c +++ b/src/resume.c @@ -6,7 +6,7 @@ #include "util.h" // dprintf #include "ioport.h" // outb -#include "pic.h" // eoi_pic2 +#include "pic.h" // pic_eoi2 #include "biosvar.h" // struct bios_data_area_s #include "bregs.h" // struct bregs #include "acpi.h" // find_resume_vector @@ -49,7 +49,7 @@ handle_resume(void) case 0x05: // flush keyboard (issue EOI) and jump via 40h:0067h - eoi_pic2(); + pic_eoi2(); // NO BREAK case 0x0a: #define BDA_JUMP (((struct bios_data_area_s *)0)->jump) diff --git a/src/system.c b/src/system.c index 7b481a8..3c815b3 100644 --- a/src/system.c +++ b/src/system.c @@ -9,7 +9,7 @@ #include "biosvar.h" // BIOS_CONFIG_TABLE #include "ioport.h" // inb #include "memmap.h" // E820_RAM -#include "pic.h" // eoi_pic2 +#include "pic.h" // pic_reset #include "bregs.h" // struct bregs // Use PS2 System Control port A to set A20 enable @@ -191,7 +191,7 @@ handle_1589(struct bregs *regs) { set_a20(1); - set_pics(regs->bl, regs->bh); + pic_reset(regs->bl, regs->bh); u64 *gdt_far = (void*)(regs->si + 0); u16 gdt_seg = regs->es; -- 1.7.11.7

1 0

Commit b98a4b1 prevents USB drives from being detected
by Dave Frodin 14 Jul '13

14 Jul '13

I'm using the current seabios (master or stable) as a payload for coreboot. If I build the current seabios I've found that commit b98a4b1 "Convert PCIDevices list to use standard list manipultion code." prevents the system from finding USB thumbdrives. The USB keyboard and mouse still work. This problem occurs for multiple mainboards (persimmon/parmer/gizmo). Let me know if there's something else I can try for anybody. Thanks, Dave

2 1

Re: [SeaBIOS] [Qemu-devel] [PATCH v5 5/7] acpi: generate hotplug memory devices
by Igor Mammedov 12 Jul '13

12 Jul '13

On Wed, 26 Jun 2013 17:15:03 +0800 Hu Tao <hutao(a)cn.fujitsu.com> wrote: > The memory device generation is guided by qemu paravirt info. Seabios > uses the info to setup SRAT entries for the hotplug-able memory slots, > and to generate appropriate memory device objects. One memory device > (and corresponding SRAT entry) is generated for each hotplug-able qemu > memslot. Currently no SSDT memory device is created for initial system > memory. > > We only support up to 255 DIMMs for now (PackageOp used for the MEON > array can only describe an array of at most 255 elements. VarPackageOp > would be needed to support more than 255 devices) > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > Signed-off-by: Hu Tao <hutao(a)cn.fujitsu.com> > --- > src/acpi.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--- > src/paravirt.c | 8 +++ > 2 files changed, 152 insertions(+), 7 deletions(-) > > diff --git a/src/acpi.c b/src/acpi.c > index ce988e0..e9a0326 100644 > --- a/src/acpi.c > +++ b/src/acpi.c > @@ -15,6 +15,8 @@ > #include "config.h" // CONFIG_* > #include "paravirt.h" // RamSize > #include "dev-q35.h" > +#include "memmap.h" > +#include "paravirt.h" > > #include "acpi-dsdt.hex" > > @@ -250,11 +252,23 @@ encodeLen(u8 *ssdt_ptr, int length, int bytes) > #define PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start) > #define PCI_SLOTS 32 > > +/* 0x5B 0x82 DeviceOp PkgLength NameString DimmID */ > +#define MEM_BASE 0xaf80 > +#define MEM_AML (ssdm_mem_aml + *ssdt_mem_start) > +#define MEM_SIZEOF (*ssdt_mem_end - *ssdt_mem_start) > +#define MEM_OFFSET_HEX (*ssdt_mem_name - *ssdt_mem_start + 2) > +#define MEM_OFFSET_ID (*ssdt_mem_id - *ssdt_mem_start) > +#define MEM_OFFSET_PXM 31 > +#define MEM_OFFSET_START 55 > +#define MEM_OFFSET_END 63 > +#define MEM_OFFSET_SIZE 79 > + > #define SSDT_SIGNATURE 0x54445353 // SSDT > #define SSDT_HEADER_LENGTH 36 > > #include "ssdt-misc.hex" > #include "ssdt-pcihp.hex" > +#include "ssdt-mem.hex" > > #define PCI_RMV_BASE 0xae0c > > @@ -306,9 +320,100 @@ static void patch_pcihp(int slot, u8 *ssdt_ptr, u32 eject) > } > } > > +static void build_memdev(u8 *ssdt_ptr, int i, u64 mem_base, u64 mem_len, u8 node) > +{ > + memcpy(ssdt_ptr, MEM_AML, MEM_SIZEOF); > + ssdt_ptr[MEM_OFFSET_HEX] = getHex(i >> 4); > + ssdt_ptr[MEM_OFFSET_HEX+1] = getHex(i); > + ssdt_ptr[MEM_OFFSET_ID] = i; > + ssdt_ptr[MEM_OFFSET_PXM] = node; > + *(u64*)(ssdt_ptr + MEM_OFFSET_START) = cpu_to_le64(mem_base); > + *(u64*)(ssdt_ptr + MEM_OFFSET_END) = cpu_to_le64(mem_base + mem_len); > + *(u64*)(ssdt_ptr + MEM_OFFSET_SIZE) = cpu_to_le64(mem_len); > +} > + > +static u8 *build_memssdt(u8 *ssdt_ptr, int memssdt_len, > + u64 *numadimmsmap, int nb_memdevs) > +{ > + u64 mem_base, mem_len; > + u64 *dimm = numadimmsmap; > + int node; > + int i; > + > + // build Scope(_SB_) header > + *(ssdt_ptr++) = 0x10; // ScopeOp > + ssdt_ptr = encodeLen(ssdt_ptr, memssdt_len, 3); > + *(ssdt_ptr++) = '_'; > + *(ssdt_ptr++) = 'S'; > + *(ssdt_ptr++) = 'B'; > + *(ssdt_ptr++) = '_'; Windows doesn't like much 2 \_SB in one SSDT table, and BSODs. Just drop it and add stuff to already existing scope or alternatively create a second SSDT table. > + for (i = 0; i < nb_memdevs; i++) { > + mem_base = *dimm++; > + mem_len = *dimm++; > + node = *dimm++; > + build_memdev(ssdt_ptr, i, mem_base, mem_len, node); > + ssdt_ptr += MEM_SIZEOF; > + } > + > + // build "Method(MTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CM00, Arg1)} ...}" > + *(ssdt_ptr++) = 0x14; // MethodOp > + ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*nb_memdevs), 2); > + *(ssdt_ptr++) = 'M'; > + *(ssdt_ptr++) = 'T'; > + *(ssdt_ptr++) = 'F'; > + *(ssdt_ptr++) = 'Y'; > + *(ssdt_ptr++) = 0x02; > + for (i=0; i<nb_memdevs; i++) { > + *(ssdt_ptr++) = 0xA0; // IfOp > + ssdt_ptr = encodeLen(ssdt_ptr, 11, 1); > + *(ssdt_ptr++) = 0x93; // LEqualOp > + *(ssdt_ptr++) = 0x68; // Arg0Op > + *(ssdt_ptr++) = 0x0A; // BytePrefix > + *(ssdt_ptr++) = i; > + *(ssdt_ptr++) = 0x86; // NotifyOp > + *(ssdt_ptr++) = 'M'; > + *(ssdt_ptr++) = 'P'; > + *(ssdt_ptr++) = getHex(i >> 4); > + *(ssdt_ptr++) = getHex(i); > + *(ssdt_ptr++) = 0x69; // Arg1Op > + } > + > + // build "Name(MEON, Package() { One, One, ..., Zero, Zero, ... })" > + *(ssdt_ptr++) = 0x08; // NameOp > + *(ssdt_ptr++) = 'M'; > + *(ssdt_ptr++) = 'E'; > + *(ssdt_ptr++) = 'O'; > + *(ssdt_ptr++) = 'N'; > + *(ssdt_ptr++) = 0x12; // PackageOp > + ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*nb_memdevs), 2); > + *(ssdt_ptr++) = nb_memdevs; > + > + dimm = numadimmsmap; > + u8 memslot_status = 0, enabled; > + > + for (i = 0; i < nb_memdevs; i++) { > + enabled = 0; > + if (i % 8 == 0) > + memslot_status = inb(MEM_BASE + i/8); > + enabled = memslot_status & 1; > + mem_base = *dimm++; > + mem_len = *dimm++; > + dimm++; // node > + *(ssdt_ptr++) = enabled ? 0x01 : 0x00; > + if (enabled) > + add_e820(mem_base, mem_len, E820_RAM); > + memslot_status = memslot_status >> 1; > + } > + > + return ssdt_ptr; > +} > + > static void* > build_ssdt(void) > { > + int nb_memdevs; > + u64 *numadimmsmap; > int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs; > int length = (sizeof(ssdp_misc_aml) // _S3_ / _S4_ / _S5_ > + (1+3+4) // Scope(_SB_) > @@ -318,9 +423,20 @@ build_ssdt(void) > + (1+3+4) // Scope(PCI0) > + ((PCI_SLOTS - 1) * PCIHP_SIZEOF) // slots > + (1+2+5+(12*(PCI_SLOTS - 1)))); // PCNT > - u8 *ssdt = malloc_high(length); > + > + numadimmsmap = romfile_loadfile("etc/numa-dimm-map", &nb_memdevs); > + nb_memdevs /= 3 * sizeof(u64); > + > + // for build_memssdt > + int memssdt_length = (1+3+4) > + + (nb_memdevs * MEM_SIZEOF) > + + (1+2+5+(12*nb_memdevs)) > + + (6+2+1+(1*nb_memdevs)); > + > + u8 *ssdt = malloc_high(length + memssdt_length); > if (! ssdt) { > warn_noalloc(); > + free(numadimmsmap); > return NULL; > } > u8 *ssdt_ptr = ssdt; > @@ -411,10 +527,13 @@ build_ssdt(void) > > ssdt_ptr = build_notify(ssdt_ptr, "PCNT", 1, PCI_SLOTS, "S00_", 1); > > + ssdt_ptr = build_memssdt(ssdt_ptr, memssdt_length, numadimmsmap, nb_memdevs); ^^^^^^^ name is misleading, since the result of call is not SSDT > + > build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1); > > //hexdump(ssdt, ssdt_ptr - ssdt); > > + free(numadimmsmap); > return ssdt; > } > > @@ -458,7 +577,7 @@ acpi_build_srat_memory(struct srat_memory_affinity *numamem, > numamem->length = sizeof(*numamem); > memset(numamem->proximity, 0, 4); > numamem->proximity[0] = node; > - numamem->flags = cpu_to_le32(!!enabled); > + numamem->flags = cpu_to_le32(!!enabled) | cpu_to_le32(0x2); > numamem->base_addr = cpu_to_le64(base); > numamem->range_length = cpu_to_le64(len); > } > @@ -466,18 +585,22 @@ acpi_build_srat_memory(struct srat_memory_affinity *numamem, > static void * > build_srat(void) > { > - int numadatasize, numacpusize; > + int numadatasize, numacpusize, nb_numa_dimms; > + u64 *numadimmsmap; > u64 *numadata = romfile_loadfile("etc/numa-nodes", &numadatasize); > u64 *numacpumap = romfile_loadfile("etc/numa-cpu-map", &numacpusize); > - if (!numadata || !numacpumap) > - goto fail; > + > int max_cpu = numacpusize / sizeof(u64); > int nb_numa_nodes = numadatasize / sizeof(u64); > > + numadimmsmap = romfile_loadfile("etc/numa-dimm-map", &nb_numa_dimms); > + > + nb_numa_dimms /= 3 * sizeof(u64); > + > struct system_resource_affinity_table *srat; > int srat_size = sizeof(*srat) + > sizeof(struct srat_processor_affinity) * max_cpu + > - sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2); > + sizeof(struct srat_memory_affinity) * (nb_numa_nodes + nb_numa_dimms + 2); > > srat = malloc_high(srat_size); > if (!srat) { > @@ -512,6 +635,7 @@ build_srat(void) > */ > struct srat_memory_affinity *numamem = (void*)core; > int slots = 0; > + int node; > u64 mem_len, mem_base, next_base = 0; > > acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1); > @@ -541,7 +665,18 @@ build_srat(void) > numamem++; > slots++; > } > - for (; slots < nb_numa_nodes + 2; slots++) { > + if (nb_numa_dimms) { > + for (i = 1; i < nb_numa_dimms + 1; ++i) { > + mem_base = *numadimmsmap++; > + mem_len = *numadimmsmap++; > + node = *numadimmsmap++; > + acpi_build_srat_memory(numamem, mem_base, mem_len, node, 1); > + numamem++; > + slots++; > + } > + } > + > + for (; slots < nb_numa_nodes + nb_numa_dimms + 2; slots++) { > acpi_build_srat_memory(numamem, 0, 0, 0, 0); > numamem++; > } > @@ -550,10 +685,12 @@ build_srat(void) > > free(numadata); > free(numacpumap); > + free(numadimmsmap); > return srat; > fail: > free(numadata); > free(numacpumap); > + free(numadimmsmap); > return NULL; > } > > diff --git a/src/paravirt.c b/src/paravirt.c > index d1a5d3e..5925c63 100644 > --- a/src/paravirt.c > +++ b/src/paravirt.c > @@ -240,6 +240,14 @@ qemu_cfg_legacy(void) > , sizeof(numacount) + max_cpu*sizeof(u64) > , numacount*sizeof(u64)); > > + u64 dimm_count; > + qemu_cfg_select(QEMU_CFG_NUMA); > + qemu_cfg_skip((1 + max_cpu + numacount) * sizeof(u64)); > + qemu_cfg_read(&dimm_count, sizeof(dimm_count)); > + qemu_romfile_add("etc/numa-dimm-map", QEMU_CFG_NUMA > + , (2 + max_cpu + numacount) * sizeof(u64), > + dimm_count * 3 * sizeof(u64)); > + > // e820 data > u32 count32; > qemu_cfg_read_entry(&count32, QEMU_CFG_E820_TABLE, sizeof(count32));

1 0

[PATCH v2 2/2] qemu: piix: PCI bridge ACPI hotplug support
by Michael S. Tsirkin 11 Jul '13

11 Jul '13

This adds support for device hotplug behind pci bridges. Bridge devices themselves need to be pre-configured on qemu command line. Design: - each bus gets assigned a number 0-255 - generated ACPI code writes this number to a new BSEL register, then uses existing UP/DOWN registers to probe slot status; to eject, write number to BSEL register, then slot into existing EJ This is to address the ACPI spec requirement to avoid config cycle access to any bus except PCI roots. Note: ACPI doesn't support adding or removing bridges by hotplug. We detect and prevent removal of bridges by hotplug, unless they were added by hotplug previously (and so, are not described by ACPI). Portability: - Non x86 (or any Linux) platforms don't need any of this code. They can keep happily using SHPC the way they always did. Things to note: - this is on top of acpi patchset posted previously. with a small patch adding a core function to walk all pci buses, on top. Can also be found in my git tree git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git acpi-bridges - Extensive use of glib completely removes pointer math in new code: we use g_array_append_vals exclusively. Code in acpi-build.c will be switched to use the same approach, for security. - As was the case previously, systems that lack working iasl are detected at configure time, pre-generated hex files in source tree are used in this case. This addresses the concern with iasl/big-endian systems. - Cross version migration: when running with -M 1.5 and older, new hotplug functionality is unavailable. All ACPI table generation is disabled. We present FW_CFG interface compatible with 1.5. Cc: Jordan Justen <jljusten(a)gmail.com> Cc: Anthony Liguori <anthony(a)codemonkey.ws> Cc: Laszlo Ersek <lersek(a)redhat.com> Cc: Gerd Hoffmann <kraxel(a)redhat.com> Cc: seabios(a)seabios.org Cc: David Woodhouse <dwmw2(a)infradead.org> Cc: Kevin O'Connor <kevin(a)koconnor.net> Cc: Peter Maydell <peter.maydell(a)linaro.org> Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- docs/specs/acpi_pci_hotplug.txt | 8 + hw/acpi/piix4.c | 217 +++++++++++++++----- hw/i386/Makefile.objs | 2 +- hw/i386/acpi-build.c | 425 +++++++++++++++++++++++++++++++++++---- hw/i386/acpi-dsdt.dsl | 36 +++- hw/i386/pc_piix.c | 3 + hw/i386/ssdt-pcihp.dsl | 51 ----- hw/i386/ssdt-pcihp.hex.generated | 108 ---------- include/hw/i386/pc.h | 5 +- 9 files changed, 587 insertions(+), 268 deletions(-) delete mode 100644 hw/i386/ssdt-pcihp.dsl delete mode 100644 hw/i386/ssdt-pcihp.hex.generated diff --git a/docs/specs/acpi_pci_hotplug.txt b/docs/specs/acpi_pci_hotplug.txt index a839434..951b99a 100644 --- a/docs/specs/acpi_pci_hotplug.txt +++ b/docs/specs/acpi_pci_hotplug.txt @@ -43,3 +43,11 @@ PCI removability status (IO port 0xae0c-0xae0f, 4-byte access): Used by ACPI BIOS _RMV method to indicate removability status to OS. One bit per slot. Read-only + +PCI bus selector (IO port 0xae10-0xae13, 4-byte access): +----------------------------------------------- + +Used by ACPI BIOS methods to select the current PCI bus. +When written, makes all the other PCI registers (0xae00 - 0xae0f) +to refer to the appropriate bus. +0 selects PCI root bus (default). diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index c077a7a..bc7df06 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -29,6 +29,7 @@ #include "exec/ioport.h" #include "hw/nvram/fw_cfg.h" #include "exec/address-spaces.h" +#include "hw/pci/pci_bus.h" //#define DEBUG @@ -42,11 +43,12 @@ #define GPE_LEN 4 #define PCI_HOTPLUG_ADDR 0xae00 -#define PCI_HOTPLUG_SIZE 0x000f +#define PCI_HOTPLUG_SIZE 0x0014 #define PCI_UP_BASE 0xae00 #define PCI_DOWN_BASE 0xae04 #define PCI_EJ_BASE 0xae08 #define PCI_RMV_BASE 0xae0c +#define PCI_SEL_BASE 0xae10 #define PIIX4_PROC_BASE 0xaf00 #define PIIX4_PROC_LEN 32 @@ -57,6 +59,8 @@ struct pci_status { uint32_t up; /* deprecated, maintained for migration compatibility */ uint32_t down; + uint32_t hotplug_enable; + uint32_t device_present; }; typedef struct CPUStatus { @@ -84,9 +88,8 @@ typedef struct PIIX4PMState { Notifier powerdown_notifier; /* for pci hotplug */ - struct pci_status pci0_status; - uint32_t pci0_hotplug_enable; - uint32_t pci0_slot_device_present; + struct pci_status pci_status[GUEST_INFO_MAX_HOTPLUG_BUS]; + uint32_t hotplug_select; uint8_t disable_s3; uint8_t disable_s4; @@ -98,6 +101,17 @@ typedef struct PIIX4PMState { PcGuestInfo *guest_info; } PIIX4PMState; +static int piix4_find_hotplug_bus(PcGuestInfo *guest_info, PCIBus *bus) +{ + int i; + for (i = 0; i < GUEST_INFO_MAX_HOTPLUG_BUS; ++i) { + if (guest_info->hotplug_buses[i] == bus) { + return i; + } + } + return -1; +} + static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCIBus *bus, PIIX4PMState *s); @@ -181,15 +195,35 @@ static void pm_write_config(PCIDevice *d, } } -static void vmstate_pci_status_pre_save(void *opaque) +static bool piix4_acpi_bridge_hotplug(PIIX4PMState *s) +{ + return s->guest_info && s->guest_info->has_acpi_bridge_hotplug; +} + +static bool vmstate_test_bridge_hotplug(void *opaque, int version_id) +{ + return piix4_acpi_bridge_hotplug(opaque); +} + +static bool vmstate_test_no_bridge_hotplug(void *opaque, int version_id) +{ + return !piix4_acpi_bridge_hotplug(opaque); +} + +static void vmstate_pci_status_pre_save_compat(void *opaque) { struct pci_status *pci0_status = opaque; - PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); + PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci_status[0]); + + /* Bridge hotplug enabled - no need for compat hacks */ + if (piix4_acpi_bridge_hotplug(s)) { + return; + } /* We no longer track up, so build a safe value for migrating * to a version that still does... of course these might get lost * by an old buggy implementation, but we try. */ - pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; + pci0_status->up = pci0_status->device_present & pci0_status->hotplug_enable; } static int vmstate_acpi_post_load(void *opaque, int version_id) @@ -227,7 +261,7 @@ static const VMStateDescription vmstate_pci_status = { .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, - .pre_save = vmstate_pci_status_pre_save, + .pre_save = vmstate_pci_status_pre_save_compat, .fields = (VMStateField []) { VMSTATE_UINT32(up, struct pci_status), VMSTATE_UINT32(down, struct pci_status), @@ -267,7 +301,8 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_be16s(f, &temp); } - ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1); + ret = vmstate_load_state(f, &vmstate_pci_status, + &s->pci_status, 1); return ret; } @@ -293,28 +328,64 @@ static const VMStateDescription vmstate_acpi = { VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), - VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, - struct pci_status), + VMSTATE_STRUCT_TEST(pci_status[0], PIIX4PMState, + vmstate_test_no_bridge_hotplug, 1, + vmstate_pci_status, + struct pci_status), + VMSTATE_UINT32_TEST(hotplug_select, PIIX4PMState, + vmstate_test_bridge_hotplug), + VMSTATE_STRUCT_ARRAY_TEST(pci_status, PIIX4PMState, + GUEST_INFO_MAX_HOTPLUG_BUS, + vmstate_test_bridge_hotplug, 1, + vmstate_pci_status, + struct pci_status), VMSTATE_END_OF_LIST() } }; -static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) +static bool acpi_piix_pc_no_hotplug(PIIX4PMState *s, PCIDevice *dev) +{ + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); + /* No ACPI hotplug? Assume native hotplug. In theory it + * can handle hot-unplug of bridge devices. + */ + if (!piix4_acpi_bridge_hotplug(s)) + return pc->no_hotplug; + /* + * ACPI doesn't allow hotplug of bridge devices. Don't allow + * hot-unplug of bridge devices unless they were added by hotplug + * (and so, not described by acpi). + */ + return (pc->is_bridge && !dev->qdev.hotplugged) || pc->no_hotplug; +} + +static PCIBus *piix4_acpi_hotplug_bus(PIIX4PMState *s, unsigned bsel) +{ + if (!piix4_acpi_bridge_hotplug(s)) + return bsel == 0 ? pci_device_root_bus(&s->dev) : NULL; + return s->guest_info->hotplug_buses[bsel]; +} + +static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned bsel, unsigned slots) { BusChild *kid, *next; - BusState *bus = qdev_get_parent_bus(&s->dev.qdev); + BusState *bus; int slot = ffs(slots) - 1; bool slot_free = true; + if (!piix4_acpi_hotplug_bus(s, bsel)) { + return; + } + bus = &piix4_acpi_hotplug_bus(s, bsel)->qbus; + /* Mark request as complete */ - s->pci0_status.down &= ~(1U << slot); + s->pci_status[bsel].down &= ~(1U << slot); QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { DeviceState *qdev = kid->child; PCIDevice *dev = PCI_DEVICE(qdev); - PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); if (PCI_SLOT(dev->devfn) == slot) { - if (pc->no_hotplug) { + if (acpi_piix_pc_no_hotplug(s, dev)) { slot_free = false; } else { qdev_free(qdev); @@ -322,35 +393,37 @@ static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) } } if (slot_free) { - s->pci0_slot_device_present &= ~(1U << slot); + s->pci_status[bsel].device_present &= ~(1U << slot); } } -static void piix4_update_hotplug(PIIX4PMState *s) +static void piix4_update_hotplug(PIIX4PMState *s, unsigned bsel) { - PCIDevice *dev = &s->dev; - BusState *bus = qdev_get_parent_bus(&dev->qdev); BusChild *kid, *next; + BusState *bus; + if (!piix4_acpi_hotplug_bus(s, bsel)) { + return; + } + bus = &piix4_acpi_hotplug_bus(s, bsel)->qbus; /* Execute any pending removes during reset */ - while (s->pci0_status.down) { - acpi_piix_eject_slot(s, s->pci0_status.down); + while (s->pci_status[bsel].down) { + acpi_piix_eject_slot(s, bsel, s->pci_status[bsel].down); } - s->pci0_hotplug_enable = ~0; - s->pci0_slot_device_present = 0; + s->pci_status[bsel].hotplug_enable = ~0; + s->pci_status[bsel].device_present = 0; QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { DeviceState *qdev = kid->child; PCIDevice *pdev = PCI_DEVICE(qdev); - PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); int slot = PCI_SLOT(pdev->devfn); - if (pc->no_hotplug) { - s->pci0_hotplug_enable &= ~(1U << slot); + if (acpi_piix_pc_no_hotplug(s, pdev)) { + s->pci_status[bsel].hotplug_enable &= ~(1U << slot); } - s->pci0_slot_device_present |= (1U << slot); + s->pci_status[bsel].device_present |= (1U << slot); } } @@ -358,6 +431,7 @@ static void piix4_reset(void *opaque) { PIIX4PMState *s = opaque; uint8_t *pci_conf = s->dev.config; + int i; pci_conf[0x58] = 0; pci_conf[0x59] = 0; @@ -371,7 +445,9 @@ static void piix4_reset(void *opaque) /* Mark SMM as already inited (until KVM supports SMM). */ pci_conf[0x5B] = 0x02; } - piix4_update_hotplug(s); + for (i = 0; i < GUEST_INFO_MAX_HOTPLUG_BUS; ++i) { + piix4_update_hotplug(s, i); + } } static void piix4_pm_powerdown_req(Notifier *n, void *opaque) @@ -382,25 +458,47 @@ static void piix4_pm_powerdown_req(Notifier *n, void *opaque) acpi_pm1_evt_power_down(&s->ar); } -static void piix4_update_guest_info(PIIX4PMState *s) +static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, + PCIHotplugState state); + +static void piix4_update_bus_guest_info(PCIBus *pci_bus, void *opaque) { - PCIDevice *dev = &s->dev; - BusState *bus = qdev_get_parent_bus(&dev->qdev); + PIIX4PMState *s = opaque; + PcGuestInfo *guest_info = s->guest_info; BusChild *kid, *next; + BusState *bus = &pci_bus->qbus; + + int i = piix4_find_hotplug_bus(guest_info, NULL); + assert(i >= 0); - memset(s->guest_info->slot_hotplug_enable, 0xff, - DIV_ROUND_UP(PCI_SLOT_MAX, BITS_PER_BYTE)); + guest_info->hotplug_buses[i] = pci_bus; QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { DeviceState *qdev = kid->child; PCIDevice *pdev = PCI_DEVICE(qdev); - PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); int slot = PCI_SLOT(pdev->devfn); - if (pc->no_hotplug) { - clear_bit(slot, s->guest_info->slot_hotplug_enable); + if (acpi_piix_pc_no_hotplug(s, pdev)) { + clear_bit(slot, guest_info->hotplug_enable[i]); } } + + pci_bus_hotplug(pci_bus, piix4_device_hotplug, &s->dev.qdev); +} + +static void piix4_update_guest_info(PIIX4PMState *s) +{ + PCIDevice *dev = &s->dev; + + memset(s->guest_info->hotplug_enable, 0xff, + sizeof s->guest_info->hotplug_enable); + + if (s->guest_info->has_acpi_bridge_hotplug) { + pci_for_each_bus(dev->bus, piix4_update_bus_guest_info, + s); + } else { + piix4_update_bus_guest_info(dev->bus, s); + } } static void piix4_pm_machine_ready(Notifier *n, void *opaque) @@ -589,16 +687,22 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) { PIIX4PMState *s = opaque; uint32_t val = 0; + int bsel = s->hotplug_select; + + if (bsel > GUEST_INFO_MAX_HOTPLUG_BUS) { + return 0; + } switch (addr) { case PCI_UP_BASE - PCI_HOTPLUG_ADDR: /* Manufacture an "up" value to cause a device check on any hotplug * slot with a device. Extra device checks are harmless. */ - val = s->pci0_slot_device_present & s->pci0_hotplug_enable; + val = s->pci_status[bsel].device_present & + s->pci_status[bsel].hotplug_enable; PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); break; case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: - val = s->pci0_status.down; + val = s->pci_status[bsel].down; PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); break; case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: @@ -606,8 +710,10 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); break; case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: - val = s->pci0_hotplug_enable; + val = s->pci_status[bsel].hotplug_enable; break; + case PCI_SEL_BASE - PCI_HOTPLUG_ADDR: + val = s->hotplug_select; default: break; } @@ -618,12 +724,18 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) static void pci_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { + PIIX4PMState *s = opaque; switch (addr) { case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: - acpi_piix_eject_slot(opaque, (uint32_t)data); + if (s->hotplug_select >= GUEST_INFO_MAX_HOTPLUG_BUS) { + break; + } + acpi_piix_eject_slot(s, s->hotplug_select, data); PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, data); break; + case PCI_SEL_BASE - PCI_HOTPLUG_ADDR: + s->hotplug_select = data; default: break; } @@ -706,9 +818,6 @@ static void piix4_init_cpu_status(CPUState *cpu, void *data) g->sts[id / 8] |= (1 << (id % 8)); } -static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, - PCIHotplugState state); - static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCIBus *bus, PIIX4PMState *s) { @@ -720,8 +829,6 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCI_HOTPLUG_SIZE); memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR, &s->io_pci); - pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); - qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu); memory_region_init_io(&s->io_cpu, &cpu_hotplug_ops, s, "apci-cpu-hotplug", PIIX4_PROC_LEN); @@ -730,16 +837,16 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, qemu_register_cpu_added_notifier(&s->cpu_added_notifier); } -static void enable_device(PIIX4PMState *s, int slot) +static void enable_device(PIIX4PMState *s, unsigned bsel, int slot) { s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; - s->pci0_slot_device_present |= (1U << slot); + s->pci_status[bsel].device_present |= (1U << slot); } -static void disable_device(PIIX4PMState *s, int slot) +static void disable_device(PIIX4PMState *s, unsigned bsel, int slot) { s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; - s->pci0_status.down |= (1U << slot); + s->pci_status[bsel].down |= (1U << slot); } static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, @@ -748,19 +855,23 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int slot = PCI_SLOT(dev->devfn); PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, PCI_DEVICE(qdev)); + int bsel = piix4_find_hotplug_bus(s->guest_info, dev->bus); + if (bsel < 0) { + return -1; + } /* Don't send event when device is enabled during qemu machine creation: * it is present on boot, no hotplug event is necessary. We do send an * event when the device is disabled later. */ if (state == PCI_COLDPLUG_ENABLED) { - s->pci0_slot_device_present |= (1U << slot); + s->pci_status[bsel].device_present |= (1U << slot); return 0; } if (state == PCI_HOTPLUG_ENABLED) { - enable_device(s, slot); + enable_device(s, bsel, slot); } else { - disable_device(s, slot); + disable_device(s, bsel, slot); } pm_update_sci(s); diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs index 2ab2572..c2e74e9 100644 --- a/hw/i386/Makefile.objs +++ b/hw/i386/Makefile.objs @@ -6,7 +6,7 @@ obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o obj-y += kvmvapic.o obj-y += acpi-build.o obj-y += bios-linker-loader.o -hw/i386/acpi-build.o: hw/i386/acpi-build.c hw/i386/acpi-dsdt.hex hw/i386/ssdt-proc.hex hw/i386/ssdt-pcihp.hex hw/i386/ssdt-misc.hex hw/i386/q35-acpi-dsdt.hex +hw/i386/acpi-build.o: hw/i386/acpi-build.c hw/i386/acpi-dsdt.hex hw/i386/ssdt-proc.hex hw/i386/ssdt-misc.hex hw/i386/q35-acpi-dsdt.hex hw/i386/pc_piix.o: hw/i386/pc_piix.c hw/i386/acpi-dsdt.hex hw/i386/pc_q35.o: hw/i386/pc_q35.c hw/i386/q35-acpi-dsdt.hex diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index bc44f95..2b3900a 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -35,6 +35,7 @@ #include "hw/nvram/fw_cfg.h" #include "hw/i386/bios-linker-loader.h" #include "hw/loader.h" +#include "hw/pci/pci_bus.h" #define ACPI_BUILD_APPNAME "Bochs" #define ACPI_BUILD_APPNAME6 "BOCHS " @@ -259,23 +260,372 @@ acpi_encode_len(uint8_t *ssdt_ptr, int length, int bytes) #define ACPI_PROC_SIZEOF (*ssdt_proc_end - *ssdt_proc_start) #define ACPI_PROC_AML (ssdp_proc_aml + *ssdt_proc_start) -/* 0x5B 0x82 DeviceOp PkgLength NameString */ -#define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1) -#define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start) -#define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start) -#define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start) -#define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start) -#define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start) - #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */ #define ACPI_SSDT_HEADER_LENGTH 36 #include "hw/i386/ssdt-misc.hex" -#include "hw/i386/ssdt-pcihp.hex" + +static inline GArray *build_alloc_array(void) +{ + return g_array_new(false, true /* clear */, 1); +} + +static inline void build_free_array(GArray *array) +{ + g_array_free(array, true); +} + +static inline void build_prepend_byte(GArray *array, uint8_t val) +{ + g_array_prepend_val(array, val); +} + +static inline void build_append_byte(GArray *array, uint8_t val) +{ + g_array_append_val(array, val); +} + +static inline void build_prepend_array(GArray *array, GArray *val) +{ + g_array_prepend_vals(array, val->data, val->len); +} + +static inline void build_append_array(GArray *array, GArray *val) +{ + g_array_append_vals(array, val->data, val->len); +} + +static void build_append_nameseg(GArray *array, const char *format, ...) +{ + GString *s = g_string_new(""); + va_list args; + + va_start(args, format); + g_string_vprintf(s, format, args); + va_end(args); + + assert(s->len == 4); + g_array_append_vals(array, s->str, s->len); + g_string_free(s, true); +} + +static void build_prepend_nameseg(GArray *array, const char *format, ...) +{ + GString *s = g_string_new(""); + va_list args; + + va_start(args, format); + g_string_vprintf(s, format, args); + va_end(args); + + assert(s->len == 4); + g_array_prepend_vals(array, s->str, s->len); + g_string_free(s, true); +} + +static void build_prepend_devfn(GArray *name, uint8_t devfn) +{ + build_prepend_nameseg(name, "S%0.02X_", devfn); +} + +static void build_append_devfn(GArray *name, uint8_t devfn) +{ + GArray *array = build_alloc_array(); + build_prepend_devfn(array, devfn); + build_append_array(name, array); + build_free_array(array); +} + +static void build_prepend_name_string(GArray *name, PCIBus *bus) +{ + int segcount; + + for (;!pci_bus_is_root(bus); bus = bus->parent_dev->bus) { + build_prepend_devfn(name, bus->parent_dev->devfn); + } + g_array_prepend_vals(name, "PCI0", 4); + g_array_prepend_vals(name, "_SB_", 4); + /* Name segment length is a multiple of 4 */ + assert(name->len % 4 == 0); + segcount = name->len / 4; + build_prepend_byte(name, segcount); + build_prepend_byte(name, 0x2f); /* MultiNamePrefix */ + build_prepend_byte(name, '\\'); /* RootChar */ +} + +static void build_append_name_string(GArray *name, PCIBus *bus) +{ + GArray *append = build_alloc_array(); + build_prepend_name_string(append, bus); + build_append_array(name, append); + build_free_array(append); +} + +/* 5.4 Definition Block Encoding */ +enum { + PACKAGE_LENGTH_1BYTE_SHIFT = 6, /* Up to 63 - use extra 2 bits. */ + PACKAGE_LENGTH_2BYTE_SHIFT = 4, + PACKAGE_LENGTH_3BYTE_SHIFT = 12, + PACKAGE_LENGTH_4BYTE_SHIFT = 20, +}; + +static void build_prepend_package_length(GArray *package) +{ + uint8_t byte; + unsigned length = package->len; + unsigned length_bytes; + + if (length + 1 < (1 << PACKAGE_LENGTH_1BYTE_SHIFT)) { + length_bytes = 1; + } else if (length + 2 < (1 << PACKAGE_LENGTH_3BYTE_SHIFT)) { + length_bytes = 2; + } else if (length + 3 < (1 << PACKAGE_LENGTH_4BYTE_SHIFT)) { + length_bytes = 3; + } else { + length_bytes = 4; + } + + /* PkgLength is the length of the inclusive length of the data. */ + length += length_bytes; + + switch (length_bytes) { + case 1: + byte = length; + build_prepend_byte(package, byte); + return; + case 4: + byte = length >> PACKAGE_LENGTH_4BYTE_SHIFT; + build_prepend_byte(package, byte); + length &= (1 << PACKAGE_LENGTH_4BYTE_SHIFT) - 1; + /* fall through */ + case 3: + byte = length >> PACKAGE_LENGTH_3BYTE_SHIFT; + build_prepend_byte(package, byte); + length &= (1 << PACKAGE_LENGTH_3BYTE_SHIFT) - 1; + /* fall through */ + case 2: + byte = length >> PACKAGE_LENGTH_2BYTE_SHIFT; + build_prepend_byte(package, byte); + length &= (1 << PACKAGE_LENGTH_2BYTE_SHIFT) - 1; + /* fall through */ + } + /* + * Most significant two bits of byte zero indicate how many following bytes + * are in PkgLength encoding. + */ + byte = ((length_bytes - 1) << PACKAGE_LENGTH_1BYTE_SHIFT) | length; + build_prepend_byte(package, byte); +} + +static void build_package(GArray *package, uint8_t op) +{ + build_prepend_package_length(package); + build_prepend_byte(package, op); +} + +static void build_extop_package(GArray *package, uint8_t op) +{ + build_package(package, op); + build_prepend_byte(package, 0x5B); /* ExtOpPrefix */ +} + +static void build_append_notify(GArray *method, GArray *target_name, + uint16_t value) +{ + GArray *notify = build_alloc_array(); + uint8_t op = 0xA0; /* IfOp */ + + build_append_byte(notify, 0x93); /* LEqualOp */ + build_append_byte(notify, 0x68); /* Arg0Op */ + build_append_byte(notify, 0x0B); /* WordPrefix */ + build_append_byte(notify, value); + build_append_byte(notify, value >> 8); + build_append_byte(notify, 0x86); /* NotifyOp */ + build_append_array(notify, target_name); + build_append_byte(notify, 0x69); /* Arg1Op */ + + /* Pack it up */ + build_package(notify, op); + + build_append_array(method, notify); + + build_free_array(notify); +} + +static void +build_append_notify_slots(GArray *method, PCIBus *bus, + unsigned bus_select, + DECLARE_BITMAP(hotplug_enable, PCI_SLOT_MAX)) +{ + int i; + + if (!bus) { + return; + } + + for (i = 0; i < PCI_SLOT_MAX; i++) { + GArray *target; + if (!test_bit(i, hotplug_enable)) { + continue; + } + target = build_alloc_array(); + build_prepend_devfn(target, PCI_DEVFN(i, 0)); + build_prepend_name_string(target, bus); + /* *32 matches Multiply in PCNF */ + build_append_notify(method, target, bus_select * 32 + i); + build_free_array(target); + } +} + +static void build_append_notify_buses(GArray *table, PcGuestInfo *guest_info) +{ + int i; + GArray *method = build_alloc_array(); + + uint8_t op = 0x14; /* MethodOp */ + + build_append_nameseg(method, "PCNT"); + build_append_byte(method, 0x02); /* MethodFlags: ArgCount */ + for (i = 0; i < ARRAY_SIZE(guest_info->hotplug_buses); ++i) { + build_append_notify_slots(method, guest_info->hotplug_buses[i], i, + guest_info->hotplug_enable[i]); + } + build_package(method, op); + + build_append_array(table, method); + build_free_array(method); +} + +static void build_append_device(GArray *table, unsigned devfn) +{ + uint8_t op, ej0_op; + + GArray *device = build_alloc_array(); + GArray *ej0 = build_alloc_array(); + + op = 0x82; /* DeviceOp */ + + build_append_devfn(device, devfn); + + build_append_byte(device, 0x08); /* NameOp */ + build_append_nameseg(device, "_SUN"); + build_append_byte(device, 0x0A); /* BytePrefix */ + build_append_byte(device, PCI_SLOT(devfn)); + build_append_byte(device, 0x08); /* NameOp */ + build_append_nameseg(device, "_ADR"); + build_append_byte(device, 0x0C); /* DWordPrefix */ + build_append_byte(device, PCI_FUNC(devfn)); + build_append_byte(device, 0x00); + build_append_byte(device, PCI_SLOT(devfn)); + build_append_byte(device, 0x00); + + ej0_op = 0x14; /* MethodOp */ + build_append_nameseg(ej0, "_EJ0"); + build_append_byte(ej0, 0x01); /* MethodFlags: ArgCount */ + build_append_byte(ej0, 0xA4); /* ReturnOp */ + build_append_nameseg(ej0, "PCEJ"); + build_append_nameseg(ej0, "_SUN"); + build_append_nameseg(ej0, "BNUM"); + build_package(ej0, ej0_op); + build_append_array(device, ej0); + + build_extop_package(device, op); + + build_append_array(table, device); + build_free_array(device); + build_free_array(ej0); +} + +static bool build_find_device_bus(PCIBus *buses[GUEST_INFO_MAX_HOTPLUG_BUS], + PCIBus *bus, unsigned devfn) +{ + int i; + for (i = 0; i < ARRAY_SIZE(buses); ++i) { + if (buses[i] && buses[i]->parent_dev && + buses[i]->parent_dev->bus == bus && + buses[i]->parent_dev->devfn == devfn) { + return true; + } + } + return false; +} + +static void +build_append_bus(GArray *table, int bnum, PcGuestInfo *guest_info) +{ + uint8_t op; + int slot; + unsigned devfn; + GArray *device; + PCIBus *bus = guest_info->hotplug_buses[bnum]; + + if (!bus) { + return; + } + + device = build_alloc_array(); + + /* Root device described in DSDT */ + if (bnum) { + devfn = bus->parent_dev->devfn; + + op = 0x82; /* DeviceOp */ + + build_append_name_string(device, bus); + + build_append_byte(device, 0x08); /* NameOp */ + build_append_nameseg(device, "_SUN"); + build_append_byte(device, 0x0A); /* BytePrefix */ + build_append_byte(device, PCI_SLOT(devfn)); + build_append_byte(device, 0x08); /* NameOp */ + build_append_nameseg(device, "BNUM"); + build_append_byte(device, 0x0A); /* BytePrefix */ + build_append_byte(device, bnum); + build_append_byte(device, 0x08); /* NameOp */ + build_append_nameseg(device, "_ADR"); + build_append_byte(device, 0x0C); /* DWordPrefix */ + build_append_byte(device, PCI_FUNC(devfn)); + build_append_byte(device, 0x00); + build_append_byte(device, PCI_SLOT(devfn)); + build_append_byte(device, 0x00); + } else { + op = 0x10; /* ScopeOp */ + build_append_nameseg(device, "PCI0"); + } + + for (slot = 0; slot < PCI_SLOT_MAX; ++slot) { + if (!test_bit(slot, guest_info->hotplug_enable[bnum])) { + continue; + } + /* Bus device? We'll add it later */ + if (build_find_device_bus(guest_info->hotplug_buses, + bus, PCI_DEVFN(slot, 0))) { + continue; + } + build_append_device(device, PCI_DEVFN(slot, 0)); + } + + if (bnum) { + build_extop_package(device, op); + } else { + build_package(device, op); + } + + build_append_array(table, device); + build_free_array(device); +} + +static void build_append_device_buses(GArray *table, PcGuestInfo *guest_info) +{ + int i; + for (i = 0; i < ARRAY_SIZE(guest_info->hotplug_buses); ++i) { + build_append_bus(table, i, guest_info); + } +} static uint8_t* build_notify(uint8_t *ssdt_ptr, const char *name, int skip, int count, - const char *target, int ofs) + const char *target, int ofs, int step) { int i; @@ -296,31 +646,14 @@ build_notify(uint8_t *ssdt_ptr, const char *name, int skip, int count, *(ssdt_ptr++) = i; *(ssdt_ptr++) = 0x86; /* NotifyOp */ memcpy(ssdt_ptr, target, 4); - ssdt_ptr[ofs] = acpi_get_hex(i >> 4); - ssdt_ptr[ofs + 1] = acpi_get_hex(i); + ssdt_ptr[ofs] = acpi_get_hex((i * step) >> 4); + ssdt_ptr[ofs + 1] = acpi_get_hex(i * step); ssdt_ptr += 4; *(ssdt_ptr++) = 0x69; /* Arg1Op */ } return ssdt_ptr; } -static void patch_pcihp(int slot, uint8_t *ssdt_ptr, uint32_t eject) -{ - ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(slot >> 4); - ssdt_ptr[ACPI_PCIHP_OFFSET_HEX+1] = acpi_get_hex(slot); - ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot; - ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot; - - /* Runtime patching of ACPI_EJ0: to disable hotplug for a slot, - * replace the method name: _EJ0 by ACPI_EJ0_. */ - /* Sanity check */ - assert (!memcmp(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "_EJ0", 4)); - - if (!eject) { - memcpy(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "EJ0_", 4); - } -} - static void build_ssdt(GArray *table_data, GArray *linker, FWCfgState *fw_cfg, PcGuestInfo *guest_info) @@ -331,11 +664,20 @@ build_ssdt(GArray *table_data, GArray *linker, + (acpi_cpus * ACPI_PROC_SIZEOF) /* procs */ + (1+2+5+(12*acpi_cpus)) /* NTFY */ + (6+2+1+(1*acpi_cpus)) /* CPON */ - + (1+3+4) /* Scope(PCI0) */ - + ((PCI_SLOT_MAX - 1) * ACPI_PCIHP_SIZEOF) /* slots */ - + (1+2+5+(12*(PCI_SLOT_MAX - 1)))); /* PCNT */ - uint8_t *ssdt = acpi_data_push(table_data, length); - uint8_t *ssdt_ptr = ssdt; + ); + uint8_t *ssdt; + uint8_t *ssdt_ptr; + GArray *devices = build_alloc_array(); + GArray *notify = build_alloc_array(); + + /* TODO: rewrite this function using glib */ + build_append_device_buses(devices, guest_info); + length += devices->len; + build_append_notify_buses(notify, guest_info); + length += notify->len; + + ssdt = acpi_data_push(table_data, length); + ssdt_ptr = ssdt; /* Copy header and encode fwcfg values in the S3_ / S4_ / S5_ packages */ memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml)); @@ -393,7 +735,7 @@ build_ssdt(GArray *table_data, GArray *linker, /* build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}" */ /* Arg0 = Processor ID = APIC ID */ - ssdt_ptr = build_notify(ssdt_ptr, "NTFY", 0, acpi_cpus, "CP00", 2); + ssdt_ptr = build_notify(ssdt_ptr, "NTFY", 0, acpi_cpus, "CP00", 2, 1); /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" */ *(ssdt_ptr++) = 0x08; /* NameOp */ @@ -415,15 +757,10 @@ build_ssdt(GArray *table_data, GArray *linker, *(ssdt_ptr++) = 'I'; *(ssdt_ptr++) = '0'; - /* build Device object for each slot */ - for (i = 1; i < PCI_SLOT_MAX; i++) { - bool eject = test_bit(i, guest_info->slot_hotplug_enable); - memcpy(ssdt_ptr, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF); - patch_pcihp(i, ssdt_ptr, eject); - ssdt_ptr += ACPI_PCIHP_SIZEOF; - } - - ssdt_ptr = build_notify(ssdt_ptr, "PCNT", 1, PCI_SLOT_MAX, "S00_", 1); + memcpy(ssdt_ptr, devices->data, devices->len); + ssdt_ptr += devices->len; + memcpy(ssdt_ptr, notify->data, notify->len); + ssdt_ptr += notify->len; build_header(linker, table_data, (void*)ssdt, ACPI_SSDT_SIGNATURE, ssdt_ptr - ssdt, 1); diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl index 90efce0..dc05668 100644 --- a/hw/i386/acpi-dsdt.dsl +++ b/hw/i386/acpi-dsdt.dsl @@ -133,11 +133,18 @@ DefinitionBlock ( B0EJ, 32, } + OperationRegion(SEL, SystemIO, 0xae10, 0x04) + Field(SEL, DWordAcc, NoLock, WriteAsZeros) { + BSEL, 32, + } + /* Methods called by bulk generated PCI devices below */ + Name(BNUM, 0x00) /* Methods called by hotplug devices */ - Method(PCEJ, 1, NotSerialized) { + Method(PCEJ, 2, NotSerialized) { // _EJ0 method - eject callback + Store(Arg1, BSEL) Store(ShiftLeft(1, Arg0), B0EJ) Return (0x0) } @@ -147,16 +154,25 @@ DefinitionBlock ( /* PCI hotplug notify method */ Method(PCNF, 0) { - // Local0 = iterator + // Local0 = bridge selector Store(Zero, Local0) - While (LLess(Local0, 31)) { - Increment(Local0) - If (And(PCIU, ShiftLeft(1, Local0))) { - PCNT(Local0, 1) - } - If (And(PCID, ShiftLeft(1, Local0))) { - PCNT(Local0, 3) - } + While (LLess(Local0, 255)) { + Store(Local0, BSEL) + // Local1 = slot iterator + Store(Zero, Local1) + + Store(PCIU, Local2) + Store(PCID, Local3) + While (LLess(Local1, 31)) { + Increment(Local1) + If (And(Local2, ShiftLeft(1, Local1))) { + PCNT(Add(Local1, Multiply(Local0, 32)), 1) + } + If (And(Local3, ShiftLeft(1, Local1))) { + PCNT(Add(Local1, Multiply(Local0, 32)), 3) + } + } + Increment(Local0) } } } diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 77e4260..9183acc 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -61,6 +61,7 @@ static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; static bool has_pvpanic = true; static bool has_pci_info = true; static bool has_acpi_build = true; +static bool has_acpi_bridge_hotplug = true; /* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, @@ -131,6 +132,7 @@ static void pc_init1(MemoryRegion *system_memory, guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); + guest_info->has_acpi_bridge_hotplug = has_acpi_bridge_hotplug; guest_info->has_acpi_build = has_acpi_build; guest_info->dsdt_code = AcpiDsdtAmlCode; guest_info->dsdt_size = sizeof AcpiDsdtAmlCode; @@ -277,6 +279,7 @@ static void pc_init_pci_1_5(QEMUMachineInitArgs *args) { has_pci_info = false; has_acpi_build = false; + has_acpi_bridge_hotplug = false; pc_init_pci(args); } diff --git a/hw/i386/ssdt-pcihp.dsl b/hw/i386/ssdt-pcihp.dsl deleted file mode 100644 index d29a5b9..0000000 --- a/hw/i386/ssdt-pcihp.dsl +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml - -DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1) -{ - -/**************************************************************** - * PCI hotplug - ****************************************************************/ - - /* Objects supplied by DSDT */ - External(\_SB.PCI0, DeviceObj) - External(\_SB.PCI0.PCEJ, MethodObj) - - Scope(\_SB.PCI0) { - - /* Bulk generated PCI hotplug devices */ - ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start - ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end - ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name - - // Method _EJ0 can be patched by BIOS to EJ0_ - // at runtime, if the slot is detected to not support hotplug. - // Extract the offset of the address dword and the - // _EJ0 name to allow this patching. - Device(SAA) { - ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id - Name(_SUN, 0xAA) - ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr - Name(_ADR, 0xAA0000) - ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0 - Method(_EJ0, 1) { - Return (PCEJ(_SUN)) - } - } - } -} diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated deleted file mode 100644 index 0d32a27..0000000 --- a/hw/i386/ssdt-pcihp.hex.generated +++ /dev/null @@ -1,108 +0,0 @@ -static unsigned char ssdt_pcihp_name[] = { -0x33 -}; -static unsigned char ssdt_pcihp_adr[] = { -0x44 -}; -static unsigned char ssdt_pcihp_end[] = { -0x58 -}; -static unsigned char ssdp_pcihp_aml[] = { -0x53, -0x53, -0x44, -0x54, -0x58, -0x0, -0x0, -0x0, -0x1, -0x77, -0x42, -0x58, -0x50, -0x43, -0x0, -0x0, -0x42, -0x58, -0x53, -0x53, -0x44, -0x54, -0x50, -0x43, -0x1, -0x0, -0x0, -0x0, -0x49, -0x4e, -0x54, -0x4c, -0x28, -0x5, -0x10, -0x20, -0x10, -0x33, -0x5c, -0x2e, -0x5f, -0x53, -0x42, -0x5f, -0x50, -0x43, -0x49, -0x30, -0x5b, -0x82, -0x26, -0x53, -0x41, -0x41, -0x5f, -0x8, -0x5f, -0x53, -0x55, -0x4e, -0xa, -0xaa, -0x8, -0x5f, -0x41, -0x44, -0x52, -0xc, -0x0, -0x0, -0xaa, -0x0, -0x14, -0xf, -0x5f, -0x45, -0x4a, -0x30, -0x1, -0xa4, -0x50, -0x43, -0x45, -0x4a, -0x5f, -0x53, -0x55, -0x4e -}; -static unsigned char ssdt_pcihp_start[] = { -0x30 -}; -static unsigned char ssdt_pcihp_id[] = { -0x3d -}; -static unsigned char ssdt_pcihp_ej0[] = { -0x4a -}; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2ac97d3..051f423 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -38,7 +38,9 @@ struct PcGuestInfo { bool s3_disabled; bool s4_disabled; uint8_t s4_val; - DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX); +#define GUEST_INFO_MAX_HOTPLUG_BUS 256 + PCIBus *hotplug_buses[GUEST_INFO_MAX_HOTPLUG_BUS]; + DECLARE_BITMAP(hotplug_enable[GUEST_INFO_MAX_HOTPLUG_BUS], PCI_SLOT_MAX); uint16_t sci_int; uint8_t acpi_enable_cmd; uint8_t acpi_disable_cmd; @@ -52,6 +54,7 @@ struct PcGuestInfo { uint16_t pvpanic_port; FWCfgState *fw_cfg; bool has_acpi_build; + bool has_acpi_bridge_hotplug; }; /* parallel.c */ -- MST

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Re: [SeaBIOS] [PATCH] Seabios: allow mapping of multiple PCI option ROMs to one
by Dave Frodin 10 Jul '13

10 Jul '13

Kevin, I talked with Marc Jones about this and he sees value in the method I've proposed. He also predicts that this will be an issue in the future on Intel motherboards. The one major difference is that if you were building coreboot for a Family15 mainboard you would only need to add one file (vendev_map) rather than 20 alias mapping files to CBFS. I agree that the parsing code is more than clunky (what I wouldn't give for a sscanf()), perhaps my patch could use some changes rather than throwing it out. I'll re-attach my patch in case anybody wants to review it. Thanks again, Dave ----- Original Message ----- > From: "Kevin O'Connor" <kevin(a)koconnor.net> > To: "Dave Frodin" <dave.frodin(a)se-eng.com> > Cc: "seabios" <seabios(a)seabios.org> > Sent: Tuesday, July 2, 2013 10:29:39 PM > Subject: Re: [SeaBIOS] [PATCH] Seabios: allow mapping of multiple PCI option ROMs to one > > On Tue, Jul 02, 2013 at 07:40:17AM -0500, Dave Frodin wrote: > > Kevin, > > > > Did you ever get a chance to look over this patch? > > I don't see the gain in introducing a config file parser for this > task. What was wrong with the approach of creating "alias" files? > > -Kevin >

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[ANNOUNCE] SeaBIOS 1.7.3
by Kevin O'Connor 09 Jul '13

09 Jul '13

The 1.7.3 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Initial support for using SeaBIOS as a UEFI Compatibility Support Module (CSM) * Support for detecting and using ACPI reboot ports. * By default, all 16bit entry points now use an internal stack to reduce stack footprint. * Floppy controller code has been rewritten to improve compatibility. Non-standard floppy sizes now work again with recent QEMU versions. * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download

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Next release
by Kevin O'Connor 08 Jul '13

08 Jul '13

As previously discussed, I'll be generating the next seabios release in the next couple of days. If there are any outstanding defects that need to be addressed in this release, please let me know. -Kevin

2 4

[PATCH v5 0/7] support for ACPI memory hotplug
by Hu Tao 07 Jul '13

07 Jul '13

This series adds memory devices and related methods to support ACPI memory hotplug. This series works with qemu counterpart. See qemu series for a detailed description. Hu Tao (2): set psize to 0 when romfile_loadfile failed acpi: generate hotplug memory devices Vasilis Liaskovitis (5): Add ACPI_EXTRACT_DEVICE* macros Add SSDT memory device support acpi-dsdt: Implement functions for memory hotplug q35: Add memory hotplug handler pci: Use paravirt interface for pcimem_start and pcimem64_start Makefile | 2 +- src/acpi-dsdt-mem-hotplug.dsl | 57 ++++++++++++++++ src/acpi-dsdt.dsl | 5 +- src/acpi.c | 151 ++++++++++++++++++++++++++++++++++++++++-- src/paravirt.c | 15 +++++ src/paravirt.h | 1 + src/pciinit.c | 9 +++ src/q35-acpi-dsdt.dsl | 6 +- src/romfile.c | 13 ++-- src/ssdt-mem.dsl | 61 +++++++++++++++++ tools/acpi_extract.py | 28 ++++++++ 11 files changed, 333 insertions(+), 15 deletions(-) create mode 100644 src/acpi-dsdt-mem-hotplug.dsl create mode 100644 src/ssdt-mem.dsl -- 1.8.3.1

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