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Re: [SeaBIOS] Commit b98a4b1 prevents USB drives from being detected
by Dave Frodin 22 Jul '13

22 Jul '13

Kevin, Your patch does fix the problem with USB thumbdrives. I tested on a Gizmo (Family14/SB800) board. Thanks, Dave ----- Original Message ----- > From: "Kevin O'Connor" <kevin(a)koconnor.net> > To: "Dave Frodin" <dave.frodin(a)se-eng.com> > Cc: "seabios" <seabios(a)seabios.org> > Sent: Sunday, July 14, 2013 11:59:11 AM > Subject: Re: [SeaBIOS] Commit b98a4b1 prevents USB drives from being detected > > On Fri, Jul 12, 2013 at 03:22:43PM -0500, Dave Frodin wrote: > > > I'm using the current seabios (master or stable) as a payload for > > coreboot. If I build the current seabios I've found that commit > > b98a4b1 "Convert PCIDevices list to use standard list manipultion > > code." prevents the system from finding USB thumbdrives. The USB > > keyboard and mouse still work. > > Thanks. The PCI list changes broke the ordering of the PCIDevices > list. Can you confirm the patch below fixes it for you? > > -Kevin > > > commit 2a9aeabdfb34374ecac25e7a8d21c9e368618cd4 > Author: Kevin O'Connor <kevin(a)koconnor.net> > Date: Sun Jul 14 13:55:52 2013 -0400 > > Fix USB EHCI detection that was broken in hlist conversion of PCIDevices. > > Make sure the PCI device list is ordered in bus order. > > Don't iterate past the end of the list when detecting EHCI devices. > > Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> > > diff --git a/src/pci.c b/src/pci.c > index 6163a29..dc62c5c 100644 > --- a/src/pci.c > +++ b/src/pci.c > @@ -122,6 +122,7 @@ pci_probe_devices(void) > } > memset(dev, 0, sizeof(*dev)); > hlist_add(&dev->node, pprev); > + pprev = &dev->node.next; > count++; > > // Find parent device. > diff --git a/src/usb.c b/src/usb.c > index ecccd75..42541ff 100644 > --- a/src/usb.c > +++ b/src/usb.c > @@ -444,7 +444,7 @@ usb_setup(void) > } > if (ehcipci->class == PCI_CLASS_SERIAL_USB) > found++; > - ehcipci = container_of( > + ehcipci = container_of_or_null( > ehcipci->node.next, struct pci_device, node); > if (!ehcipci || (pci_bdf_to_busdev(ehcipci->bdf) > != pci_bdf_to_busdev(pci->bdf))) >

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[PATCH] Add missing mathcp_setup() call to CSM code.
by Kevin O'Connor 22 Jul '13

22 Jul '13

It looks like when mathcp_setup() got moved from interface_init() to platform_hardware_setup() in 3a735baa the corresponding change was not made to the CSM code. Update it now. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/csm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/csm.c b/src/csm.c index e855d2c..2021701 100644 --- a/src/csm.c +++ b/src/csm.c @@ -169,6 +169,7 @@ handle_csm_0002(struct bregs *regs) struct bios_data_area_s *bda = MAKE_FLATPTR(SEG_BDA, 0); bda->hdcount = 0; + mathcp_setup(); timer_setup(); clock_setup(); device_hardware_setup(); -- 1.7.11.7

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[PATCH] Default unused UMB areas to be read-only.
by Kevin O'Connor 21 Jul '13

21 Jul '13

It looks like MSDOS 6 wants the UMB area to be read-only in order for it to use it. FreeDOS doesn't care, but it always maps a page from high mem when it does use the area. So, add an option to control whether unused UMB ram is marked read-only and default it to read-only as that seems to be more compatible. This also fixes an off-by-one bug in the shadow range checking code. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/Kconfig | 12 ++++++++++++ src/shadow.c | 8 +++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 5e2db8b..3a4d580 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -362,6 +362,18 @@ menu "BIOS interfaces" default n help Disable A20 on 16bit boot. + + config WRITABLE_UPPERMEMORY + depends on QEMU + bool "Make unused UMB memory read/writeable." + default n + help + When selected, the "Upper Memory Block" area + (0x90000-0xa0000) that is not used for option roms will be + made writable. This allows the ram to be directly + modified by programs. However, some old DOS high memory + managers may require the UMB region to be read-only. + endmenu menu "BIOS Tables" diff --git a/src/shadow.c b/src/shadow.c index 967eb8e..242f220 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -80,13 +80,15 @@ make_bios_readonly_intel(u16 bdf, u32 pam0) wbinvd(); // Write protect roms from 0xc0000-0xf0000 - u32 romend = rom_get_last(), romtop = rom_get_max(); + u32 romlast = BUILD_BIOS_ADDR, rommax = rom_get_max(); + if (CONFIG_WRITABLE_UPPERMEMORY) + romlast = rom_get_last(); int i; for (i=0; i<6; i++) { u32 mem = BUILD_ROM_START + i * 32*1024; u32 pam = pam0 + 1 + i; - if (romend <= mem + 16*1024 || romtop <= mem + 32*1024) { - if (romend > mem && romtop > mem + 16*1024) + if (romlast < mem + 16*1024 || rommax < mem + 32*1024) { + if (romlast >= mem && rommax >= mem + 16*1024) pci_config_writeb(bdf, pam, 0x31); break; } -- 1.7.11.7

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[PATCH 00/10] Timer enhancements and cleanups
by Kevin O'Connor 21 Jul '13

21 Jul '13

This patch series improves the accuracy of the internal timers. It also refactors a bit of the code and makes it a little cleaner. -Kevin Kevin O'Connor (10): Move internal timer code from clock.c to a new file timer.c. Don't pass khz to pmtimer_setup - it's always PM_TIMER_FREQUENCY. Add helper functions to convert timer irqs to milliseconds. Improve accuracy of internal timers. Rename cpu_khz to TimerKHz. Shift CPU TSC down to reduce need for 64bit variables. Rename check_timer() function (and similar) to irqtimer_check(). Rename check_tsc() (and similar) to timer_check() and use u32. Separate out timer setup code. Unify pmtimer_read() and pittimer_read() code. Makefile | 2 +- src/acpi.c | 2 +- src/ahci.c | 19 ++--- src/ata.c | 18 ++--- src/biosvar.h | 3 + src/blockcmd.c | 6 +- src/boot.c | 4 +- src/clock.c | 249 ++------------------------------------------------------- src/csm.c | 1 + src/floppy.c | 8 +- src/megasas.c | 10 +-- src/pciinit.c | 7 +- src/pit.h | 29 +++++++ src/post.c | 1 + src/ps2port.c | 8 +- src/serial.c | 12 +-- src/timer.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/usb-ehci.c | 16 ++-- src/usb-hub.c | 8 +- src/usb-ohci.c | 18 ++--- src/usb-uhci.c | 14 ++-- src/util.c | 4 +- src/util.h | 29 ++++--- 23 files changed, 374 insertions(+), 338 deletions(-) create mode 100644 src/pit.h create mode 100644 src/timer.c -- 1.7.11.7

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[PATCH] acpi: sync FADT flags from PIIX4 to Q35
by Michael S. Tsirkin 19 Jul '13

19 Jul '13

The following commits updated the FADT flags for PIIX4: commit c7be281b3be0f2013aa4b5d5f400981a1adb6e63 Drop FIX_RTC flag from FADT. commit a4e2b9adbba95c2d783761e84444bbb3c8d6107b enable USE_PLATFORM_CLOCK bit in FADT flags Q35 support was originally written before these commits in seabios, PIIX got updated, Q35 didn't. QEMU uses the same clock for both so there's no reason for these bits to differ. Sync them up. Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- src/acpi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/acpi.c b/src/acpi.c index 3fe5e36..6df2971 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -99,9 +99,9 @@ void ich9_lpc_fadt_setup(struct pci_device *dev, void *arg) fadt->gpe0_blk_len = ICH9_PMIO_GPE0_BLK_LEN; fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported - /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */ - fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) | - (1 << 7)); + /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */ + fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) | + (1 << 15)); } static const struct pci_device_id fadt_init_tbl[] = { -- MST

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[PATCH] Add CONFIG_DEBUG_COREBOOT config option
by Gerd Hoffmann 18 Jul '13

18 Jul '13

Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/Kconfig | 10 ++++++++++ src/coreboot.c | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 5882d11..5e2db8b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -433,4 +433,14 @@ menu "Debugging" information by outputing strings in a special port present in the IO space. + config DEBUG_COREBOOT + depends on COREBOOT && DEBUG_LEVEL != 0 + bool "coreboot cbmem debug logging" + default y + help + Send debugging information to the coreboot cbmem console buffer. + Needs CONFIG_CONSOLE_CBMEM in coreboot. You can read the log + after boot using 'cbmem -c'. Only 32bit code (basically every- + thing before booting the OS) writes to the log buffer. + endmenu diff --git a/src/coreboot.c b/src/coreboot.c index c66e6e3..7f7b322 100644 --- a/src/coreboot.c +++ b/src/coreboot.c @@ -206,7 +206,7 @@ fail: void debug_cbmem(char c) { - if (!CONFIG_COREBOOT) + if (!CONFIG_DEBUG_COREBOOT) return; if (!cbcon) return; -- 1.7.9.7

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Re: [SeaBIOS] "ata_piix device not availabile cannot reserve io" issue
by Kevin O'Connor 17 Jul '13

17 Jul '13

On Mon, Jul 15, 2013 at 11:41:02AM +0200, Riccardo Schirone wrote: > Hi, i use seabios on qemu with Linux as guest OS and i am not able to boot > my machine because kernel says > > ata_piix 0000:00:01.1: device not available (can't reserve [io > 0x0000-0x0007]) > > i try with qemu v1.5.50 and v.1.4.2 and i have the same error. > > Bisecting seabios i found that the error was introduced with this commit > > 76e58028d28e78431f9de3cee0b3c88d807fa39d - acpi: Eliminate BDAT parameter > passing to DSDT code. This looks like the bios.rom file was updated while the acpi-dsdt.aml file was not. The two files must be kept in sync. -Kevin

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Re: [SeaBIOS] [PATCH v5 7/7] pci: Use paravirt interface for pcimem_start and pcimem64_start
by Vasilis Liaskovitis 15 Jul '13

15 Jul '13

Hi, 2013/6/26 Hu Tao <hutao(a)cn.fujitsu.com> > From: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > > Initialize the 32-bit and 64-bit pci starting offsets from values passed > in by > the qemu paravirt interface QEMU_CFG_PCI_WINDOW. Qemu calculates the > starting > offsets based on initial memory and hotplug-able dimms. > We should drop this patch and the corresponding seabios patch since Michael Tsirkin's pci-window patches are merged or will be soon. See "pc: pass PCI hole ranges to Guests" - already in qemu master "pci: load memory window setup from host" (should go into seabios) thanks, - Vasilis > It's possible to avoid the new paravirt interface, and calculate pci > ranges from > srat entries. But the code changes are ugly, see: > http://lists.gnu.org/archive/html/qemu-devel/2012-09/msg03548.html > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> > --- > src/paravirt.c | 7 +++++++ > src/paravirt.h | 1 + > src/pciinit.c | 9 +++++++++ > 3 files changed, 17 insertions(+) > > diff --git a/src/paravirt.c b/src/paravirt.c > index 5925c63..9c1e511 100644 > --- a/src/paravirt.c > +++ b/src/paravirt.c > @@ -134,6 +134,7 @@ qemu_platform_setup(void) > #define QEMU_CFG_BOOT_MENU 0x0e > #define QEMU_CFG_MAX_CPUS 0x0f > #define QEMU_CFG_FILE_DIR 0x19 > +#define QEMU_CFG_PCI_WINDOW 0x1a > #define QEMU_CFG_ARCH_LOCAL 0x8000 > #define QEMU_CFG_ACPI_TABLES (QEMU_CFG_ARCH_LOCAL + 0) > #define QEMU_CFG_SMBIOS_ENTRIES (QEMU_CFG_ARCH_LOCAL + 1) > @@ -339,3 +340,9 @@ void qemu_cfg_init(void) > , 0, be32_to_cpu(qfile.size)); > } > } > + > +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start) > +{ > + qemu_cfg_read_entry(pcimem_start, QEMU_CFG_PCI_WINDOW, sizeof(u64)); > + qemu_cfg_read((u8*)(pcimem64_start), sizeof(u64)); > +} > diff --git a/src/paravirt.h b/src/paravirt.h > index fce5af9..2c37d0d 100644 > --- a/src/paravirt.h > +++ b/src/paravirt.h > @@ -27,5 +27,6 @@ static inline int runningOnKVM(void) { > void qemu_preinit(void); > void qemu_platform_setup(void); > void qemu_cfg_init(void); > +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start); > > #endif > diff --git a/src/pciinit.c b/src/pciinit.c > index 8370b96..7e63c5e 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -805,6 +805,7 @@ static void pci_bios_map_devices(struct pci_bus > *busses) > void > pci_setup(void) > { > + u64 pv_pcimem_start, pv_pcimem64_start; > if (!CONFIG_QEMU) > return; > > @@ -837,6 +838,14 @@ pci_setup(void) > > pci_bios_init_devices(); > > + /* if qemu gives us other pci window values, it means there are > hotplug-able > + * dimms. Adjust accordingly */ > + qemu_cfg_get_pci_offsets(&pv_pcimem_start, &pv_pcimem64_start); > + if (pv_pcimem_start > pcimem_start) > + pcimem_start = pv_pcimem_start; > + if (pv_pcimem64_start > pcimem64_start) > + pcimem64_start = pv_pcimem64_start; > + > free(busses); > > pci_enable_default_vga(); > -- > 1.8.3.1 > >

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Re: [SeaBIOS] Commit b98a4b1 prevents USB drives from being detected
by Dave 15 Jul '13

15 Jul '13

Kevin, I'm currently out of the office. I'll try your patch when I return on July 22nd. Thanks, Dave Kevin O'Connor <kevin(a)koconnor.net> wrote: >On Fri, Jul 12, 2013 at 03:22:43PM -0500, Dave Frodin wrote: > >> I'm using the current seabios (master or stable) as a payload for >> coreboot. If I build the current seabios I've found that commit >> b98a4b1 "Convert PCIDevices list to use standard list manipultion >> code." prevents the system from finding USB thumbdrives. The USB >> keyboard and mouse still work. > >Thanks. The PCI list changes broke the ordering of the PCIDevices >list. Can you confirm the patch below fixes it for you? > >-Kevin > > >commit 2a9aeabdfb34374ecac25e7a8d21c9e368618cd4 >Author: Kevin O'Connor <kevin(a)koconnor.net> >Date: Sun Jul 14 13:55:52 2013 -0400 > >Fix USB EHCI detection that was broken in hlist conversion of >PCIDevices. > > Make sure the PCI device list is ordered in bus order. > > Don't iterate past the end of the list when detecting EHCI devices. > > Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> > >diff --git a/src/pci.c b/src/pci.c >index 6163a29..dc62c5c 100644 >--- a/src/pci.c >+++ b/src/pci.c >@@ -122,6 +122,7 @@ pci_probe_devices(void) > } > memset(dev, 0, sizeof(*dev)); > hlist_add(&dev->node, pprev); >+ pprev = &dev->node.next; > count++; > > // Find parent device. >diff --git a/src/usb.c b/src/usb.c >index ecccd75..42541ff 100644 >--- a/src/usb.c >+++ b/src/usb.c >@@ -444,7 +444,7 @@ usb_setup(void) > } > if (ehcipci->class == PCI_CLASS_SERIAL_USB) > found++; >- ehcipci = container_of( >+ ehcipci = container_of_or_null( > ehcipci->node.next, struct pci_device, node); > if (!ehcipci || (pci_bdf_to_busdev(ehcipci->bdf) > != pci_bdf_to_busdev(pci->bdf)))

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[PATCH] fix calculation of PkgLength
by Hu Tao 15 Jul '13

15 Jul '13

Currently the calculation of PkgLength isn't acpi-compliant. This patch fixes it to be acpi-compliant. Signed-off-by: Hu Tao <hutao(a)cn.fujitsu.com> --- When testing memory hotplug patchset, I found the PkgLength calculation will cause windows 2012, Windows 2008 BSOD (but not windows XP). After fixing it, the problem is resolved. src/acpi.c | 48 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/src/acpi.c b/src/acpi.c index ce988e0..ae28427 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -216,10 +216,34 @@ static inline char getHex(u32 val) { return (val <= 9) ? ('0' + val) : ('A' + val - 10); } +int getBytes(int length, int included) +{ + int nbyte; + + if (length < (included ? 64 : 64 - 1)) { + nbyte = 1; + } else if (length < (included ? 4096 : 4096 - 2)) { + nbyte = 2; + } else if (length < (included ? 1048576 : 1048576 - 3)) { + nbyte = 3; + } else { + nbyte = 4; + } + + return nbyte; +} + // Encode a length in an SSDT. +// PkgLength includes itself, but the bytes(PkgLeadByte + ByteData) +// depends on length of following data. This function calculates the +// bytes, given the @length of following data. static u8 * -encodeLen(u8 *ssdt_ptr, int length, int bytes) +encodeLen(u8 *ssdt_ptr, int length, int included) { + int bytes = getBytes(length, included); + if (!included) + length += bytes; + switch (bytes) { default: case 4: ssdt_ptr[3] = ((length >> 20) & 0xff); @@ -265,15 +289,15 @@ build_notify(u8 *ssdt_ptr, const char *name, int skip, int count, count -= skip; *(ssdt_ptr++) = 0x14; // MethodOp - ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*count), 2); + ssdt_ptr = encodeLen(ssdt_ptr, 4+1+(12*count), 0); memcpy(ssdt_ptr, name, 4); ssdt_ptr += 4; - *(ssdt_ptr++) = 0x02; // MethodOp + *(ssdt_ptr++) = 0x02; // MethodFlags int i; for (i = skip; count-- > 0; i++) { *(ssdt_ptr++) = 0xA0; // IfOp - ssdt_ptr = encodeLen(ssdt_ptr, 11, 1); + ssdt_ptr = encodeLen(ssdt_ptr, 10, 0); *(ssdt_ptr++) = 0x93; // LEqualOp *(ssdt_ptr++) = 0x68; // Arg0Op *(ssdt_ptr++) = 0x0A; // BytePrefix @@ -311,13 +335,13 @@ build_ssdt(void) { int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs; int length = (sizeof(ssdp_misc_aml) // _S3_ / _S4_ / _S5_ - + (1+3+4) // Scope(_SB_) + + (1+2+4) // Scope(_SB_) + (acpi_cpus * PROC_SIZEOF) // procs - + (1+2+5+(12*acpi_cpus)) // NTFY - + (6+2+1+(1*acpi_cpus)) // CPON - + (1+3+4) // Scope(PCI0) + + (1+1+5+(12*acpi_cpus)) // NTFY + + (6+1+1+(1*acpi_cpus)) // CPON + + (1+2+4) // Scope(PCI0) + ((PCI_SLOTS - 1) * PCIHP_SIZEOF) // slots - + (1+2+5+(12*(PCI_SLOTS - 1)))); // PCNT + + (1+1+5+(12*(PCI_SLOTS - 1))+1)); // PCNT u8 *ssdt = malloc_high(length); if (! ssdt) { warn_noalloc(); @@ -359,7 +383,7 @@ build_ssdt(void) // build Scope(_SB_) header *(ssdt_ptr++) = 0x10; // ScopeOp - ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 3); + ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 1); *(ssdt_ptr++) = '_'; *(ssdt_ptr++) = 'S'; *(ssdt_ptr++) = 'B'; @@ -387,14 +411,14 @@ build_ssdt(void) *(ssdt_ptr++) = 'O'; *(ssdt_ptr++) = 'N'; *(ssdt_ptr++) = 0x12; // PackageOp - ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*acpi_cpus), 2); + ssdt_ptr = encodeLen(ssdt_ptr, 1+(1*acpi_cpus), 0); *(ssdt_ptr++) = acpi_cpus; for (i=0; i<acpi_cpus; i++) *(ssdt_ptr++) = (apic_id_is_present(i)) ? 0x01 : 0x00; // build Scope(PCI0) opcode *(ssdt_ptr++) = 0x10; // ScopeOp - ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 3); + ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 1); *(ssdt_ptr++) = 'P'; *(ssdt_ptr++) = 'C'; *(ssdt_ptr++) = 'I'; -- 1.8.3.1

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