SeaBIOS

seabios@seabios.org

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3801 discussions

Emulation failure on booting/rebooting VMs
by Mohammed Gamal 18 Mar '15

18 Mar '15

Hi, I've been sporadically getting my KVM virtual machines crashing with this message while they're booting KVM internal error. Suberror: 1 emulation failure EAX=00000000 EBX=00000000 ECX=00000000 EDX=00600f12 ESI=00000000 EDI=00000000 EBP=00000000 ESP=0000fffa EIP=0000ff53 EFL=00000006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES =0000 00000000 0000ffff 00009300 CS =f000 000f0000 0000ffff 00009b00 SS =0000 00000000 0000ffff 00009200 DS =0000 00000000 0000ffff 00009300 FS =0000 00000000 0000ffff 00009300 GS =0000 00000000 0000ffff 00009300 LDT=0000 00000000 0000ffff 00008200 TR =0000 00000000 0000ffff 00008300 GDT= 00000000 0000ffff IDT= 00000000 0000ffff CR0=60000010 CR2=00000000 CR3=00000000 CR4=00000000 DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000 DR6=00000000ffff0ff0 DR7=0000000000000400 EFER=0000000000000000 Code=74 65 61 6d 2e 00 66 68 5f 55 00 00 e9 c3 f8 fb f4 cb 66 c3 <cf> 66 68 ff e6 00 00 e9 8b b1 66 55 66 57 66 56 66 53 66 89 c1 66 89 d6 a8 07 75 23 66 0f I am running qemu 1.2, seabios 1.7.3 and ipxe (1.0.0-f6840ba) and the host CPU is AMD Opteron 6386 SE running kernel 3.4.71. I digged a little into the kvm kernel module code and I can trace these emulation failures only to either a call to pf_interception() - which is highly unlikely since the machine doesn't appear to have setup paging yet - and task_switch_interception(). I am suspecting that ipxe or seabios might be executing some invalid code or something, since this failure only appears sporadically and is not 100% reproducible. Any ideas why this might be happening? Regards, Mohammed

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IDT issue
by Naresh G. Solanki 17 Mar '15

17 Mar '15

Dear All, I'm trying to port coreboot with seabios payload on Intel Atom E6xx based board, The problem I'm facing is during malloc init, the board reboot & keeps on rebooting after displaying malloc init debug message. I tried to track it & found that it might probably be due to dummy IDT loaded @seabios entry point (entry_elf) Once it reboot I'm finding that breakpoints set are not working. Breakpoints are set through JTAG-XDP. Can anyone give an idea to how to go about this issue. -- -------- * ---------------* ----------------* ----------- *-------------------------------------- ------- --------- -------------- ------- ------ -------------- ------- - ---- -------------- ------- ---- - -------------- ------- ------ --------------- ------- -------- --------------- --------------------------------------*

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IDT issue
by Naresh G. Solanki 17 Mar '15

17 Mar '15

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Re: [SeaBIOS] error in write and read from usb hid device
by Kevin O'Connor 16 Mar '15

16 Mar '15

On Mon, Mar 16, 2015 at 11:13:16AM +0330, Navid Movahedi wrote: > > See http://seabios.org/Debugging > > > > I couldn't add the physical EHCI controller to qemu using pass through. how > to do that? > > So, you are using coreboot+seabios on vmware and coreboot+seabios on > > real hardware as well? > > > > no, i have developed a boot loader and for usb detection and enumeration i > have used the seabios source base and i test this bootloader with vmware > and real hardware Okay, if the code has been modified that much I wont be able to help. I suggest you start by downloading the ehci specification and read through it. -Kevin

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[PATCH] vgabios: Avoid extra stack if it appears a modern OS is in use
by Kevin O'Connor 16 Mar '15

16 Mar '15

If a VBE mode set call is made, stop using the vgabios extra stack. This works under the premise that only a modern OS would invoke the VBE mode changing facilities and a modern OS would always call the vgabios with sufficient stack space. This is an ugly hack to work around a problem Windows Vista (and possibly later Windows releases) has with the VGA BIOS using a stack in the e-segment. Reported-by: Richard Laager <rlaager(a)wiktel.com> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- I ran some further tests with the Windows emulator crashing problem. I eventually came up with the targeted solution above. Basically, I tried to find a signature that indicates Windows is running and disable the extra stack in that case. It's a hack for sure, but it seems to work. For the curious, some other tests that I ran that didn't yield a solution: * The "concurrent dos" image I have actually uses vm86 mode and it still expects the vgabios to only use a tiny amount of stack space. So, just disabling the extra stack in vm86 mode breaks this "concurrent dos" image. * Windows faults on the first write access to the e-segment, so testing if the extra stack is read/writable doesn't work (as the test itself causes a fault which halts the emulation). * Windows actually copies the first 1 Meg before starting the emulation, so putting some kind of signature in the extra stack doesn't help detect if it's read-only. * When these troublesome vgabios calls are made, Windows is using a copy of the first 1 Meg instead of accessing it in place. If a log is written to the writable part of the first 1 Meg, then when the log is inspected later it doesn't show any of the troublesome calls. --- vgasrc/vbe.c | 1 + vgasrc/vgabios.h | 1 + vgasrc/vgainit.c | 15 +++++++++++++++ 3 files changed, 17 insertions(+) diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c index af3d0cc..834d7b3 100644 --- a/vgasrc/vbe.c +++ b/vgasrc/vbe.c @@ -205,6 +205,7 @@ static void vbe_104f02(struct bregs *regs) { dprintf(1, "VBE mode set: %x\n", regs->bx); + check_extra_stack(); int mode = regs->bx & ~MF_VBEFLAGS; int flags = regs->bx & MF_VBEFLAGS; diff --git a/vgasrc/vgabios.h b/vgasrc/vgabios.h index fd796f2..985bbbb 100644 --- a/vgasrc/vgabios.h +++ b/vgasrc/vgabios.h @@ -100,6 +100,7 @@ extern u8 vgafont16alt[]; // vgainit.c extern struct video_save_pointer_s video_save_pointer_table; extern struct video_param_s video_param_table[29]; +void check_extra_stack(void); // vgabios.c extern int VgaBDF; diff --git a/vgasrc/vgainit.c b/vgasrc/vgainit.c index 8d12261..4616883 100644 --- a/vgasrc/vgainit.c +++ b/vgasrc/vgainit.c @@ -86,6 +86,21 @@ allocate_extra_stack(void) } } +void +check_extra_stack(void) +{ + if (!CONFIG_VGA_ALLOCATE_EXTRA_STACK) + return; + extern void entry_10(void); + if (GET_IVT(0x10).offset == (u32)entry_10) + return; + // Disable the extra stack if a VBE mode set call is made. This + // works around a bug in Windows Vista when the stack is in the + // e-segment. + dprintf(1, "Disabling SeaVGABIOS extra stack.\n"); + SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10)); +} + /**************************************************************** * Timer hook -- 1.9.3

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[Qemu-devel] [PATCH v5 for-2.3 00/28] hw/pc: implement multiple primary busses for pc machines
by Marcel Apfelbaum 16 Mar '15

16 Mar '15

Notes: - Sorry for the late submission, I was waiting for dynamic ACPI series to get merged in order to submit - my bad. - The prev version (v2) was wrongfully tagged by me as RFC, it was actually ready but not rebased. V3 only rebases with no actual functionality changed. - This series is not that big, patches 1-8 are really small and can be submitted separately, however I preferred to keep them here to get the whole picture. The series is fully functional. - Limitations: - Pxb's bus does not support hotplug. It will be addressed on top of this series because is already getting to big. - Depends on: - [SeaBIOS] [PATCH V3 0/2] fw/pci: better support for multiple host bridges - It was already reviewed/accepted by the maintainers, it will be merged after this series gets accepted. - You are more than welcome to try using: -device pxb-device,id=pxb,bus_nr=4,numa_node=1 -device e1000,bus=pxb,addr=0x1 -bios <patched with the above series> v4->v5: - Rebased on pci branch, tree: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git - Added PXB documentation (patch 28/28) - Addressed Gerd Hoffmann's review: - fix PXB behaviour if used with unsupported BIOS (patch 27/28) - Addressed Michael S. Tsirkin's review: - Removed assert in aml_index (patch 5/28) - Renamed pci_ functions to crs_ (patch 12/28) - used uint64_t variables instead of signed ones (patch 12/28) - Emit MEM/IO AML only for PXBs and i440fx (patch 26/28) - Addressed Shannon Zhao's review: - Changed build_append_int to build_append_byte in aml_or (patch 2/25) - Thanks to Igor and Kevin for reviews v3->v4: - Addressed Michael S. Tsirkin's review: - refactored build_prt method (patch 11/25) hw/apci: add _PRT method for extra PCI root busses - Addressed Igor Mammedov's reiew - add assert to aml_index (patch 5/25) - Fixed aml_equal implementation (patch 1/25) v2->v3: - Rebased on Michael S. Tsirkin's pci branch (that includes now all the dependencies) - Refactored acpi terms patch into multiple patches to match Igor's design. v1->v2: - Add support for multiple pxb devices. - Attach pxb's bus to specific NUMA node. - Got rid of the hacks from prev version. - Tested also for Win7 and Fedora 20, and for virtio blk devices. - Several bug-fixes resulting in a stable version ready for submission. Reasoning: We need multiple primary busess for a few reasons, the most important one is to be able to associate a pass-trough device with a guest NUMA node. The OS-es are able to associate a NUMA node only to a primary bus, not to a specific PCI device or a pci-2-pci bridge. PC machines support multiple NUMA nodes for CPUs and memory, however the IO was not yet supported. patch 1-9 adds the necessary acpi constructs based on Igor's series patch 10-13 implements acpi code needed to expose the pxb's primary bus to guests patch 14 separates the pci_bus code into a designated file patch 15-19 handles the implicit assumptions in code that only one primary bus can exist patch 20 handles the actual implementation of the PXB devices patch 21-22 enables the device patch 23 implements PXB map_irq function, (can be squashed into the actual PXB) patch 24-25 adds NUMA support patch 26 Emit MEM/IO AML only for PXBs and i440fx patch 27 Backward compatibility with SeaBIOS patch 28 PXB Documentation Marcel Apfelbaum (28): acpi: fix aml_equal term implementation acpi: add aml_or() term acpi: add aml_add() term acpi: add aml_lless() term acpi: add aml_index() term acpi: add aml_shiftleft() term acpi: add aml_shiftright() term acpi: add aml_increment() term acpi: add aml_while() term hw/acpi: add support for multiple root busses hw/apci: add _PRT method for extra PCI root busses hw/acpi: add _CRS method for extra root busses hw/acpi: remove from root bus 0 the crs resources used by other busses. hw/pci: move pci bus related code to separate files hw/pci: made pci_bus_is_root a PCIBusClass method hw/pci: made pci_bus_num a PCIBusClass method hw/pci: introduce TYPE_PCI_MAIN_HOST_BRIDGE interface hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query hw/pci: implement iteration over multiple host bridges hw/pci: introduce PCI Expander Bridge (PXB) hw/pci: inform bios if the system has more than one pci bridge hw/pci: piix - suport multiple host bridges hw/pxb: add map_irq func hw/pci_bus: add support for NUMA nodes hw/pxb: add numa_node parameter acpi: restrict the aml emission to PXB host bridges apci: fix PXB behaviour if used with unsupported BIOS docs: Add PXB documentation arch_init.c | 1 + docs/pci_expander_bridge.txt | 52 ++++ hw/acpi/aml-build.c | 76 +++++- hw/alpha/typhoon.c | 1 + hw/i386/acpi-build.c | 367 ++++++++++++++++++++++++- hw/i386/kvm/pci-assign.c | 1 + hw/i386/pc.c | 13 + hw/mips/gt64xxx_pci.c | 1 + hw/pci-bridge/Makefile.objs | 1 + hw/pci-bridge/pci_expander_bridge.c | 207 +++++++++++++++ hw/pci-host/bonito.c | 1 + hw/pci-host/grackle.c | 1 + hw/pci-host/piix.c | 63 ++++- hw/pci-host/ppce500.c | 1 + hw/pci-host/q35.c | 5 + hw/pci-host/uninorth.c | 1 + hw/pci/Makefile.objs | 2 +- hw/pci/pci.c | 501 +--------------------------------- hw/pci/pci_bus.c | 517 ++++++++++++++++++++++++++++++++++++ hw/pci/pci_host.c | 6 + hw/ppc/ppc4xx_pci.c | 1 + hw/scsi/megasas.c | 1 + hw/sh4/r2d.c | 1 + hw/sh4/sh_pci.c | 1 + hw/vfio/pci.c | 1 + hw/xen/xen_pt.c | 1 + include/hw/acpi/aml-build.h | 8 + include/hw/pci/pci.h | 6 +- include/hw/pci/pci_bus.h | 35 +++ include/hw/pci/pci_host.h | 13 + include/sysemu/sysemu.h | 1 + 31 files changed, 1377 insertions(+), 510 deletions(-) create mode 100644 docs/pci_expander_bridge.txt create mode 100644 hw/pci-bridge/pci_expander_bridge.c create mode 100644 hw/pci/pci_bus.c -- 2.1.0

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[PATCH v4 0/2] boot: switch default menu key to ESC
by Paolo Bonzini 16 Mar '15

16 Mar '15

Patch 1 applies a small improvement to user experience, as suggested by Matt DeVillier. Then patch 2 makes the switch. v3->v4: also update docs/Runtime_config.md. Paolo Bonzini (2): boot.c: delay exiting boot if menu key is ESC boot: switch default menu key to ESC docs/Runtime_config.md | 4 ++-- src/boot.c | 12 +++++++++--- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.3.0

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seabios stable release
by Gerd Hoffmann 16 Mar '15

16 Mar '15

Hi, Looks like we need a stable release branch for 1.8 and roll out a 1.8.1 release with some fixes for qemu. Issue #1: support for multiple pci roots. Issue #2: There is a (not-yet fixed) emulation failure with newer intel processors, apparently triggered by seabios commit 0673b7870063a3affbad9046fb6d385a4e734c19 Thread starts here: https://lists.gnu.org/archive/html/qemu-devel/2015-03/msg01140.html Other known issues in 1.8 which should be addressed in 1.8.1? cheers, Gerd

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Re: [SeaBIOS] error in write and read from usb hid device
by Kevin O'Connor 16 Mar '15

16 Mar '15

On Mon, Mar 16, 2015 at 08:47:13AM +0330, Navid Movahedi wrote: > Hi > Is there a mechanism to save log messages at boot time? See http://seabios.org/Debugging > I tested again and found that ehci_wait_td function timeouts in all > execution of for loop including first. > which registers you want to know? > i got these information from log messages: > > pipe->qh.current = 0x1eff8d80 > pipe->qh.token = 0x00400141 > pipe->qh.qtd_next = 0x1efff140 > td->token = 0x00400c80 > pipe->qh.info1 = 0x00400202 > pipe->qh.info2 = 0x00400202 I need to see a copy of the full log in order to help. > for uhci i used vmware workstation and it works perfectly and i can send > and receive data from hid device, but my real hardware does not have uhci > controller , instead it has 2 EHCI controller with rate matching hub, so i > should use ehci driver for this kind of controller. So, you are using coreboot+seabios on vmware and coreboot+seabios on real hardware as well? -Kevin

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Re: [SeaBIOS] error in write and read from usb hid device
by Kevin O'Connor 16 Mar '15

16 Mar '15

On Sun, Mar 15, 2015 at 12:32:04PM +0330, Navid Movahedi wrote: > Hi > I have a usb 1 HID device with 2 endpoints, 1 in, 1 out, and i want to > enumerate this usb device with seabios at boot time, so i hacked > seabios hid source code and add needed codes for this device. now > device is full functional with uhci driver in vmware and i have no > problem with read and write to device . the problem is for machines > with ehci controllers that don't have companion uhci controller and > uses rate matching hub to connect to this usb 1 device. The currewnt > status for this kind of controller is that the device is detected and > configured and 2 endpoints and corresponding 2 interrupt pipes are > allocated and initialized but when i use usb_send_pipe function to > write to device , error occurs . error is Timeout in ehci_wait_td > function in this section of code: > > for (i=0, td=tds; i<STACKQTDS; i++, td++) { > ret = ehci_wait_td(pipe, td, end); > if (ret) > return -1; > } > > timeout occurs for second td. i called usb_send_pipe function in this way: > > usb_send_pipe(out_pipe, USB_DIR_OUT , NULL , data, 64); > > is it correct? > > How can i solve this problem? We'd need to see the full seabios log in order to help. When the EHCI controller complains, it should also print out some ehci registers which give further information on what the controller was doing at the time of the error. Was this second ehci setup also on vmware or on some other emulator/real hardware? -Kevin

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