SeaBIOS

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Re: [SeaBIOS] [PATCH v10 3/6] Support for BIOS interrupt handler
by Stefan Berger 30 Mar '15

30 Mar '15

On 03/27/2015 03:58 AM, Xu, Quan wrote: > >> -----Original Message----- >> From: Xu, Quan >> Sent: Friday, March 27, 2015 10:01 AM >> To: 'Stefan Berger'; Kevin O'Connor >> Cc: seabios(a)seabios.org; stefano.stabellini(a)eu.citrix.com >> Subject: RE: [PATCH v10 3/6] Support for BIOS interrupt handler >> >> >> >>> -----Original Message----- >>> From: Stefan Berger [mailto:stefanb@linux.vnet.ibm.com] >>> Sent: Thursday, March 26, 2015 7:04 PM >>> To: Xu, Quan; Kevin O'Connor >>> Cc: seabios(a)seabios.org; stefano.stabellini(a)eu.citrix.com >>> Subject: Re: [PATCH v10 3/6] Support for BIOS interrupt handler >>> >>> On 03/26/2015 07:01 AM, Xu, Quan wrote: >>>>> -----Original Message----- >>>>> From: Stefan Berger [mailto:stefanb@linux.vnet.ibm.com] >>>>> Sent: Thursday, March 26, 2015 6:18 PM >>>>> To: Kevin O'Connor; Xu, Quan >>>>> Cc: seabios(a)seabios.org; stefano.stabellini(a)eu.citrix.com >>>>> Subject: Re: [PATCH v10 3/6] Support for BIOS interrupt handler >>>>> >>>>> On 03/25/2015 06:42 PM, Kevin O'Connor wrote: >>>>>> On Tue, Mar 24, 2015 at 11:10:03AM -0400, Stefan Berger wrote: >>>>>>> On 03/23/2015 08:13 PM, Kevin O'Connor wrote: >>>>>>>> Because of the mixed 16bit/32bit code in SeaBIOS, all assembler >>>>>>>> must use size suffixes - so the above should be "roll" instead of "rol". >>>>>>> Ok, fixed. >>>>>>> >>>>>>>> As before - both issues are minor and can be addressed after >>>>>>>> merge (as long as there is agreement that the sha1.c file can be >>>>>>>> licensed as LGPLv3). >>>>>>> It can have that license. I can post v11 or you can modify it, >>>>>>> either way is fine. >>>>>> Thanks. I pushed the first three patches into a test branch at: >>>>>> >>>>>> https://github.com/KevinOConnor/seabios/tree/tcg-testing >>>>>> >>>>>> I'd like to get confirmation that this works for the Xen >>>>>> requirements before merging. >>>>> I don't use Xen. I hope that Quan will provide feedback. >>>>> >>>>> Stefan >>>> Sure, I am glad to help you test it :):) Try to >>>> https://github.com/KevinOConnor/seabios/tree/tcg-testing ?? >>> Yes. >>> >>> Stefan >> Just for check, >> I can NOT git clone https://github.com/KevinOConnor/seabios/tree/tcg-testing >> I can clone https://github.com/KevinOConnor/seabios and checkout * tcg-testing >> branch. >> Correct? >> >> Quan > Share the test result first. It is not working with Xen vTPM. > The log from vtpm mini-os: > > [.. ] > tpm_testing.c:229: Debug: verify plain text > tpm_testing.c:261: Info: Self-Test succeeded > tpm_startup.c:43: Info: TPM_Startup(1) > Tpmback:Info Frontend 0/0 connected > tpm_cmd_handler.c:4217: Debug: tpm_handle_command(0) > tpm_cmd_handler.c:3514: Debug: [TPM_TAG_RQU_COMMAND] > tpm_cmd_handler.c:3537: Debug: [TPM_ORD_Startup] > tpm_startup.c:43: Info: TPM_Startup(1) > tpm_cmd_handler.c:4151: Info: TPM command failed: (0x26) The command was received in the wrong sequence > relative to TPM_Init and a subsequent TPM_Startup. > [..] > > > In my opinion, we need this patch for Xen vTPM too. Which patch is 'this patch'? Does the above indicate that TPM_Startup(1) is sent twice to the Xen vTPM? Besides SeaBIOS, what else is sending a TPM_Startup()? If there is something else in Xen that sends a TPM_Startup() to the TPM, before SeaBIOS does, then the following code may apply as well: This part is from src/tcgbios.c. + rc = build_and_send_cmd(TPM_ORD_Startup, + Startup_ST_CLEAR, sizeof(Startup_ST_CLEAR), + NULL, 10, &returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, "Return code from TPM_Startup = 0x%08x\n", + returnCode); + + if (CONFIG_COREBOOT) { Here you could add a check whether you are running on Xen and ignore the error returned from TPM_Startup(). + /* with other firmware on the system the TPM may already have been + * initialized + */ + if (returnCode == TPM_INVALID_POSTINIT) + returnCode = 0; + } + + if (rc || returnCode) + goto err_exit; Regards, Stefan > now Xen vTPM is working with two basic functions: TPM TCPA / SSDT and registers reset > in my previous seabios patch. > > > Quan > > >>

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Re: [SeaBIOS] [PATCH v10 3/6] Support for BIOS interrupt handler
by Stefan Berger 27 Mar '15

27 Mar '15

On 03/26/2015 07:01 AM, Xu, Quan wrote: > >> -----Original Message----- >> From: Stefan Berger [mailto:stefanb@linux.vnet.ibm.com] >> Sent: Thursday, March 26, 2015 6:18 PM >> To: Kevin O'Connor; Xu, Quan >> Cc: seabios(a)seabios.org; stefano.stabellini(a)eu.citrix.com >> Subject: Re: [PATCH v10 3/6] Support for BIOS interrupt handler >> >> On 03/25/2015 06:42 PM, Kevin O'Connor wrote: >>> On Tue, Mar 24, 2015 at 11:10:03AM -0400, Stefan Berger wrote: >>>> On 03/23/2015 08:13 PM, Kevin O'Connor wrote: >>>>> Because of the mixed 16bit/32bit code in SeaBIOS, all assembler must >>>>> use size suffixes - so the above should be "roll" instead of "rol". >>>> Ok, fixed. >>>> >>>>> As before - both issues are minor and can be addressed after merge >>>>> (as long as there is agreement that the sha1.c file can be licensed >>>>> as LGPLv3). >>>> It can have that license. I can post v11 or you can modify it, either >>>> way is fine. >>> Thanks. I pushed the first three patches into a test branch at: >>> >>> https://github.com/KevinOConnor/seabios/tree/tcg-testing >>> >>> I'd like to get confirmation that this works for the Xen requirements >>> before merging. >> I don't use Xen. I hope that Quan will provide feedback. >> >> Stefan > Sure, I am glad to help you test it :):) > Try to https://github.com/KevinOConnor/seabios/tree/tcg-testing ?? Yes. Stefan

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Methods to reduce bios image size
by Bruce Rogers 26 Mar '15

26 Mar '15

All, When building SeaBIOS in the context of QEMU v2.3-rc0 using various openSUSE versions we found that some recent versions overflowed the 128K limit imposed for bios.bin. The Makefile fails with the suggestion of using a more recent toolset or of eliminating some features to make it fit. Neither of those are options in this case. Of course another option is to review the code for places where variables or strings can be reduced in size without changing functionality. That doesn't buy us all that much, but enough for all of our cases except the oldest toolset. I'll post the patches I came up with during this review of the SeaBIOS code shortly to see what people think. The 128K bios.bin needed by older QEMU machine types doesn't need new functionality, but some future SeaBIOS changes will undoubtedly still cause it to continue to grow a bit. Since we are right at the boundary of overflowing 128K, I thought it was worth investing some effort in backing away from that limit so we don't have to constantly worry about every small change causing an issue there. In addition to the above mentioned data size reductions, another thing I noticed was that the e820 array is 32 entries, as given by BUILD_MAX_E820. It appears that QEMU only will ever fill 16 of those entries, so perhaps it would make sense to reduce that size when the usage is for QEMU only. As a more general query, I was wondering if anyone else knew of places where the size of SeaBIOS could be reduced? I'd be happy to try to help make that happen. Thanks, Bruce Rogers

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[PATCH v10 0/6] Add TPM support to SeaBIOS
by Stefan Berger 26 Mar '15

26 Mar '15

This is a repost of a series of patches providing TPM support to SeaBIOS. As an addition, this patch series now works on the Acer C720 Chromebook with limitations (S3 not getting invoked; no logging into TCPA table). The patch series cleanly applies to a checkout of b4581224. The following set of patches add TPM and Trusted Computing support to SeaBIOS. In particular the patches add: - a TPM driver for the Qemu's TPM TIS emulation - Support for initialzation of the TPM - init of TCPA logging table - Support for the TCG BIOS extensions (1ah handler [ah = 0xbb]) (used by trusted grub; http://trousers.sourceforge.net/grub.html) - Static Root of Trusted for Measurement (SRTM) support - Support for S3 resume (sends command to TPM upon resume) - Support for sending control messages from the OS to the BIOS and have the BIOS control certain life-cycle aspects of the TPM following those messages - TPM-specific menu for controlling aspects of the TPM All implementations necessarily follow specifications. When all patches are applied the following services are available - SSDT ACPI table for TPM support - initialization of the TPM upon VM start and S3 resume - Static root of trust for measurements (SRTM) that measures (some) data of SeaBIOS in TCPA ACPI table - 1ah interrupt handler offering APIs for measuring and sending commands to the TPM (trusted grub uses them) - With an extensions to QEMU's TPM SSDT: The root user in Linux (for example) can send the above mentioned control messages to the BIOS and have the BIOS act upon them - User menu for controlling aspects of the state of the TPM Stefan Berger (6): Add an implementation of a TPM TIS driver Implementation of the TCG BIOS extensions Support for BIOS interrupt handler Add 'measurement' code to the BIOS Support for TPM Physical Presence Interface Add a menu for TPM control Makefile | 5 +- src/Kconfig | 7 + src/boot.c | 27 +- src/cdrom.c | 11 + src/clock.c | 13 + src/config.h | 1 + src/hw/tpm_drivers.c | 291 +++++++ src/hw/tpm_drivers.h | 90 +++ src/optionroms.c | 4 + src/post.c | 14 + src/resume.c | 3 + src/sha1.c | 145 ++++ src/sha1.h | 8 + src/std/acpi.h | 20 + src/tcgbios.c | 2186 ++++++++++++++++++++++++++++++++++++++++++++++++++ src/tcgbios.h | 454 +++++++++++ src/util.h | 2 + src/x86.h | 7 + 18 files changed, 3283 insertions(+), 5 deletions(-) create mode 100644 src/hw/tpm_drivers.c create mode 100644 src/hw/tpm_drivers.h create mode 100644 src/sha1.c create mode 100644 src/sha1.h create mode 100644 src/tcgbios.c create mode 100644 src/tcgbios.h -- 1.9.3

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Re: [SeaBIOS] [coreboot] Booting Windows 8 failed
by Kevin O'Connor 25 Mar '15

25 Mar '15

On Wed, Mar 25, 2015 at 12:14:00PM -0700, David Hendricks wrote: > On Mon, Mar 23, 2015 at 7:27 PM, Bao, Zheng <Zheng.Bao(a)amd.com> wrote: > > I am porting the coreboot to a platform with a new AMD APU, which is close > > to Kabini and Mullins. > > Now the board can boot Ubuntu and Windows 7. But it failed to boot Windows > > 8. > > It crashes at a very early stage, which seems to be Windows bootloader. > > The debug message of SeaBIOS is attached. > > > > The interrupt routine installed by SeaBIOS still work. We can see > > handle_13, handle_08, handle_1a are called once in a while. > > There is no BSOD. There is only a windows logo on the monitor, without > > progress ring of Windows 8. > > Even the debug version of windows 8 doesn't help, because it crashes > > before the image is loaded. > > > > Is there any more way to debug windows 8 bootloader? There have been success reports with SeaBIOS booting Windows 8, so it's not a general win8 problem. If possible, try to pull the disk image into a QEMU VM and see if it has the same crash when running QEMU with a native instance of SeaBIOS. Also, make sure the problem is still present with SeaBIOS debug level 1 - very high debug levels are known to cause issues with some software. -Kevin

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Re: [SeaBIOS] [coreboot] Booting Windows 8 failed
by David Hendricks 25 Mar '15

25 Mar '15

[+seabios, coreboot --> bcc] On Mon, Mar 23, 2015 at 7:27 PM, Bao, Zheng <Zheng.Bao(a)amd.com> wrote: > I am porting the coreboot to a platform with a new AMD APU, which is close > to Kabini and Mullins. > Now the board can boot Ubuntu and Windows 7. But it failed to boot Windows > 8. > It crashes at a very early stage, which seems to be Windows bootloader. > The debug message of SeaBIOS is attached. > > The interrupt routine installed by SeaBIOS still work. We can see > handle_13, handle_08, handle_1a are called once in a while. > There is no BSOD. There is only a windows logo on the monitor, without > progress ring of Windows 8. > Even the debug version of windows 8 doesn't help, because it crashes > before the image is loaded. > > Is there any more way to debug windows 8 bootloader? > > Zheng > > > serial output > --------------------- > ....... > ....... > handle_08 > enter handle_15: > a=0000e820 b=00000006 c=00000018 d=534d4150 ds=0000 es=3004 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a25 f=0256 > enter handle_13: > a=00004200 b=00000000 c=00000000 d=00000080 ds=3024 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a1d f=0256 > disk_op d=0x000f98e0 lba=0 buf=0x00030000 count=1 cmd=2 > AHCI/0: send cmd ... > handle_08 > AHCI/0: ... intbits 0x1, status 0x50 ... > AHCI/0: ... finished, status 0x50, OK > ahci disk read, lba 0, count 1, buf 0x00030000, rc 0 > enter handle_13: > a=00004200 b=00000000 c=00000000 d=00000080 ds=3204 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a1d f=0256 > disk_op d=0x000f98e0 lba=2048 buf=0x00030000 count=16 cmd=2 > AHCI/0: send cmd ... > AHCI/0: ... intbits 0x1, status 0x50 ... > AHCI/0: ... finished, status 0x50, OK > ahci disk read, lba 800, count 10, buf 0x00030000, rc 0 > enter handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > handle_08 > enter handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > enter handle_13: > a=00004200 b=00000000 c=00000000 d=00000080 ds=3804 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a1d f=0256 > disk_op d=0x000f98e0 lba=7166912 buf=0x00030000 count=64 cmd=2 > AHCI/0: send cmd ... > handle_08 > AHCI/0: ... intbits 0x1, status 0x50 ... > AHCI/0: ... finished, status 0x50, OK > ahci disk read, lba 6d5bc0, count 40, buf 0x00030000, rc 0 enter > handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > enter handle_13: > a=00004200 b=00000000 c=00000000 d=00000080 ds=3204 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a1d f=0256 > disk_op d=0x000f98e0 lba=31249832 buf=0x00030000 count=16 cmd=2 > AHCI/0: send cmd ... > handle_08 > AHCI/0: ... intbits 0x1, status 0x50 ... > AHCI/0: ... finished, status 0x50, OK > ahci disk read, lba 1dcd5a8, count 10, buf 0x00030000, rc 0 enter > handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > enter handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > enter handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > handle_08 > enter handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > enter handle_1a: > a=00000200 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > enter handle_1a: > a=00000400 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > enter handle_1a: > a=00000000 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=9000 > si=00000000 di=00000000 bp=00000000 sp=0000ffd6 cs=2000 ip=0a39 f=0256 > handle_08 > agesawrapper_amdinitmmio() entry > agesawrapper_amdinitmmio() returned AGESA_SUCCESS > > > coreboot-4.0-6798-gdd6d81f-dirty Thu Mar 19 20:02:01 CST 2015 starting... > BSP Family_Model: > cpu_init_detectedx = 00000000 > agesawrapper_amdinitreset() entry > AmdCreateStruct, 188, InterfaceParams->StdHeader.HeapBasePtr=400000 > Fch OEM config in INIT RESET Done > agesawrapper_amdinitreset() returned AGESA_SUCCESS Got past > agesawrapper_amdinitreset > agesawrapper_amdinitearly() entry > AmdCreateStruct, 188, InterfaceParams->StdHeader.HeapBasePtr=400000 > AmdInitEarly, 239, &EarlyParams->StdHeader=400290 AmdInitEarly, 247, > EarlyParams->StdHeader=0 AmdInitEarly, 273, EarlyParams->StdHeader=0 > AmdInitEarly, 283, EarlyParams->StdHeader=0 AmdInitEarly, 297, > EarlyParams->StdHeader=0 GnbGetScsDataCZ, 183:PspDir=ff860000 > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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[PATCH] Eliminate some duplicate string segments to reduce bios image size
by Bruce Rogers 24 Mar '15

24 Mar '15

In some build environments, we are running up against the 128K bios size limit. This change simply takes larger string segments which are used in printf style messages and uses a single copy, now referenced with a %s specifier, resulting in the needed space savings. Signed-off-by: Bruce Rogers <brogers(a)suse.com> --- src/boot.c | 20 +++++++++++--------- src/bootsplash.c | 5 +++-- src/fw/paravirt.c | 8 +++++--- src/fw/pciinit.c | 19 ++++++++++--------- src/hw/usb-hub.c | 9 +++++---- src/hw/usb-msc.c | 6 ++++-- 6 files changed, 38 insertions(+), 29 deletions(-) diff --git a/src/boot.c b/src/boot.c index d6b1fb7..de37041 100644 --- a/src/boot.c +++ b/src/boot.c @@ -25,6 +25,8 @@ * Boot priority ordering ****************************************************************/ +static const char *no_boot_dev_str = "No bootable device."; +static const char *boot_str = "Booting from "; static char **Bootorder VARVERIFY32INIT; static int BootorderCount; @@ -587,7 +589,7 @@ bcv_prepboot(void) static void call_boot_entry(struct segoff_s bootsegip, u8 bootdrv) { - dprintf(1, "Booting from %04x:%04x\n", bootsegip.seg, bootsegip.offset); + dprintf(1, "%s%04x:%04x\n", boot_str, bootsegip.seg, bootsegip.offset); struct bregs br; memset(&br, 0, sizeof(br)); br.flags = F_IF; @@ -641,7 +643,7 @@ boot_cdrom(struct drive_s *drive_g) { if (! CONFIG_CDROM_BOOT) return; - printf("Booting from DVD/CD...\n"); + printf("%sDVD/CD...\n", boot_str); int status = cdrom_boot(drive_g); if (status) { @@ -664,7 +666,7 @@ boot_cbfs(struct cbfs_file *file) { if (!CONFIG_COREBOOT_FLASH) return; - printf("Booting from CBFS...\n"); + printf("%sCBFS...\n", boot_str); cbfs_run_payload(file); } @@ -672,7 +674,7 @@ boot_cbfs(struct cbfs_file *file) static void boot_rom(u32 vector) { - printf("Booting from ROM...\n"); + printf("%sROM...\n", boot_str); struct segoff_s so; so.segoff = vector; call_boot_entry(so, 0); @@ -683,10 +685,10 @@ static void boot_fail(void) { if (BootRetryTime == (u32)-1) - printf("No bootable device.\n"); + printf("%s\n", no_boot_dev_str); else - printf("No bootable device. Retrying in %d seconds.\n" - , BootRetryTime/1000); + printf("%s Retrying in %d seconds.\n", no_boot_dev_str, + BootRetryTime/1000); // Wait for 'BootRetryTime' milliseconds and then reboot. u32 end = irqtimer_calc(BootRetryTime); for (;;) { @@ -712,11 +714,11 @@ do_boot(int seq_nr) struct bev_s *ie = &BEV[seq_nr]; switch (ie->type) { case IPL_TYPE_FLOPPY: - printf("Booting from Floppy...\n"); + printf("%sFloppy...\n", boot_str); boot_disk(0x00, CheckFloppySig); break; case IPL_TYPE_HARDDISK: - printf("Booting from Hard Disk...\n"); + printf("%sHard Disk...\n", boot_str); boot_disk(0x80, 1); break; case IPL_TYPE_CDROM: diff --git a/src/bootsplash.c b/src/bootsplash.c index c572685..e28d264 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -16,6 +16,7 @@ #include "string.h" // memset #include "util.h" // enable_bootsplash +static const char *decode_failed_str = "_decode failed with return code "; /**************************************************************** * Helper functions @@ -154,7 +155,7 @@ enable_bootsplash(void) dprintf(5, "Decoding bootsplash.jpg\n"); ret = jpeg_decode(jpeg, filedata); if (ret) { - dprintf(1, "jpeg_decode failed with return code %d...\n", ret); + dprintf(1, "jpeg%s%d...\n", decode_failed_str, ret); goto done; } jpeg_get_size(jpeg, &width, &height); @@ -168,7 +169,7 @@ enable_bootsplash(void) dprintf(5, "Decoding bootsplash.bmp\n"); ret = bmp_decode(bmp, filedata, filesize); if (ret) { - dprintf(1, "bmp_decode failed with return code %d...\n", ret); + dprintf(1, "bmp%s%d...\n", decode_failed_str, ret); goto done; } bmp_get_size(bmp, &width, &height); diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index db22ae8..868435a 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -36,6 +36,8 @@ int PlatformRunningOn VARFSEG; */ #define KVM_CPUID_SIGNATURE 0x40000000 +static const char *running_on_qemu_str = "Running on QEMU ("; + static void kvm_detect(void) { unsigned int eax, ebx, ecx, edx; @@ -73,13 +75,13 @@ static void qemu_detect(void) PlatformRunningOn |= PF_QEMU; switch (d) { case 0x1237: - dprintf(1, "Running on QEMU (i440fx)\n"); + dprintf(1, "%si440fx)\n", running_on_qemu_str); break; case 0x29c0: - dprintf(1, "Running on QEMU (q35)\n"); + dprintf(1, "%sq35)\n", running_on_qemu_str); break; default: - dprintf(1, "Running on QEMU (unknown nb: %04x:%04x)\n", v, d); + dprintf(1, "%sunknown nb: %04x:%04x)\n", running_on_qemu_str, v, d); break; } kvm_detect(); diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index ac39d23..63018e4 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -27,6 +27,10 @@ #define PCI_BRIDGE_MEM_MIN (1<<21) // 2M == hugepage size #define PCI_BRIDGE_IO_MIN 0x1000 // mandated by pci bridge spec +static const char *pri_bus_str = "PCI: primary bus = "; +static const char *sec_bus_str = "PCI: secondary bus = "; +static const char *sub_bus_str = "PCI: subordinate bus = "; + static const char *region_type_name[] = { [ PCI_REGION_TYPE_IO ] = "io", [ PCI_REGION_TYPE_MEM ] = "mem", @@ -425,7 +429,6 @@ static void pci_bios_init_platform(void) } } - /**************************************************************** * Bus initialization ****************************************************************/ @@ -456,21 +459,20 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS); if (pribus != bus) { - dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus); + dprintf(1, "%s0x%x -> 0x%x\n", pri_bus_str, pribus, bus); pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus); } else { - dprintf(1, "PCI: primary bus = 0x%x\n", pribus); + dprintf(1, "%s0x%x\n", pri_bus_str, pribus); } u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS); (*pci_bus)++; if (*pci_bus != secbus) { - dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n", - secbus, *pci_bus); + dprintf(1, "%s0x%x -> 0x%x\n", sec_bus_str, secbus, *pci_bus); secbus = *pci_bus; pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus); } else { - dprintf(1, "PCI: secondary bus = 0x%x\n", secbus); + dprintf(1, "%s0x%x\n", sec_bus_str, secbus); } /* set to max for access to all subordinate buses. @@ -481,11 +483,10 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) pci_bios_init_bus_rec(secbus, pci_bus); if (subbus != *pci_bus) { - dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n", - subbus, *pci_bus); + dprintf(1, "%s0x%x -> 0x%x\n", sub_bus_str, subbus, *pci_bus); subbus = *pci_bus; } else { - dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus); + dprintf(1, "%s0x%x\n", sub_bus_str, subbus); } pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus); } diff --git a/src/hw/usb-hub.c b/src/hw/usb-hub.c index 54e341b..337385d 100644 --- a/src/hw/usb-hub.c +++ b/src/hw/usb-hub.c @@ -11,6 +11,8 @@ #include "usb-hub.h" // struct usb_hub_descriptor #include "util.h" // timer_calc +static const char *port_hub_fail_str = "Failure on hub port "; + static int get_hub_desc(struct usb_pipe *pipe, struct usb_hub_descriptor *desc) { @@ -82,7 +84,6 @@ get_port_status(struct usbhub_s *hub, int port, struct usb_port_status *sts) mutex_unlock(&hub->lock); return ret; } - // Check if device attached to port static int usb_hub_detect(struct usbhub_s *hub, u32 port) @@ -90,7 +91,7 @@ usb_hub_detect(struct usbhub_s *hub, u32 port) struct usb_port_status sts; int ret = get_port_status(hub, port, &sts); if (ret) { - dprintf(1, "Failure on hub port %d detect\n", port); + dprintf(1, "%s%d detect\n", port_hub_fail_str, port); return -1; } return (sts.wPortStatus & USB_PORT_STAT_CONNECTION) ? 1 : 0; @@ -102,7 +103,7 @@ usb_hub_disconnect(struct usbhub_s *hub, u32 port) { int ret = clear_port_feature(hub, port, USB_PORT_FEAT_ENABLE); if (ret) - dprintf(1, "Failure on hub port %d disconnect\n", port); + dprintf(1, "%s%d disconnect\n", port_hub_fail_str, port); } // Reset device on port @@ -142,7 +143,7 @@ usb_hub_reset(struct usbhub_s *hub, u32 port) >> USB_PORT_STAT_SPEED_SHIFT); fail: - dprintf(1, "Failure on hub port %d reset\n", port); + dprintf(1, "%s%d reset\n", port_hub_fail_str, port); usb_hub_disconnect(hub, port); return -1; } diff --git a/src/hw/usb-msc.c b/src/hw/usb-msc.c index d90319f..9c6b3e2 100644 --- a/src/hw/usb-msc.c +++ b/src/hw/usb-msc.c @@ -50,6 +50,8 @@ struct csw_s { u8 bCSWStatus; } PACKED; +static const char *cant_config_str = "Unable to configure USB MSC "; + static int usb_msc_send(struct usbdrive_s *udrive_gf, int dir, void *buf, u32 bytes) { @@ -158,7 +160,7 @@ usb_msc_lun_setup(struct usb_pipe *inpipe, struct usb_pipe *outpipe, int prio = bootprio_find_usb(usbdev, lun); int ret = scsi_drive_setup(&drive->drive, "USB MSC", prio); if (ret) { - dprintf(1, "Unable to configure USB MSC drive.\n"); + dprintf(1, "%sdrive.\n", cant_config_str); free(drive); return -1; } @@ -213,7 +215,7 @@ usb_msc_setup(struct usbdevice_s *usbdev) return 0; fail: - dprintf(1, "Unable to configure USB MSC device.\n"); + dprintf(1, "%sdevice.\n", cant_config_str); usb_free_pipe(usbdev, inpipe); usb_free_pipe(usbdev, outpipe); return -1; -- 1.9.0

1 0

[PATCH] Reduce size of certain global variables to reduce bios size
by Bruce Rogers 24 Mar '15

24 Mar '15

In doing a pass through all the code, I found a number of global variables which were reasonable candidates to reduce in size, typically from int to u8. Also a large array in the keyboard code was packed. This change reduces the resulting size by 240 bytes in my case. Signed-off-by: Bruce Rogers <brogers(a)suse.com> --- src/boot.c | 16 ++++++++-------- src/bootsplash.c | 2 +- src/hw/usb-xhci.c | 31 +++++++++++++++---------------- src/hw/usb.c | 2 +- src/kbd.c | 2 +- src/stacks.c | 2 +- src/vgahooks.c | 6 +++--- 7 files changed, 30 insertions(+), 31 deletions(-) diff --git a/src/boot.c b/src/boot.c index d6b1fb7..8238f62 100644 --- a/src/boot.c +++ b/src/boot.c @@ -26,7 +26,7 @@ ****************************************************************/ static char **Bootorder VARVERIFY32INIT; -static int BootorderCount; +static u8 BootorderCount; static void loadBootOrder(void) @@ -240,7 +240,7 @@ int bootprio_find_usb(struct usbdevice_s *usbdev, int lun) ****************************************************************/ static int BootRetryTime; -static int CheckFloppySig = 1; +static u8 CheckFloppySig = 1; #define DEFAULT_PRIO 9999 @@ -520,8 +520,8 @@ struct bev_s { u32 vector; }; static struct bev_s BEV[20]; -static int BEVCount; -static int HaveHDBoot, HaveFDBoot; +static u8 BEVCount; +static u8 HaveHDBoot, HaveFDBoot; static void add_bev(int type, u32 vector) @@ -600,7 +600,7 @@ call_boot_entry(struct segoff_s bootsegip, u8 bootdrv) // Boot from a disk (either floppy or harddrive) static void -boot_disk(u8 bootdrv, int checksig) +boot_disk(u8 bootdrv, u8 checksig) { u16 bootseg = 0x07c0; @@ -700,7 +700,7 @@ boot_fail(void) // Determine next boot method and attempt a boot using it. static void -do_boot(int seq_nr) +do_boot(u8 seq_nr) { if (! CONFIG_BOOT) panic("Boot support not compiled in.\n"); @@ -740,14 +740,14 @@ do_boot(int seq_nr) call16_int(0x18, &br); } -int BootSequence VARLOW = -1; +u8 BootSequence VARLOW = -1; // Boot Failure recovery: try the next device. void VISIBLE32FLAT handle_18(void) { debug_enter(NULL, DEBUG_HDL_18); - int seq = BootSequence + 1; + u8 seq = BootSequence + 1; BootSequence = seq; do_boot(seq); } diff --git a/src/bootsplash.c b/src/bootsplash.c index c572685..0b66a04 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -91,7 +91,7 @@ find_videomode(struct vbe_info *vesa_info, struct vbe_mode_info *mode_info } } -static int BootsplashActive; +static u8 BootsplashActive; void enable_bootsplash(void) diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index fd58334..a92a8b3 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -271,16 +271,14 @@ static const char *speed_name[16] = { [ 4 ] = "Super", }; -static const int speed_from_xhci[16] = { - [ 0 ] = -1, - [ 1 ] = USB_FULLSPEED, - [ 2 ] = USB_LOWSPEED, - [ 3 ] = USB_HIGHSPEED, - [ 4 ] = USB_SUPERSPEED, - [ 5 ... 15 ] = -1, +static const u8 speed_from_xhci[] = { + [ 0 ] = USB_FULLSPEED, + [ 1 ] = USB_LOWSPEED, + [ 2 ] = USB_HIGHSPEED, + [ 3 ] = USB_SUPERSPEED, }; -static const int speed_to_xhci[] = { +static const u8 speed_to_xhci[] = { [ USB_FULLSPEED ] = 1, [ USB_LOWSPEED ] = 2, [ USB_HIGHSPEED ] = 3, @@ -350,23 +348,24 @@ xhci_hub_reset(struct usbhub_s *hub, u32 port) { struct usb_xhci_s *xhci = container_of(hub->cntl, struct usb_xhci_s, usb); u32 portsc = readl(&xhci->pr[port].portsc); - int rc; + unsigned int index; + int rc = -1; switch (xhci_get_field(portsc, XHCI_PORTSC_PLS)) { - case PLS_U0: - rc = speed_from_xhci[xhci_get_field(portsc, XHCI_PORTSC_SPEED)]; - break; case PLS_POLLING: xhci_print_port_state(3, __func__, port, portsc); portsc |= XHCI_PORTSC_PR; writel(&xhci->pr[port].portsc, portsc); if (wait_bit(&xhci->pr[port].portsc, XHCI_PORTSC_PED, XHCI_PORTSC_PED, 100) != 0) - return -1; + return rc; portsc = readl(&xhci->pr[port].portsc); - rc = speed_from_xhci[xhci_get_field(portsc, XHCI_PORTSC_SPEED)]; + // fall through + case PLS_U0: + index = xhci_get_field(portsc, XHCI_PORTSC_SPEED) - 1; + if (index < 4) + rc = speed_from_xhci[index]; break; default: - rc = -1; break; } @@ -834,7 +833,7 @@ xhci_alloc_inctx(struct usbdevice_s *usbdev, int maxepid) struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64]; slot->ctx[0] |= maxepid << 27; // context entries - slot->ctx[0] |= speed_to_xhci[usbdev->speed] << 20; + slot->ctx[0] |= (u32)speed_to_xhci[usbdev->speed] << 20; // Set high-speed hub flags. struct usbdevice_s *hubdev = usbdev->hub->usbdev; diff --git a/src/hw/usb.c b/src/hw/usb.c index 1b4ea8b..6ceeda5 100644 --- a/src/hw/usb.c +++ b/src/hw/usb.c @@ -278,7 +278,7 @@ set_configuration(struct usb_pipe *pipe, u16 val) * Initialization and enumeration ****************************************************************/ -static const int speed_to_ctlsize[] = { +static const u16 speed_to_ctlsize[] = { [ USB_FULLSPEED ] = 8, [ USB_LOWSPEED ] = 8, [ USB_HIGHSPEED ] = 64, diff --git a/src/kbd.c b/src/kbd.c index a5a1ad9..43ae351 100644 --- a/src/kbd.c +++ b/src/kbd.c @@ -289,7 +289,7 @@ static struct scaninfo { u16 control; u16 alt; u8 lock_flags; -} scan_to_scanascii[] VAR16 = { +} PACKED scan_to_scanascii[] VAR16 = { { none, none, none, none, none }, { 0x011b, 0x011b, 0x011b, 0x0100, none }, /* escape */ { 0x0231, 0x0221, none, 0x7800, none }, /* 1! */ diff --git a/src/stacks.c b/src/stacks.c index 1dbdfe9..e510a2f 100644 --- a/src/stacks.c +++ b/src/stacks.c @@ -742,7 +742,7 @@ mutex_unlock(struct mutex_s *mutex) * Thread preemption ****************************************************************/ -int CanPreempt VARFSEG; +u8 CanPreempt VARFSEG; static u32 PreemptCount; // Turn on RTC irqs and arrange for them to check the 32bit threads. diff --git a/src/vgahooks.c b/src/vgahooks.c index 6a4acfe..3fc716a 100644 --- a/src/vgahooks.c +++ b/src/vgahooks.c @@ -18,7 +18,7 @@ #define VH_INTEL 2 #define VH_SMI 3 -int VGAHookHandlerType VARFSEG; +u8 VGAHookHandlerType VARFSEG; static void handle_155fXX(struct bregs *regs) @@ -308,7 +308,7 @@ handle_155f(struct bregs *regs) return; } - int htype = GET_GLOBAL(VGAHookHandlerType); + u8 htype = GET_GLOBAL(VGAHookHandlerType); switch (htype) { case VH_VIA: via_155f(regs); break; case VH_INTEL: intel_155f(regs); break; @@ -325,7 +325,7 @@ handle_157f(struct bregs *regs) return; } - int htype = GET_GLOBAL(VGAHookHandlerType); + u8 htype = GET_GLOBAL(VGAHookHandlerType); switch (htype) { case VH_SMI: smi_157f(regs); break; default: handle_157fXX(regs); break; -- 1.9.0

1 0

[Mohon Peak] Console output behavior before and after call to int19h
by Patrick Agrain 24 Mar '15

24 Mar '15

Hello, Purpose: Get the output sent through int10h on an external serial link mapped on MEM space (PCIe board with OxPCIe952 from Startech). Hardware: Mohon Peak CRB with coreboot. PCIe board with OxPCIe952 from Startech. Bootable hard disk with GRUB and Linux. Code flow: (from my understanding) <...> ./src/post.c: mainint() |--> interactive_bootmenu() | |--> "Press ESC for boot menu." (sent through INT10h calls) | |--> startBoot() |--> "Jump to int19" |--> Call INT19h <INT19h handler> ./src/boot.c: do_boot() |--> "Booting from Hard Disk..." (sent through INT10h calls) |--> boot_disk() |--> Call INT13h <...> What works: Modified seabios to initialize PCIe board OxPCIe952. - Add field at the end of BDA to store the u32 base address of the additional UART ports. - Init the bridge after pci_probe(). - Store the base address of the additional UART ports during serial_setup(). Using sgabios with output set to 0x2f8 (uart1) works flawlessly. - All (dprintf-based) messages are sent on second UART port of the Mohon Peak. - All (printf-based, INT10h) messages are also displayed on second UART port of the Mohon Peak. - System boots. What almost works: Modified sgabios to display INT10h calls on MEM mapped UART port. - All (dprintf-based) messages are still sent on second UART port of the Mohon Peak. - Display of "Press ESC for boot menu." on OxPCIe952 : OK (any previous INT10h-based messages also displayed on OxPCIe952). - After call of INT19h, "Booting from Hard Disk..." is not displayed on OxPCIe952. - Mohon Peak remains in POST code F8h (like as for waiting a selection in the GRUB menu). Note: reducing debug level (20 -> 2) of int10h shows that the int10h-handler is called with the messages to be displayed, but nothing appears on OxPCIe952 side. What could be the reason of this behavior ? Any switch between 16-bit and 32-bit code execution ? Any suggestion is welcome. Regards, Patrick Agrain

2 2

Re: [SeaBIOS] Orom execution issue.
by Kevin O'Connor 24 Mar '15

24 Mar '15

On Mon, Mar 23, 2015 at 08:25:15PM +0530, Naresh G. Solanki wrote: > Dear All, > > I'm porting coreboot with seabios payload on a e6xx processor based board. > Seabios is executing properly but when it tries to execute vga bios of pcie > graphic card(copied @ C000:0000), it hangs and doesn't returns. > > Can anyone give me suggestion on how to find the cause of the issue and > resolve it so that it executes properly. It is often very difficult to trace option rom problems. If you post the full debug log, we can point out any obvious problems. -Kevin

2 1

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