SeaBIOS

seabios@seabios.org

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3801 discussions

[cross-post] QEMU fw_cfg DMA interface
by Marc Marí 21 Oct '15

21 Oct '15

Implementation of the FW CFG DMA interface. When running a Linux guest on top of QEMU, using the -kernel option and with fw_cfg DMA Linux boot support, this is the timing improvement for x86: Original QEMU and SeaBIOS QEMU startup time: .080 BIOS startup time: .060 Kernel setup time: .586 Total time: .726 QEMU and SeaBIOS with this patch series and fw_cfg DMA Linux boot support QEMU startup time: .080 BIOS startup time: .039 Kernel setup time: .005 Total time: .126 QEMU startup time is the time between the start and the first kvm_entry. BIOS startup time is the time between the first kvm_entry and the start of function do_boot, in SeaBIOS. Kernel setup time is the time between the start of the function do_boot in SeaBIOS and the jump to the Linux kernel. As you can see, both the BIOS (because of ACPI tables and other configurations) and the Linux kernel boot (because of the copy to memory) are greatly improved with this new interface. Also, this new interface is an addon to the old interface. Both interfaces are compatible and interchangeable. Changes from v1: - Take into account order of fields in the FWCfgDmaAccess structure - Check and change endianness of FWCfgDmaAccess fields - Change order of fields in the FWCfgDmaAccess structure - Add FW_CFG_DMA_CTL_SKIP feature for control field - Split FW_CFG_SIZE in QEMU - Make FW_CFG_ID a bitmap of features - Add 64 bit address support for the transfer. Trigger when writing the low address, and address is 0 by default and at the end of each transfer. - Align ports and addresses. - Preserve old fw_cfg_comb_valid behaviour in QEMU - Update documentation to reflect all these changes Changes from v2: - Make IOports fw_cfg DMA region a different IO region. - Reuse everything for MMIO and IOport DMA regions - Make transfer status only based on control field - Use DMA helpers instead of direct map/unmap - Change ARM fw_cfg DMA address space - Change Linux boot process to match linuxboot.S - Add select capabilities in the FWCfgDmaAccess struct - Update documentation to reflect all these changes Changes from v3: - Set properly fw_cfg DMA fields in ARM - Set fw_cfg DMA boot process properly (by Laszlo Ersek) - Add signature to fw_cfg DMA address field (by Kevin O'Connor) - Minor nitpicks Changes from v4: - Remove Linux fw_cfg boot from this series (will be sent separately) - Minor nitpicks

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Re: [SeaBIOS] [RFC PATCH] x86: Support booting SeaBIOS
by Simon Glass 19 Oct '15

19 Oct '15

Hi Bin, On 10 October 2015 at 02:57, Bin Meng <bmeng.cn(a)gmail.com> wrote: > Hi Simon, > > On Sat, Oct 3, 2015 at 10:29 PM, Simon Glass <sjg(a)chromium.org> wrote: >> Hi Bin, >> >> On 29 September 2015 at 11:17, Bin Meng <bmeng.cn(a)gmail.com> wrote: >>> SeaBIOS is an open source implementation of a 16-bit X86 BIOS. >>> It can run in an emulator or natively on X86 hardware with the >>> use of coreboot. With SeaBIOS's help, we can boot some OSes >>> that require 16-bit BIOS services like Windows/DOS. >>> >>> As U-Boot, we have to manually create a table where SeaBIOS gets >>> system information (eg: E820) from. The table unfortunately has >>> to follow the coreboot table format as SeaBIOS currently supports >>> booting as a coreboot payload. No U-Boot native support there. >>> >>> Booting SeaBIOS is done via U-Boot's bootelf command. >>> >>> This is the initial attempt to support booting SeaBIOS from U-Boot. >>> If the basic concept is good, I can spend time working on follow-on >>> patches to enable BIOS tables as well as graphics support. One issue >>> is that U-Boot x86 does not has a ROM file system like coreboot. >>> This brings difficulities to pass PCI option ROM to SeaBIOS, if we >>> don't modify SeaBIOS's source codes. Maybe we should promote CBFS >>> in U-Boot x86? >>> >>> This is tested on an Intel Crown Bay board with VGA card, booting >>> SeaBIOS then chain loading a GRUB on a USB drive, then Linux kernel >>> finally. >> >> Looks good to me. I think it is OK to use CBFS if needed - are you >> thinking of an option to build u-boot.rom as a CBFS filesystem? > > If using CBFS, that means we may have to abandon ifdtool? Or maybe > mixed usage of both tools? So far I'm not sure of the best approach. At present we have the ROM offsets stored mostly in Kconfig, with the MRC area in the SPI flash device tree node. The environment is also in Kconfig. What sort of option ROMs do you want to support? What other options does seabios provide? What does SEA stand for? [snip] Regards, Simon

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[PATCH] stacks: Use macro wrappers for call32() and stack_hop_back()
by Kevin O'Connor 15 Oct '15

15 Oct '15

The C code only uses _cfuncX_ prefixes for parameters to the call32(), stack_hop_back(), and call32_params() functions. It's simpler to use macro wrappers around those functions which provide the required prefix. This also changes the parameter order of stack_hop() and stack_hop_back() to use the more natural (func, params) ordering. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- docs/Linking_overview.md | 14 +++----------- src/block.c | 7 +++---- src/clock.c | 4 +--- src/hw/usb.c | 5 ++--- src/mouse.c | 3 +-- src/romlayout.S | 2 +- src/stacks.c | 25 ++++++++++--------------- src/stacks.h | 25 ++++++++++++++++++++----- 8 files changed, 41 insertions(+), 44 deletions(-) diff --git a/docs/Linking_overview.md b/docs/Linking_overview.md index 965e926..bcb8298 100644 --- a/docs/Linking_overview.md +++ b/docs/Linking_overview.md @@ -92,17 +92,9 @@ those situations where an address of a C function in another mode is required the build supports symbols with a special "\_cfuncX_" prefix. The layoutrom.py script detects these references and will emit a corresponding symbol definitions in the linker script that points to -the C code of the specified mode. This is typically seen with code -like: - -``` -extern void _cfunc32flat_process_op(void); -return call32(_cfunc32flat_process_op, 0, 0); -``` - -In the above example, when the build finds the symbol -"\_cfunc32flat_process_op" it will emit that symbol with the physical -address of the 32bit "flat" version of the process_op() C function. +the C code of the specified mode. The call32() and stack_hop_back() +macros automatically add the required prefix for C code, but the +prefixes need to be explicitly added in assembler code. Build garbage collection ------------------------ diff --git a/src/block.c b/src/block.c index 97e05fa..1762e2a 100644 --- a/src/block.c +++ b/src/block.c @@ -525,9 +525,8 @@ process_op_both(struct disk_op_s *op) if (!MODESEGMENT) return DISK_RET_EPARAM; // In 16bit mode and driver not found - try in 32bit mode - extern void _cfunc32flat_process_op_32(void); - return call32(_cfunc32flat_process_op_32 - , (u32)MAKE_FLATPTR(GET_SEG(SS), op), DISK_RET_EPARAM); + return call32(process_op_32, MAKE_FLATPTR(GET_SEG(SS), op) + , DISK_RET_EPARAM); } } @@ -625,5 +624,5 @@ send_disk_op(struct disk_op_s *op) if (! CONFIG_DRIVES) return -1; - return stack_hop((u32)op, GET_SEG(SS), __send_disk_op); + return stack_hop(__send_disk_op, op, GET_SEG(SS)); } diff --git a/src/clock.c b/src/clock.c index c73545b..e83e0f3 100644 --- a/src/clock.c +++ b/src/clock.c @@ -248,9 +248,7 @@ handle_1abb(struct bregs *regs) return; dprintf(DEBUG_tcg, "16: Calling tpm_interrupt_handler\n"); - extern void _cfunc32flat_tpm_interrupt_handler32(void); - call32(_cfunc32flat_tpm_interrupt_handler32, - (u32)MAKE_FLATPTR(GET_SEG(SS), regs), 0); + call32(tpm_interrupt_handler32, MAKE_FLATPTR(GET_SEG(SS), regs), 0); } // Unsupported diff --git a/src/hw/usb.c b/src/hw/usb.c index 2d5c224..e46092c 100644 --- a/src/hw/usb.c +++ b/src/hw/usb.c @@ -79,9 +79,8 @@ usb_poll_intr(struct usb_pipe *pipe_fl, void *data) case USB_TYPE_EHCI: return ehci_poll_intr(pipe_fl, data); case USB_TYPE_XHCI: ; - extern void _cfunc32flat_xhci_poll_intr(void); - return call32_params(_cfunc32flat_xhci_poll_intr, (u32)pipe_fl - , (u32)MAKE_FLATPTR(GET_SEG(SS), (u32)data), 0, -1); + return call32_params(xhci_poll_intr, pipe_fl + , MAKE_FLATPTR(GET_SEG(SS), data), 0, -1); } } diff --git a/src/mouse.c b/src/mouse.c index 6d1f5b7..b7ad7c6 100644 --- a/src/mouse.c +++ b/src/mouse.c @@ -280,8 +280,7 @@ invoke_mouse_handler(void) if (!CONFIG_MOUSE) return; if (need_hop_back()) { - extern void _cfunc16_invoke_mouse_handler(void); - stack_hop_back(0, 0, _cfunc16_invoke_mouse_handler); + stack_hop_back(invoke_mouse_handler, 0, 0); return; } ASSERT16(); diff --git a/src/romlayout.S b/src/romlayout.S index 7910806..7d65809 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -277,7 +277,7 @@ entry_pmm: movl $_cfunc32flat_handle_pmm, %eax // Setup: call32(handle_pmm, args, -1) leal PUSHBREGS_size+12(%esp, %ecx), %edx // %edx points to start of args movl $-1, %ecx - calll call32 + calll __call32 movw %ax, BREGS_eax(%esp) // Modify %ax:%dx to return %eax shrl $16, %eax movw %ax, BREGS_edx(%esp) diff --git a/src/stacks.c b/src/stacks.c index 583b456..40bd4d3 100644 --- a/src/stacks.c +++ b/src/stacks.c @@ -242,7 +242,7 @@ call16_smm(u32 eax, u32 edx, void *func) // Call a 32bit SeaBIOS function from a 16bit SeaBIOS function. u32 VISIBLE16 -call32(void *func, u32 eax, u32 errret) +__call32(void *func, u32 eax, u32 errret) { ASSERT16(); if (CONFIG_CALL32_SMM && GET_GLOBAL(HaveSmmCall32)) @@ -341,7 +341,7 @@ on_extra_stack(void) // Switch to the extra stack and call a function. u32 -stack_hop(u32 eax, u32 edx, void *func) +__stack_hop(u32 eax, u32 edx, void *func) { if (on_extra_stack()) return ((u32 (*)(u32, u32))func)(eax, edx); @@ -374,7 +374,7 @@ stack_hop(u32 eax, u32 edx, void *func) // Switch back to original caller's stack and call a function. u32 -stack_hop_back(u32 eax, u32 edx, void *func) +__stack_hop_back(u32 eax, u32 edx, void *func) { if (!MODESEGMENT) return call16(eax, edx, func); @@ -417,8 +417,7 @@ void VISIBLE16 _farcall16(struct bregs *callregs, u16 callregseg) { if (need_hop_back()) { - extern void _cfunc16__farcall16(void); - stack_hop_back((u32)callregs, callregseg, _cfunc16__farcall16); + stack_hop_back(_farcall16, callregs, callregseg); return; } ASSERT16(); @@ -612,8 +611,7 @@ check_irqs(void) return; } if (need_hop_back()) { - extern void _cfunc16_check_irqs(void); - stack_hop_back(0, 0, _cfunc16_check_irqs); + stack_hop_back(check_irqs, 0, 0); return; } if (MODE16) @@ -642,8 +640,7 @@ void VISIBLE16 wait_irq(void) { if (need_hop_back()) { - extern void _cfunc16_wait_irq(void); - stack_hop_back(0, 0, _cfunc16_wait_irq); + stack_hop_back(wait_irq, 0, 0); return; } asm volatile("sti ; hlt ; cli ; cld": : :"memory"); @@ -748,9 +745,8 @@ yield_preempt(void) void check_preempt(void) { - extern void _cfunc32flat_yield_preempt(void); if (CONFIG_THREADS && GET_GLOBAL(CanPreempt) && have_threads()) - call32(_cfunc32flat_yield_preempt, 0, 0); + call32(yield_preempt, 0, 0); } @@ -771,11 +767,10 @@ call32_params_helper(struct call32_params_s *params) } u32 -call32_params(void *func, u32 eax, u32 edx, u32 ecx, u32 errret) +__call32_params(void *func, u32 eax, u32 edx, u32 ecx, u32 errret) { ASSERT16(); struct call32_params_s params = {func, eax, edx, ecx}; - extern void _cfunc32flat_call32_params_helper(void); - return call32(_cfunc32flat_call32_params_helper - , (u32)MAKE_FLATPTR(GET_SEG(SS), &params), errret); + return call32(call32_params_helper, MAKE_FLATPTR(GET_SEG(SS), &params) + , errret); } diff --git a/src/stacks.h b/src/stacks.h index a3b031c..c71bdc8 100644 --- a/src/stacks.h +++ b/src/stacks.h @@ -10,17 +10,27 @@ // stacks.c extern int HaveSmmCall32; -u32 call32(void *func, u32 eax, u32 errret); +u32 __call32(void *func, u32 eax, u32 errret); +#define call32(func, eax, errret) ({ \ + extern void _cfunc32flat_ ##func (void); \ + __call32( _cfunc32flat_ ##func , (u32)(eax), (errret)); \ + }) extern u8 ExtraStack[], *StackPos; -u32 stack_hop(u32 eax, u32 edx, void *func); -u32 stack_hop_back(u32 eax, u32 edx, void *func); +u32 __stack_hop(u32 eax, u32 edx, void *func); +#define stack_hop(func, eax, edx) \ + __stack_hop((u32)(eax), (u32)(edx), (func)) +u32 __stack_hop_back(u32 eax, u32 edx, void *func); +#define stack_hop_back(func, eax, edx) ({ \ + extern void _cfunc16_ ##func (void); \ + __stack_hop_back((u32)(eax), (u32)(edx), _cfunc16_ ##func ); \ + }) int on_extra_stack(void); struct bregs; void farcall16(struct bregs *callregs); void farcall16big(struct bregs *callregs); void __call16_int(struct bregs *callregs, u16 offset); #define call16_int(nr, callregs) do { \ - extern void irq_trampoline_ ##nr (); \ + extern void irq_trampoline_ ##nr (void); \ __call16_int((callregs), (u32)&irq_trampoline_ ##nr ); \ } while (0) void reset(void); @@ -39,7 +49,12 @@ void start_preempt(void); void finish_preempt(void); int wait_preempt(void); void check_preempt(void); -u32 call32_params(void *func, u32 eax, u32 edx, u32 ecx, u32 errret); +u32 __call32_params(void *func, u32 eax, u32 edx, u32 ecx, u32 errret); +#define call32_params(func, eax, edx, ecx, errret) ({ \ + extern void _cfunc32flat_ ##func (void); \ + __call32_params( _cfunc32flat_ ##func , (u32)(eax), (u32)(edx) \ + , (u32)(ecx), (errret)); \ + }) // Inline functions -- 2.4.3

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[PATCH 00/10] Misc code cleanups
by Kevin O'Connor 15 Oct '15

15 Oct '15

This series is a fallout of work I was doing to test PAE. I think the cleanups in this series make sense even without PAE. -Kevin Kevin O'Connor (10): e820: Introduce e820_remove() and avoid exporting E820_HOLE e820: Rename memmap.c to e820map.c and use consistent "e820_" prefix e820: Update debugging messages to report 64bit values virtio: Simplify vring alignment code virtio: Move standard definitions from virtio-ring.h to standard headers malloc: Use consistent naming for internal low-level "alloc" functions malloc: Introduce common helper alloc_new_detail() malloc: Add warning if free() called on invalid memory malloc: Don't mix virtual and physical addresses memmap: Introduce SYMBOL() macro to access linker script symbols Makefile | 2 +- src/biosvar.h | 6 +- src/{memmap.c => e820map.c} | 18 ++- src/{memmap.h => e820map.h} | 9 +- src/fw/biostables.c | 10 +- src/fw/coreboot.c | 8 +- src/fw/csm.c | 18 +-- src/fw/paravirt.c | 14 +-- src/fw/pciinit.c | 6 +- src/fw/shadow.c | 10 +- src/fw/xen.c | 9 +- src/hw/pvscsi.c | 2 +- src/hw/ramdisk.c | 5 +- src/hw/virtio-ring.h | 36 ++---- src/list.h | 10 ++ src/malloc.c | 294 +++++++++++++++++++++++--------------------- src/malloc.h | 11 +- src/memmap.h | 38 +++--- src/pmm.c | 16 +-- src/post.c | 41 +++--- src/system.c | 2 +- src/x86.h | 8 ++ 22 files changed, 293 insertions(+), 280 deletions(-) rename src/{memmap.c => e820map.c} (90%) copy src/{memmap.h => e820map.h} (66%) -- 2.4.3

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Next release
by Kevin O'Connor 12 Oct '15

12 Oct '15

I think it would be good to schedule the next SeaBIOS release (v1.9.0). I think the first week of November (Nov 6th) would be a good target date for a release. There are a couple of pending features that I would like to see go into the next release: - the fw_cfg dma interface. (Hopefully the fw_cfg dma interface will be accepted into QEMU in the next week or two so that it could make the next SeaBIOS release.) - remove the "make VERSION=xyz" version override, and replace it with a standard version string that is more "reproducible" than the current identifier. (I hope to send some patches that implement a revised seabios version identifier later this week.) Are there any other features or bug fixes that should be addressed prior to the next release? -Kevin

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Re: [SeaBIOS] [RFC PATCH] x86: Support booting SeaBIOS
by Bin Meng 10 Oct '15

10 Oct '15

Hi Simon, On Sat, Oct 3, 2015 at 10:29 PM, Simon Glass <sjg(a)chromium.org> wrote: > Hi Bin, > > On 29 September 2015 at 11:17, Bin Meng <bmeng.cn(a)gmail.com> wrote: >> SeaBIOS is an open source implementation of a 16-bit X86 BIOS. >> It can run in an emulator or natively on X86 hardware with the >> use of coreboot. With SeaBIOS's help, we can boot some OSes >> that require 16-bit BIOS services like Windows/DOS. >> >> As U-Boot, we have to manually create a table where SeaBIOS gets >> system information (eg: E820) from. The table unfortunately has >> to follow the coreboot table format as SeaBIOS currently supports >> booting as a coreboot payload. No U-Boot native support there. >> >> Booting SeaBIOS is done via U-Boot's bootelf command. >> >> This is the initial attempt to support booting SeaBIOS from U-Boot. >> If the basic concept is good, I can spend time working on follow-on >> patches to enable BIOS tables as well as graphics support. One issue >> is that U-Boot x86 does not has a ROM file system like coreboot. >> This brings difficulities to pass PCI option ROM to SeaBIOS, if we >> don't modify SeaBIOS's source codes. Maybe we should promote CBFS >> in U-Boot x86? >> >> This is tested on an Intel Crown Bay board with VGA card, booting >> SeaBIOS then chain loading a GRUB on a USB drive, then Linux kernel >> finally. > > Looks good to me. I think it is OK to use CBFS if needed - are you > thinking of an option to build u-boot.rom as a CBFS filesystem? If using CBFS, that means we may have to abandon ifdtool? Or maybe mixed usage of both tools? > >> >> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> >> >> --- >> >> arch/x86/Kconfig | 10 ++++++++++ >> arch/x86/include/asm/tables.h | 29 +++++++++++++++++++++++++++++ >> arch/x86/lib/tables.c | 39 +++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 78 insertions(+) >> >> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig >> index 5e42d7d..b432ff8 100644 >> --- a/arch/x86/Kconfig >> +++ b/arch/x86/Kconfig >> @@ -401,6 +401,16 @@ config PCIE_ECAM_SIZE >> so a default 0x10000000 size covers all of the 256 buses which is the >> maximum number of PCI buses as defined by the PCI specification. >> >> +config SEABIOS >> + bool "Support booting SeaBIOS" >> + help >> + SeaBIOS is an open source implementation of a 16-bit X86 BIOS. >> + It can run in an emulator or natively on X86 hardware with the use >> + of coreboot/U-Boot. By turning on this option, U-Boot prepares >> + all the configuration tables that are necessary to boot SeaBIOS. >> + >> + Check http://www.seabios.org/SeaBIOS for details. >> + >> source "arch/x86/lib/efi/Kconfig" >> >> endmenu >> diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h >> index 0aa6d9b..a083cac 100644 >> --- a/arch/x86/include/asm/tables.h >> +++ b/arch/x86/include/asm/tables.h >> @@ -7,6 +7,32 @@ >> #ifndef _X86_TABLES_H_ >> #define _X86_TABLES_H_ >> >> +#ifdef CONFIG_SEABIOS >> + >> +#define CB_TAG_MEMORY 1 >> + >> +struct cb_header { >> + u8 signature[4]; >> + u32 header_bytes; >> + u32 header_checksum; >> + u32 table_bytes; >> + u32 table_checksum; >> + u32 table_entries; >> +}; >> + >> +struct cb_memory_range { >> + u64 start; >> + u64 size; >> + u32 type; >> +}; >> + >> +struct cb_memory { >> + u32 tag; >> + u32 size; >> + struct cb_memory_range map[0]; >> +}; >> +#endif >> + >> /* >> * All x86 tables happen to like the address range from 0xf0000 to 0x100000. >> * We use 0xf0000 as the starting address to store those tables, including >> @@ -14,6 +40,9 @@ >> */ >> #define ROM_TABLE_ADDR 0xf0000 >> >> +/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */ >> +#define CB_TABLE_ADDR 0x800 >> + >> /** >> * table_compute_checksum() - Compute a table checksum >> * >> diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c >> index f15b2e2..5849b2f 100644 >> --- a/arch/x86/lib/tables.c >> +++ b/arch/x86/lib/tables.c >> @@ -9,6 +9,7 @@ >> #include <asm/mpspec.h> >> #include <asm/tables.h> >> #include <asm/acpi_table.h> >> +#include <asm/e820.h> >> >> u8 table_compute_checksum(void *v, int len) >> { >> @@ -36,6 +37,41 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad) >> dest[i] = pad; >> } >> >> +#ifdef CONFIG_SEABIOS >> +static u32 write_cb_tables(u32 addr) >> +{ >> + struct cb_header *cbh = (struct cb_header *)addr; >> + struct cb_memory *mem; >> + struct cb_memory_range *map; >> + struct e820entry entry[32]; >> + int num, i; >> + >> + memset(cbh, 0, sizeof(struct cb_header)); >> + strncpy((char *)cbh->signature, "LBIO", 4); > > memcpy()? Yes. > >> + cbh->header_bytes = sizeof(struct cb_header); >> + >> + /* populate memory map table */ >> + mem = (struct cb_memory *)(cbh + 1); >> + mem->tag = CB_TAG_MEMORY; >> + map = mem->map; >> + num = install_e820_map(32, entry); > > ARRAY_SIZE(entry) Yes > >> + for (i = 0; i < num; i++) { >> + map->start = entry[i].addr; >> + map->size = entry[i].size; >> + map->type = entry[i].type; >> + map++; >> + } >> + mem->size = num * sizeof(struct cb_memory_range) + 8; > > What is 8? It's sizeof(struct cb_memory) - sizeof(struct cb_memory_range) > >> + >> + cbh->table_bytes = mem->size; >> + cbh->table_checksum = compute_ip_checksum(mem, cbh->table_bytes); >> + cbh->table_entries = 1; >> + cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes); >> + >> + return (u32)map; >> +} >> +#endif >> + >> void write_tables(void) >> { >> u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR; >> @@ -56,4 +92,7 @@ void write_tables(void) >> rom_table_end = write_acpi_tables(rom_table_end); >> rom_table_end = ALIGN(rom_table_end, 1024); >> #endif >> +#ifdef CONFIG_SEABIOS >> + write_cb_tables(CB_TABLE_ADDR); >> +#endif >> } >> -- Regards, Bin

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[PATCH 1/2] Fix typos found by codespell
by Stefan Weil 09 Oct '15

09 Oct '15

Signed-off-by: Stefan Weil <sw(a)weilnetz.de> --- scripts/kconfig/lxdialog/util.c | 2 +- src/Kconfig | 2 +- src/biosvar.h | 2 +- src/bmp.c | 2 +- src/fw/shadow.c | 2 +- src/hw/pci_regs.h | 2 +- src/misc.c | 2 +- src/sha1.c | 4 ++-- src/std/LegacyBios.h | 4 ++-- src/std/bda.h | 2 +- src/string.c | 2 +- src/types.h | 2 +- src/vgahooks.c | 2 +- vgasrc/geodevga.h | 2 +- 14 files changed, 16 insertions(+), 16 deletions(-) diff --git a/scripts/kconfig/lxdialog/util.c b/scripts/kconfig/lxdialog/util.c index f7abdeb..2a0d182 100644 --- a/scripts/kconfig/lxdialog/util.c +++ b/scripts/kconfig/lxdialog/util.c @@ -376,7 +376,7 @@ void print_title(WINDOW *dialog, const char *title, int width) /* * Print a string of text in a window, automatically wrap around to the * next line if the string is too long to fit on one line. Newline - * characters '\n' are propperly processed. We start on a new line + * characters '\n' are properly processed. We start on a new line * if there is no room for at least 4 nonblanks following a double-space. */ void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x) diff --git a/src/Kconfig b/src/Kconfig index b873cd3..95bf087 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -20,7 +20,7 @@ choice Configure for an emulated machine (QEMU, Xen, KVM, or Bochs). config CSM - bool "Build as Compatibilty Support Module for EFI BIOS" + bool "Build as Compatibility Support Module for EFI BIOS" help Configure to be used by EFI firmware as Compatibility Support module (CSM) to provide legacy BIOS services. diff --git a/src/biosvar.h b/src/biosvar.h index 58bcbce..3b40957 100644 --- a/src/biosvar.h +++ b/src/biosvar.h @@ -12,7 +12,7 @@ /**************************************************************** - * Interupt vector table + * Interrupt vector table ****************************************************************/ #define GET_IVT(vector) \ diff --git a/src/bmp.c b/src/bmp.c index d8e76b7..96a2b3f 100644 --- a/src/bmp.c +++ b/src/bmp.c @@ -1,6 +1,6 @@ /* * Basic BMP data process and Raw picture data handle functions. -* Could be used to adjust pixel data format, get infomation, etc. +* Could be used to adjust pixel data format, get information, etc. * * Copyright (C) 2011 Wayne Xia <xiawenc(a)cn.ibm.com> * diff --git a/src/fw/shadow.c b/src/fw/shadow.c index 4f00006..936ae28 100644 --- a/src/fw/shadow.c +++ b/src/fw/shadow.c @@ -65,7 +65,7 @@ make_bios_writable_intel(u16 bdf, u32 pam0) if (!(reg & 0x10)) { // QEMU doesn't fully implement the piix shadow capabilities - // if ram isn't backing the bios segment when shadowing is - // disabled, the code itself wont be in memory. So, run the + // disabled, the code itself won't be in memory. So, run the // code from the high-memory flash location. u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET; void (*func)(u16 bdf, u32 pam0) = (void*)pos; diff --git a/src/hw/pci_regs.h b/src/hw/pci_regs.h index e5effd4..f7a455d 100644 --- a/src/hw/pci_regs.h +++ b/src/hw/pci_regs.h @@ -221,7 +221,7 @@ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ -#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ +#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ diff --git a/src/misc.c b/src/misc.c index 8caaf31..f02237c 100644 --- a/src/misc.c +++ b/src/misc.c @@ -56,7 +56,7 @@ void VISIBLE16 handle_10(struct bregs *regs) { debug_enter(regs, DEBUG_HDL_10); - // dont do anything, since the VGA BIOS handles int10h requests + // don't do anything, since the VGA BIOS handles int10h requests } // NMI handler diff --git a/src/sha1.c b/src/sha1.c index 352114f..2ecb3cb 100644 --- a/src/sha1.c +++ b/src/sha1.c @@ -33,7 +33,7 @@ sha1_block(u32 *w, sha1_ctx *ctx) static const u32 sha_ko[4] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; - /* change endianess of given data */ + /* change endianness of given data */ for (i = 0; i < 16; i++) w[i] = be32_to_cpu(w[i]); @@ -120,7 +120,7 @@ sha1_do(sha1_ctx *ctx, const u8 *data32, u32 length) sha1_block(w, ctx); - /* need to switch result's endianess */ + /* need to switch result's endianness */ for (num = 0; num < 5; num++) ctx->h[num] = cpu_to_be32(ctx->h[num]); } diff --git a/src/std/LegacyBios.h b/src/std/LegacyBios.h index 5170c37..e0c40d6 100644 --- a/src/std/LegacyBios.h +++ b/src/std/LegacyBios.h @@ -219,7 +219,7 @@ typedef struct { /// value of the start of the PCI Express memory-mapped configuration registers and /// must be filled in prior to EfiCompatibility code issuing the Compatibility16 function /// Compatibility16InitializeYourself(). - /// Compatibility16InitializeYourself() is defined in Compatability16 + /// Compatibility16InitializeYourself() is defined in Compatibility16 /// Functions. /// UINT32 PciExpressBase; @@ -252,7 +252,7 @@ typedef struct { /// /// Functions provided by the CSM binary which communicate between the EfiCompatibility -/// and Compatability16 code. +/// and Compatibility16 code. /// /// Inconsistent with the specification here: /// The member's name started with "Compatibility16" [defined in Intel Framework diff --git a/src/std/bda.h b/src/std/bda.h index c321266..4ad6605 100644 --- a/src/std/bda.h +++ b/src/std/bda.h @@ -7,7 +7,7 @@ /**************************************************************** - * Interupt vector table + * Interrupt vector table ****************************************************************/ struct rmode_IVT { diff --git a/src/string.c b/src/string.c index 2e4e437..adb8198 100644 --- a/src/string.c +++ b/src/string.c @@ -227,7 +227,7 @@ strtcpy(char *dest, const char *src, size_t len) return dest; } -// locate first occurance of character c in the string s +// locate first occurrence of character c in the string s char * strchr(const char *s, int c) { diff --git a/src/types.h b/src/types.h index 097372c..19d9f6c 100644 --- a/src/types.h +++ b/src/types.h @@ -70,7 +70,7 @@ extern void __force_link_error__only_in_16bit(void) __noreturn; # define VARFSEG __section(".discard.varfseg." UNIQSEC) __VISIBLE __weak // Designate a variable at a specific address in the f-segment. # define VARFSEGFIXED(addr) __section(".discard.varfixed." UNIQSEC) __VISIBLE __weak -// Verify a variable is only accessable via 32bit "init" functions +// Verify a variable is only accessible via 32bit "init" functions # define VARVERIFY32INIT __section(".discard.varinit." UNIQSEC) // Designate top-level assembler as 16bit only. # define ASM16(code) __ASM(code) diff --git a/src/vgahooks.c b/src/vgahooks.c index 6a4acfe..48efb08 100644 --- a/src/vgahooks.c +++ b/src/vgahooks.c @@ -124,7 +124,7 @@ getAMDRamSpeed(void) /* int 0x15 - 5f18 - ECX = unknown/dont care + ECX = unknown/don't care EBX[3..0] Frame Buffer Size 2^N MiB EBX[7..4] Memory speed: 0: SDR 66Mhz diff --git a/vgasrc/geodevga.h b/vgasrc/geodevga.h index 61d7808..c99f54b 100644 --- a/vgasrc/geodevga.h +++ b/vgasrc/geodevga.h @@ -2,7 +2,7 @@ // // Copyright (C) 2009 Chris Kindt // -// Writen for Google Summer of Code 2009 for the coreboot project +// Written for Google Summer of Code 2009 for the coreboot project // // This file may be distributed under the terms of the GNU LGPLv3 license. -- 2.1.4

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[PATCH 1/2] Consolidate code16*() functions
by Kevin O'Connor 09 Oct '15

09 Oct '15

Introduce code16_override() for cases where call16() should not restore the previous 16bit state. All callers now use call16_back() to invoke 16bit code, so rename call16_back() to call16(). Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/stacks.c | 61 +++++++++++++++++++++++++++--------------------------------- 1 file changed, 27 insertions(+), 34 deletions(-) diff --git a/src/stacks.c b/src/stacks.c index 850a335..a156138 100644 --- a/src/stacks.c +++ b/src/stacks.c @@ -92,7 +92,23 @@ call32_post(void) return method; } -// 16bit handler code called from call16_back() / call16_smm() +// Force next call16() to restore to a pristine cpu environment state +static void +call16_override(int big) +{ + ASSERT32FLAT(); + if (getesp() > BUILD_STACK_ADDR) + panic("call16_override with invalid stack\n"); + memset(&Call16Data, 0, sizeof(Call16Data)); + if (big) { + Call16Data.method = C16_BIG; + Call16Data.a20 = 1; + } else { + Call16Data.a20 = !CONFIG_DISABLE_A20; + } +} + +// 16bit handler code called from call16() / call16_smm() u32 VISIBLE16 call16_helper(u32 eax, u32 edx, u32 (*func)(u32 eax, u32 edx)) { @@ -243,11 +259,11 @@ call32(void *func, u32 eax, u32 errret) // Call a 16bit SeaBIOS function, restoring the mode from last call32(). static u32 -call16_back(u32 eax, u32 edx, void *func) +call16(u32 eax, u32 edx, void *func) { ASSERT32FLAT(); if (getesp() > MAIN_STACK_MAX) - panic("call16_back with invalid stack\n"); + panic("call16 with invalid stack\n"); if (CONFIG_CALL32_SMM && Call16Data.method == C16_SMM) return call16_smm(eax, edx, func); @@ -283,31 +299,6 @@ call16_back(u32 eax, u32 edx, void *func) return eax; } -// Call a 16bit SeaBIOS function in regular ("non-big") mode. -static u32 -call16(u32 eax, u32 edx, void *func) -{ - ASSERT32FLAT(); - if (getesp() > BUILD_STACK_ADDR) - panic("call16 with invalid stack\n"); - memset(&Call16Data, 0, sizeof(Call16Data)); - Call16Data.a20 = !CONFIG_DISABLE_A20; - return call16_back(eax, edx, func); -} - -// Call a 16bit SeaBIOS function in "big real" mode. -static u32 -call16big(u32 eax, u32 edx, void *func) -{ - ASSERT32FLAT(); - if (getesp() > BUILD_STACK_ADDR) - panic("call16big with invalid stack\n"); - memset(&Call16Data, 0, sizeof(Call16Data)); - Call16Data.method = C16_BIG; - Call16Data.a20 = 1; - return call16_back(eax, edx, func); -} - /**************************************************************** * Extra 16bit stack @@ -362,7 +353,7 @@ u32 stack_hop_back(u32 eax, u32 edx, void *func) { if (!MODESEGMENT) - return call16_back(eax, edx, func); + return call16(eax, edx, func); if (!MODE16 || !on_extra_stack()) return ((u32 (*)(u32, u32))func)(eax, edx); ASSERT16(); @@ -414,18 +405,20 @@ _farcall16(struct bregs *callregs, u16 callregseg) : "ebx", "ecx", "esi", "edi", "cc", "memory"); } +// Invoke external 16bit code. void farcall16(struct bregs *callregs) { - extern void _cfunc16__farcall16(void); - call16((u32)callregs, 0, _cfunc16__farcall16); + call16_override(0); + _farcall16(callregs, 0); } +// Invoke external 16bit code in "big real" mode. void farcall16big(struct bregs *callregs) { - extern void _cfunc16__farcall16(void); - call16big((u32)callregs, 0, _cfunc16__farcall16); + call16_override(1); + _farcall16(callregs, 0); } // Invoke a 16bit software interrupt. @@ -448,7 +441,7 @@ reset(void) { extern void reset_vector(void) __noreturn; if (!MODE16) - call16_back(0, 0, reset_vector); + call16(0, 0, reset_vector); reset_vector(); } -- 2.4.3

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Re: [SeaBIOS] VT-d not enabled on Chromebook Pixel 2013 Link & Chromebook Pixel 2015 Samus
by Kevin O'Connor 09 Oct '15

09 Oct '15

On Fri, Oct 09, 2015 at 04:36:02PM +0100, edward wandasiewicz wrote: > Basically, we are missing a DMAR table in the BIOS [...] > $ acpidump -s > > ACPI: RSDP 0x00000000000F48E0 000024 (v02 CORE ) > ACPI: RSDT 0x000000007CF44030 000038 (v01 CORE COREBOOT 00000000 > CORE 00000000) > ACPI: XSDT 0x000000007CF440E0 00004C (v01 CORE COREBOOT 00000000 > CORE 00000000) > ACPI: DSDT 0x000000007CF44250 004720 (v02 COREv4 COREBOOT 20110725 > INTL 20130117) > ACPI: FACS 0x000000007CF44210 000040 > ACPI: FACP 0x000000007CF48970 0000F4 (v05 CORE COREBOOT 00000000 > CORE 00000001) > ACPI: HPET 0x000000007CF48A70 000038 (v01 CORE COREBOOT 00000000 > CORE 00000000) > ACPI: APIC 0x000000007CF48AB0 00006C (v01 CORE COREBOOT 00000000 > CORE 00000000) > ACPI: MCFG 0x000000007CF48B20 00003C (v01 CORE COREBOOT 00000000 > CORE 00000000) > ACPI: SSDT 0x000000007CF49BC0 000FF8 (v02 CORE COREBOOT 0000002A > CORE 0000002A) > > I get the same output, both before running qemu for the first time, > after a fresh reboot, and whilst running qemu - on the off chance, if > VT-x is enabled whilst running qemu, then maybe the DMAR tables for > VT-d might be available at the same time, but alas, no, it wasn't to > be. > > For VT-d to work, we would need a DMAR table in the BIOS. > > Is this at all possible? SeaBIOS just passes along the ACPI tables generated by coreboot. If you want to change those tables it needs to be done in the coreboot code - see: http://coreboot.org/ -Kevin

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VT-d not enabled on Chromebook Pixel 2013 Link & Chromebook Pixel 2015 Samus
by edward wandasiewicz 09 Oct '15

09 Oct '15

Basically, we are missing a DMAR table in the BIOS How I came to the conclusion? 2013 Chromebook Pixel Link runs on Intel's HM75 chipset 2015 Chromebook Pixel Samus runs on Intel's HM97 chipset Looking up the HM75 chipset specs on http://ark.intel.com/#@Chipsets - links to http://ark.intel.com/products/64348 At a brief glance, Intel are telling us VT-d is not available on this chipset. However, if we click on 'Link', next to Essentials -> Datasheet Jump to page 282, we see the list of Intel® VT-d Features Supported So we know the motherboard chipset of HM75 is VT-d compatible at a native level. HM97 for mobile laptops is not listed on the website at present, but Wildcat Point chipsets of Z97 and H97 for Desktops are listed, and show the same wrong info of VT-d not available, at a quick glance, but further reading of the datasheet PDF indicates the opposite. We know the CPU on Link & Samus is VT-d compatible. To get VT-d to work, we need a compatible CPU, a compatible chipset and a flag in the BIOS. All 3 must be available, else we won't get VT-d. It appears we have all the wiring in place (CPU & chipset), but no switch attached to the wires, to turn it on or off (BIOS) The factory SeaBIOS does not turn off VT-x completely. If we run a qemu 2.4.0-4 on Arch Linux 4.2.2-1, it gets turned on at run time, Before we run qemu $ rdmsr 0x3a 0 Whilst running qemu and after we finish / kill qemu $ rdmsr 0x3a 5 So VT-x works fine. If we turn it on by running qemu, we should have access to VT-d, (theoretically speaking, if Google never turned off VT features in the SeaBIOS to begin with), but to no avail. If I run $ ls -l /sys/firmware/acpi/tables total 0 -r-------- 1 root root 108 Oct 9 14:40 APIC -r-------- 1 root root 18208 Oct 9 14:40 DSDT drwxr-xr-x 2 root root 0 Oct 9 14:40 dynamic -r-------- 1 root root 244 Oct 9 14:40 FACP -r-------- 1 root root 64 Oct 9 14:40 FACS1 -r-------- 1 root root 64 Oct 9 14:40 FACS2 -r-------- 1 root root 56 Oct 9 14:40 HPET -r-------- 1 root root 60 Oct 9 14:40 MCFG -r-------- 1 root root 4088 Oct 9 14:40 SSDT $ acpidump -s ACPI: RSDP 0x00000000000F48E0 000024 (v02 CORE ) ACPI: RSDT 0x000000007CF44030 000038 (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: XSDT 0x000000007CF440E0 00004C (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: DSDT 0x000000007CF44250 004720 (v02 COREv4 COREBOOT 20110725 INTL 20130117) ACPI: FACS 0x000000007CF44210 000040 ACPI: FACP 0x000000007CF48970 0000F4 (v05 CORE COREBOOT 00000000 CORE 00000001) ACPI: HPET 0x000000007CF48A70 000038 (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: APIC 0x000000007CF48AB0 00006C (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: MCFG 0x000000007CF48B20 00003C (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: SSDT 0x000000007CF49BC0 000FF8 (v02 CORE COREBOOT 0000002A CORE 0000002A) I get the same output, both before running qemu for the first time, after a fresh reboot, and whilst running qemu - on the off chance, if VT-x is enabled whilst running qemu, then maybe the DMAR tables for VT-d might be available at the same time, but alas, no, it wasn't to be. For VT-d to work, we would need a DMAR table in the BIOS. Is this at all possible? Edward.

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