SeaBIOS August 2018

seabios@seabios.org

20 participants
41 discussions

[PATCH v2 3/3] pci: recognize RH PCI legacy bridge resource
by Jing Liu 14 Aug '18

14 Aug '18

Enable the firmware recognizing RedHat legacy PCI bridge device ID, so QEMU can reserve additional PCI bridge resource capability. Signed-off-by: Jing Liu <jing2.liu(a)linux.intel.com> --- src/fw/pciinit.c | 50 +++++++++++++++++++++++++++++--------------------- src/hw/pci_ids.h | 1 + 2 files changed, 30 insertions(+), 21 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 62a32f1..795d84a 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -525,30 +525,38 @@ static void pci_bios_init_platform(void) static u8 pci_find_resource_reserve_capability(u16 bdf) { - if (pci_config_readw(bdf, PCI_VENDOR_ID) == PCI_VENDOR_ID_REDHAT && - pci_config_readw(bdf, PCI_DEVICE_ID) == - PCI_DEVICE_ID_REDHAT_ROOT_PORT) { - u8 cap = 0; - do { - cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap); - } while (cap && - pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) != - REDHAT_CAP_RESOURCE_RESERVE); - if (cap) { - u8 cap_len = pci_config_readb(bdf, cap + PCI_CAP_FLAGS); - if (cap_len < RES_RESERVE_CAP_SIZE) { - dprintf(1, "PCI: QEMU resource reserve cap length %d is invalid\n", - cap_len); - return 0; - } - } else { - dprintf(1, "PCI: QEMU resource reserve cap not found\n"); + u16 device_id; + + if (pci_config_readw(bdf, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) { + dprintf(1, "PCI: QEMU resource reserve cap vendor ID doesn't match.\n"); + return 0; + } + + device_id = pci_config_readw(bdf, PCI_DEVICE_ID); + + if (device_id != PCI_DEVICE_ID_REDHAT_ROOT_PORT && + device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) { + dprintf(1, "PCI: QEMU resource reserve cap device ID doesn't match.\n"); + return 0; + } + u8 cap = 0; + + do { + cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap); + } while (cap && + pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) != + REDHAT_CAP_RESOURCE_RESERVE); + if (cap) { + u8 cap_len = pci_config_readb(bdf, cap + PCI_CAP_FLAGS); + if (cap_len < RES_RESERVE_CAP_SIZE) { + dprintf(1, "PCI: QEMU resource reserve cap length %d is invalid\n", + cap_len); + return 0; } - return cap; } else { - dprintf(1, "PCI: QEMU resource reserve cap VID or DID doesn't match.\n"); - return 0; + dprintf(1, "PCI: QEMU resource reserve cap not found\n"); } + return cap; } /**************************************************************** diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 38fa2ca..1096461 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2265,6 +2265,7 @@ #define PCI_VENDOR_ID_REDHAT 0x1b36 #define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C +#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 -- 1.8.3.1

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[SEABIOS] [PATCH 1/1] nvme: fix I/O queue length calculation overflow
by Matt DeVillier 12 Aug '18

12 Aug '18

>From a17975b5fe0cb2b17fdf0335430d5f4d2ab3ba4d Mon Sep 17 00:00:00 2001 From: Matt DeVillier <matt.devillier(a)gmail.com> Date: Sun, 12 Aug 2018 15:26:59 -0500 Subject: [PATCH 1/1] nvme: fix I/O queue length calculation overflow Commit cd47172 changed the I/O queue length calculation to use the Maximum Queue Entries Supported (MQES) value from the capabilities register, plus one, with a maximum value of NVME_PAGE_SIZE. An unintended effect from this is that a MQES value of 0xFFFF yields a length of zero, resulting in the queue allocation failing. Fix this by checking for a zero length when checking that the length exceeds NVME_PAGE_SIZE, and setting to NVME_PAGE_SIZE. TEST: build/boot on a Purism Librem13v2 with a MyDigitalSSD BPX NVMe drive, which reports a MQES of 0xFFFF. Verify NVMe drive present in boot menu and OS boots successfully. Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/hw/nvme.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/hw/nvme.c b/src/hw/nvme.c index e6d739d..c2d6863 100644 --- a/src/hw/nvme.c +++ b/src/hw/nvme.c @@ -319,7 +319,7 @@ nvme_create_io_cq(struct nvme_ctrl *ctrl, struct nvme_cq *cq, u16 q_idx) int rc; struct nvme_sqe *cmd_create_cq; u16 length = 1 + (ctrl->reg->cap & 0xffff); - if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) + if (length == 0 || length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); rc = nvme_init_cq(ctrl, cq, q_idx, length); @@ -363,7 +363,7 @@ nvme_create_io_sq(struct nvme_ctrl *ctrl, struct nvme_sq *sq, u16 q_idx, struct int rc; struct nvme_sqe *cmd_create_sq; u16 length = 1 + (ctrl->reg->cap & 0xffff); - if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) + if (length == 0 || length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); rc = nvme_init_sq(ctrl, sq, q_idx, length, cq); -- 2.17.1

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Re: [SeaBIOS] Marvell 88SE9230 passthrough in KVM takes long time to boot
by Gerd Hoffmann 09 Aug '18

09 Aug '18

On Sun, Jul 29, 2018 at 01:49:10PM +0200, Konrad Eisele wrote: > I'm passing through a Marvell 88SE9230 card to a KVM guest under > Ubuntu 18.04. The card is a Sata controller with 4 ports. > The option rom of the Marvell 88SE9230 card shows on a normal boot a > bios screen. When pressing CTRL-m quick enough, you can interrupt the > bootprocess and enter a menue wherer you can define raid > arrays. > > When booting seabios inside KVM the bootprocess is very slow. > There is a 1 min holdtime where the cpu is about 30%. The screen is > black with only the seabios version string shown. I suspect that > the passed-through Marvell 88SE9230 cards option roms causes this > behaviour. > Maybe the scanning for option rom cause the slow bootprocess? > > In the seabios boot case no bios menue is shown, after > around 1 min the boot continues. > > Is it possible to disable the options rom processing? Is there some > documentation about this (How can I configure it for Ubuntu) ? Set the romfile option to the empty string (for vfio-pci, on the qemu command line) should do that (qemu will not expose the rom to the guest then). cheers, Gerd

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enable log path of devices in seabios
by zahra rahimkhani 09 Aug '18

09 Aug '18

Hello Friends I want to enable a log that show path of devices that by seabios was recognize . this paths are different from boot default paths. Could you suggest me a advice? Thank you, Zahra

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[PATCH] pci: add RedHat PCI BRIDGE capability
by Jing Liu 09 Aug '18

09 Aug '18

Add a device-specific capability for the RedHat PCI BRIDGE to enable reserving additional resources. Signed-off-by: Jing Liu <jing2.liu(a)linux.intel.com> --- src/fw/pciinit.c | 9 ++++++--- src/hw/pci_ids.h | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 3a2f747..0265e9d 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -525,9 +525,12 @@ static void pci_bios_init_platform(void) static u8 pci_find_resource_reserve_capability(u16 bdf) { - if (pci_config_readw(bdf, PCI_VENDOR_ID) == PCI_VENDOR_ID_REDHAT && - pci_config_readw(bdf, PCI_DEVICE_ID) == - PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID); + u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID); + + if (vendor_id == PCI_VENDOR_ID_REDHAT && + (device_id == PCI_DEVICE_ID_REDHAT_ROOT_PORT || + device_id == PCI_DEVICE_ID_REDHAT_BRIDGE)) { u8 cap = 0; do { cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap); diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 38fa2ca..1096461 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2265,6 +2265,7 @@ #define PCI_VENDOR_ID_REDHAT 0x1b36 #define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C +#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 -- 1.8.3.1

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Fwd: [RFC 0/2] (Ongoing)Support multiple pci domains in pci_device
by Zihan Yang 09 Aug '18

09 Aug '18

[forgot to cc to the mail list] Kevin O'Connor <kevin(a)koconnor.net> 于2018年8月8日周三下午10:14写道： > > On Thu, Aug 02, 2018 at 10:39:13AM +0800, Zihan Yang wrote: > > NOTE: This patch set is still ongoing and does not fully function > > as its goal. But it involves some API changes, therefore I post them for > > comments before moving on to make sure I'm on the right path. > > > > The corresponding qemu part can be found at > > https://gitlab.com/WhoisZihan/qemu-pci-domain/tree/master/qemu > > I will submit it to qemu list later. > > > > Currently seabios assumes there is only one pci domain(0), and almost > > everything operates on pci domain 0 by default. This patch aims to add > > multiple pci domain support for pci_device, while reserve the original > > API for compatibility. > > Thanks. I understand the desire to support multiple PCI domains in > QEMU and the guest OS. However, what is the high level reason for > wanting the BIOS to be able to interact with the secondary PCI > domains? The pxb-pcie host bus is put into a separated domain, so are the devices under the pxb host bus. I think we should also initialize busses in other domains and probe those devices during bios initialization. But currently qemu only binds port 0xcf8 and 0xcfc to q35 host's conf_mem and data_mem, if we want to read the config space of pxb host, we should use another port. I use port range 0x1000 and 0x1004 for a temporary workaround because they seem to be 'free' now. Please correct me if I misunderstand it. P.S. Maybe you would want to ignore this patch set as there are a few bugs that I fix later, and I will soon send a v2 patch (v2 is not working either, but I think I find where the current problem is), soon after I fix my network proxy issue... Thanks Zihan

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Re: [SeaBIOS] Problem with boot coreboot
by Mike Banon 08 Aug '18

08 Aug '18

Dear friend, have you tried this advice (given at your coreboot thread) : For the beginning, I recommend you to check if you could boot anything at all. In example, try making an Ubuntu LiveUSB from a spare USB flash drive, and using SeaBIOS try booting from it. If it is working, you could also try installing Ubuntu to a spare Hard Drive and also try booting for it. If all this is working (means the SeaBIOS booting capabilities are fully functional both for USB and SATA interfaces) - while booting FreeBSD still doesn't work - that means something is wrong either with FreeBSD installation or (more likely) its partition table or maybe GRUB2 is corrupted. Then you could try restoring GRUB2, by following these instructions for example - https://howtoubuntu.org/how-to-repair-restore-reinstall-grub-2-with-a-ubunt… If yes, it didn't help you? Best regards, Mike Banon On Wed, Aug 8, 2018 at 6:57 PM, zahra rahimkhani <zrahimkhani2014(a)gmail.com> wrote: > Hello friends > > I compiled coreboot and seabios based on > https://review.coreboot.org/cgit/board-status.git/plain/intel/minnowmax/4.5… > > but my Freebsd or grub2 or Debian or ubuntu did not boot and it shows > this message. > > Running option rom at c000:0003 > Turning on vga text mode console > SeaBIOS (version rel-1.11.2-0-gf9626cc) > EHCI init on dev 00:1d.0 (regs=0xd061e020) > WARNING - Timeout at i8042_flush:71! > AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 > Searching bootorder for: /pci@i0cf8/*@12 > Found 0 lpt ports > Found 1 serial ports > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 > USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 > removable=1 > USB MSC blksize=512 sectors=15730688 > Initialized USB HUB (1 ports used) > All threads complete. > Scan for option roms > > Press ESC for boot menu. > > Searching bootorder for: HALT > drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 s=15730688 > Space available for UMB: cd800-ed800, f5b60-f62c0 > Returned 253952 bytes of ZoneHigh > e820 map has 18 items: > 0: 0000000000000000 - 000000000009fc00 = 1 RAM > 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED > 3: 0000000000100000 - 0000000020000000 = 1 RAM > 4: 0000000020000000 - 0000000020100000 = 2 RESERVED > 5: 0000000020100000 - 000000007ad9c000 = 1 RAM > 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED > 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED > 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED > 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED > 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED > 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED > 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED > 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED > 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED > 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED > 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED > 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED > enter handle_19: > NULL > Booting from Hard Disk... > Booting from 0000:7c00 > > I would be grateful if you guide me . > > Thanks, > Zahra > > > > _______________________________________________ > SeaBIOS mailing list > SeaBIOS(a)seabios.org > https://mail.coreboot.org/mailman/listinfo/seabios

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Problem with boot coreboot
by zahra rahimkhani 08 Aug '18

08 Aug '18

Hello friends I compiled coreboot and seabios based on https://review.coreboot.org/cgit/board-status.git/plain/intel/minnowmax/4.5… but my Freebsd or grub2 or Debian or ubuntu did not boot and it shows this message. Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version rel-1.11.2-0-gf9626cc) EHCI init on dev 00:1d.0 (regs=0xd061e020) WARNING - Timeout at i8042_flush:71! AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 Searching bootorder for: /pci@i0cf8/*@12 Found 0 lpt ports Found 1 serial ports Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 removable=1 USB MSC blksize=512 sectors=15730688 Initialized USB HUB (1 ports used) All threads complete. Scan for option roms Press ESC for boot menu. Searching bootorder for: HALT drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 s=15730688 Space available for UMB: cd800-ed800, f5b60-f62c0 Returned 253952 bytes of ZoneHigh e820 map has 18 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000020000000 = 1 RAM 4: 0000000020000000 - 0000000020100000 = 2 RESERVED 5: 0000000020100000 - 000000007ad9c000 = 1 RAM 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00 I would be grateful if you guide me . Thanks, Zahra

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[RFC 0/2] (Ongoing)Support multiple pci domains in pci_device
by Zihan Yang 08 Aug '18

08 Aug '18

NOTE: This patch set is still ongoing and does not fully function as its goal. But it involves some API changes, therefore I post them for comments before moving on to make sure I'm on the right path. The corresponding qemu part can be found at https://gitlab.com/WhoisZihan/qemu-pci-domain/tree/master/qemu I will submit it to qemu list later. Currently seabios assumes there is only one pci domain(0), and almost everything operates on pci domain 0 by default. This patch aims to add multiple pci domain support for pci_device, while reserve the original API for compatibility. Some part of it is dirty and hardcoded, as I plan to make it support 2 pci domains first as a working POC. Many works remain to do when BIOS checks and initializes PCI devices, because almost everywhere assumes 1 pci domain by default. It compiles and runs, but the guest will issue a "Bus 0001:00 not in PCI Namespace" warning, and it does not correctly recognize the bus under host bridges other than q35. If you have any clue about this error, please point me out, I will appreciate it. Zihan Yang (2): fw/pciinit: Recognize pxb-pcie-dev device pci_device: Add pci domain support src/fw/coreboot.c | 2 +- src/fw/csm.c | 2 +- src/fw/paravirt.c | 3 +- src/fw/pciinit.c | 208 ++++++++++++++++++++++++++++++++++------------------- src/hw/pci.c | 69 +++++++++--------- src/hw/pci.h | 42 +++++++---- src/hw/pci_ids.h | 6 +- src/hw/pcidevice.c | 8 ++- src/hw/pcidevice.h | 10 ++- 9 files changed, 223 insertions(+), 127 deletions(-) -- 2.7.4

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Download URLs changed
by Paolo Bonzini 02 Aug '18

02 Aug '18

Hi, it looks like at some point the download URLs for SeaBIOS changed from https://code.coreboot.org/p/seabios/downloads/get/seabios-X.Y.Z.tar.gz to https://code.coreboot.org/p/seabios/downloads/seabios-X.Y.Z.tar.gz. Would it be possible to add a redirect or symlink from the old files, so as not to break places (such as distribution packages) that have the old URL in it? Thanks, Paolo

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SeaBIOS August 2018