August 2018 - SeaBIOS - mail.coreboot.org

Re: [SeaBIOS] [SEABIOS] [PATCH 1/1] nvme: fix I/O queue length calculation overflow
by Matt DeVillier Aug. 21, 2018

Aug. 21, 2018

>From 2741d96d07855c3bc904d6ce47c82391039bca87 Mon Sep 17 00:00:00 2001 From: Matt DeVillier <matt.devillier(a)puri.sm> Date: Tues, 21 Aug 2018 10:00:53 -0500 Subject: [PATCH v2 1/1] nvme: fix I/O queue length calculation overflow Commit cd47172 changed the I/O queue length calculation to use the Maximum Queue Entries Supported (MQES) value from the capabilities register, plus one, with a maximum value of NVME_PAGE_SIZE. An unintended effect from this is that due to length being an unsigned 16-bit int, a MQES value of 0xFFFF yields a length of zero, resulting in the queue allocation failing. Fix this by changing length to a u32. TEST: build/boot on a Purism Librem13v2 with a MyDigitalSSD BPX NVMe drive, which reports a MQES of 0xFFFF. Verify NVMe drive present in boot menu and OS boots successfully. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- src/hw/nvme.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/hw/nvme.c b/src/hw/nvme.c index e6d739d..2e3aa38 100644 --- a/src/hw/nvme.c +++ b/src/hw/nvme.c @@ -318,7 +318,7 @@ nvme_create_io_cq(struct nvme_ctrl *ctrl, struct nvme_cq *cq, u16 q_idx) { int rc; struct nvme_sqe *cmd_create_cq; - u16 length = 1 + (ctrl->reg->cap & 0xffff); + u32 length = 1 + (ctrl->reg->cap & 0xffff); if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); @@ -362,7 +362,7 @@ nvme_create_io_sq(struct nvme_ctrl *ctrl, struct nvme_sq *sq, u16 q_idx, struct { int rc; struct nvme_sqe *cmd_create_sq; - u16 length = 1 + (ctrl->reg->cap & 0xffff); + u32 length = 1 + (ctrl->reg->cap & 0xffff); if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); -- 2.17.1 On Tue, Aug 21, 2018 at 6:52 AM Matt DeVillier <matt.devillier(a)gmail.com> wrote: > On Mon, Aug 20, 2018 at 11:16 PM Kevin O'Connor <kevin(a)koconnor.net> > wrote: > >> On Sun, Aug 12, 2018 at 03:42:40PM -0500, Matt DeVillier wrote: >> > Commit cd47172 changed the I/O queue length calculation to use the >> > Maximum Queue Entries Supported (MQES) value from the capabilities >> > register, plus one, with a maximum value of NVME_PAGE_SIZE. >> > >> > An unintended effect from this is that a MQES value of 0xFFFF yields >> > a length of zero, resulting in the queue allocation failing. Fix this >> > by checking for a zero length when checking that the length exceeds >> > NVME_PAGE_SIZE, and setting to NVME_PAGE_SIZE. >> > >> > TEST: build/boot on a Purism Librem13v2 with a MyDigitalSSD BPX NVMe >> > drive, which reports a MQES of 0xFFFF. Verify NVMe drive present in >> > boot menu and OS boots successfully. >> > >> > Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> >> > --- >> > src/hw/nvme.c | 4 ++-- >> > 1 file changed, 2 insertions(+), 2 deletions(-) >> > >> > diff --git a/src/hw/nvme.c b/src/hw/nvme.c >> > index e6d739d..c2d6863 100644 >> > --- a/src/hw/nvme.c >> > +++ b/src/hw/nvme.c >> > @@ -319,7 +319,7 @@ nvme_create_io_cq(struct nvme_ctrl *ctrl, struct >> > nvme_cq *cq, u16 q_idx) >> > int rc; >> > struct nvme_sqe *cmd_create_cq; >> > u16 length = 1 + (ctrl->reg->cap & 0xffff); >> > - if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) >> > + if (length == 0 || length > NVME_PAGE_SIZE / sizeof(struct >> nvme_cqe)) >> > length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); >> >> Thanks. Instead of changing the if statement, could we just change >> length here to a u32 to avoid this issue? >> > > I can't think of why not, I'll test this method and submit an updated > patchset if so - thanks! > > >> >> > >> > rc = nvme_init_cq(ctrl, cq, q_idx, length); >> > @@ -363,7 +363,7 @@ nvme_create_io_sq(struct nvme_ctrl *ctrl, struct >> > nvme_sq *sq, u16 q_idx, struct >> > int rc; >> > struct nvme_sqe *cmd_create_sq; >> > u16 length = 1 + (ctrl->reg->cap & 0xffff); >> > - if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) >> > + if (length == 0 || length > NVME_PAGE_SIZE / sizeof(struct >> nvme_cqe)) >> > length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); >> > >> > rc = nvme_init_sq(ctrl, sq, q_idx, length, cq); >> > -- >> > 2.17.1 >> >> -Kevin >> >

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Certificate expired for https://git.seabios.org
by Wei Liu Aug. 21, 2018

Aug. 21, 2018

Hello In case nobody noticed: the certificate for git.seabios.org has expired during the weekend. Maybe certbot is on vacation? :-) Regards, Wei.

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Re: [SeaBIOS] [SEABIOS] [PATCH 1/1] nvme: fix I/O queue length calculation overflow
by Kevin O'Connor Aug. 21, 2018

Aug. 21, 2018

On Sun, Aug 12, 2018 at 03:42:40PM -0500, Matt DeVillier wrote: > Commit cd47172 changed the I/O queue length calculation to use the > Maximum Queue Entries Supported (MQES) value from the capabilities > register, plus one, with a maximum value of NVME_PAGE_SIZE. > > An unintended effect from this is that a MQES value of 0xFFFF yields > a length of zero, resulting in the queue allocation failing. Fix this > by checking for a zero length when checking that the length exceeds > NVME_PAGE_SIZE, and setting to NVME_PAGE_SIZE. > > TEST: build/boot on a Purism Librem13v2 with a MyDigitalSSD BPX NVMe > drive, which reports a MQES of 0xFFFF. Verify NVMe drive present in > boot menu and OS boots successfully. > > Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> > --- > src/hw/nvme.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/src/hw/nvme.c b/src/hw/nvme.c > index e6d739d..c2d6863 100644 > --- a/src/hw/nvme.c > +++ b/src/hw/nvme.c > @@ -319,7 +319,7 @@ nvme_create_io_cq(struct nvme_ctrl *ctrl, struct > nvme_cq *cq, u16 q_idx) > int rc; > struct nvme_sqe *cmd_create_cq; > u16 length = 1 + (ctrl->reg->cap & 0xffff); > - if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) > + if (length == 0 || length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) > length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); Thanks. Instead of changing the if statement, could we just change length here to a u32 to avoid this issue? > > rc = nvme_init_cq(ctrl, cq, q_idx, length); > @@ -363,7 +363,7 @@ nvme_create_io_sq(struct nvme_ctrl *ctrl, struct > nvme_sq *sq, u16 q_idx, struct > int rc; > struct nvme_sqe *cmd_create_sq; > u16 length = 1 + (ctrl->reg->cap & 0xffff); > - if (length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) > + if (length == 0 || length > NVME_PAGE_SIZE / sizeof(struct nvme_cqe)) > length = NVME_PAGE_SIZE / sizeof(struct nvme_cqe); > > rc = nvme_init_sq(ctrl, sq, q_idx, length, cq); > -- > 2.17.1 -Kevin

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Fwd: Fwd: [RFC 0/2] (Ongoing)Support multiple pci domains in pci_device
by Zihan Yang Aug. 21, 2018

Aug. 21, 2018

---------- Forwarded message --------- From: Zihan Yang <whois.zihan.yang(a)gmail.com> Date: 2018年8月21日周二上午10:34 Subject: Re: [SeaBIOS] Fwd: [RFC 0/2] (Ongoing)Support multiple pci domains in pci_device To: Kevin OConnor <kevin(a)koconnor.net> Kevin O'Connor <kevin(a)koconnor.net> 于2018年8月21日周二上午4:24写道： > > On Thu, Aug 09, 2018 at 07:44:22AM +0800, Zihan Yang wrote: > > Kevin O'Connor <kevin(a)koconnor.net> 于2018年8月8日周三下午10:14写道： > > > On Thu, Aug 02, 2018 at 10:39:13AM +0800, Zihan Yang wrote: > > > > NOTE: This patch set is still ongoing and does not fully function > > > > as its goal. But it involves some API changes, therefore I post them for > > > > comments before moving on to make sure I'm on the right path. > > > > > > > > The corresponding qemu part can be found at > > > > https://gitlab.com/WhoisZihan/qemu-pci-domain/tree/master/qemu > > > > I will submit it to qemu list later. > > > > > > > > Currently seabios assumes there is only one pci domain(0), and almost > > > > everything operates on pci domain 0 by default. This patch aims to add > > > > multiple pci domain support for pci_device, while reserve the original > > > > API for compatibility. > > > > > > Thanks. I understand the desire to support multiple PCI domains in > > > QEMU and the guest OS. However, what is the high level reason for > > > wanting the BIOS to be able to interact with the secondary PCI > > > domains? > > > > The pxb-pcie host bus is put into a separated domain, so are the devices > > under the pxb host bus. I think we should also initialize busses in other > > domains and probe those devices during bios initialization. But currently > > qemu only binds port 0xcf8 and 0xcfc to q35 host's conf_mem and data_mem, > > if we want to read the config space of pxb host, we should use another port. > > I use port range 0x1000 and 0x1004 for a temporary workaround because they > > seem to be 'free' now. > > The patchset is quite large and touches a large amount of code in > different parts of SeaBIOS. I'd like to understand the high-level, > user-visible, reason for making the change. What important > capabilities will a user be unable to accomplish if we don't make this > change? The restriction is that pcie topology limits one pcie device per bus, and there are at most 256 buses in a pci domain/segment. Currently the pxb host are still inside the same domain with q35, and the buses will run out if there are many pcie devices. This patch set aims to let users be able to put these 'extra' devices into separate pci domains to overcome the limitation of bus numbers in a single domain. > As far as I know, there is no standard for accessing PCI besides the > main one at cf8/cfc - so I'm not sure there is a good solution to this > problem. Perhaps it would be easier for users to always put their > boot devices on the main PCI. Yes, seabios reads pci config space only through 0xcf8/0xcfc, it seems currently seabios does not seperate pcie devices from pci devices. This patch is just an temporary workaround, maybe we can replace it with mmio later but I think that would involve many changes to seabios too. > Thanks, > -Kevin

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Re: [SeaBIOS] Fwd: [RFC 0/2] (Ongoing)Support multiple pci domains in pci_device
by Kevin O'Connor Aug. 21, 2018

Aug. 21, 2018

On Thu, Aug 09, 2018 at 07:44:22AM +0800, Zihan Yang wrote: > Kevin O'Connor <kevin(a)koconnor.net> 于2018年8月8日周三下午10:14写道： > > On Thu, Aug 02, 2018 at 10:39:13AM +0800, Zihan Yang wrote: > > > NOTE: This patch set is still ongoing and does not fully function > > > as its goal. But it involves some API changes, therefore I post them for > > > comments before moving on to make sure I'm on the right path. > > > > > > The corresponding qemu part can be found at > > > https://gitlab.com/WhoisZihan/qemu-pci-domain/tree/master/qemu > > > I will submit it to qemu list later. > > > > > > Currently seabios assumes there is only one pci domain(0), and almost > > > everything operates on pci domain 0 by default. This patch aims to add > > > multiple pci domain support for pci_device, while reserve the original > > > API for compatibility. > > > > Thanks. I understand the desire to support multiple PCI domains in > > QEMU and the guest OS. However, what is the high level reason for > > wanting the BIOS to be able to interact with the secondary PCI > > domains? > > The pxb-pcie host bus is put into a separated domain, so are the devices > under the pxb host bus. I think we should also initialize busses in other > domains and probe those devices during bios initialization. But currently > qemu only binds port 0xcf8 and 0xcfc to q35 host's conf_mem and data_mem, > if we want to read the config space of pxb host, we should use another port. > I use port range 0x1000 and 0x1004 for a temporary workaround because they > seem to be 'free' now. The patchset is quite large and touches a large amount of code in different parts of SeaBIOS. I'd like to understand the high-level, user-visible, reason for making the change. What important capabilities will a user be unable to accomplish if we don't make this change? As far as I know, there is no standard for accessing PCI besides the main one at cf8/cfc - so I'm not sure there is a good solution to this problem. Perhaps it would be easier for users to always put their boot devices on the main PCI. Thanks, -Kevin

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Re: [SeaBIOS] enable log path of devices in seabios
by Kevin O'Connor Aug. 21, 2018

Aug. 21, 2018

On Thu, Aug 09, 2018 at 12:00:49AM -0300, zahra rahimkhani wrote: > Hello Friends > > I want to enable a log that show path of devices that by seabios was > recognize . > this paths are different from boot default paths. > > Could you suggest me a advice? There's some info on generating a log file at: https://www.seabios.org/Debugging -Kevin

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Re: [SeaBIOS] [Qemu-devel] [PATCH v2 0/3] hw/pci: PCI resource reserve capability
by Laszlo Ersek Aug. 17, 2018

Aug. 17, 2018

Hi, On 08/16/18 11:28, Jing Liu wrote: > This patch serial is about PCI resource reserve capability. > > First patch refactors the resource reserve fields in GenPCIERoorPort > structure out to another new structure, called "PCIResReserve". Modify > the parameter list of pci_bridge_qemu_reserve_cap_init(). > > Then we add the teardown function called pci_bridge_qemu_reserve_cap_uninit(). > > Last we enable the resource reserve capability for legacy PCI bridge > so that firmware can reserve additional resources for the bridge. > > Change Log: > v2 -> v1 > * add refactoring patch > * add teardown function > * some other fixes > > Jing Liu (3): > hw/pci: factor PCI reserve resources to a separate structure > hw/pci: add teardown function for PCI resource reserve capability > hw/pci: add PCI resource reserve capability to legacy PCI bridge > > hw/pci-bridge/gen_pcie_root_port.c | 32 +++++++++++++------------- > hw/pci-bridge/pci_bridge_dev.c | 25 ++++++++++++++++++++ > hw/pci/pci_bridge.c | 47 +++++++++++++++++++++----------------- > include/hw/pci/pci_bridge.h | 18 +++++++++++---- > 4 files changed, 80 insertions(+), 42 deletions(-) > just some meta comments for now: - I've added Marcel; please keep him CC'd on this set (and the SeaBIOS counterpart, [SeaBIOS] [PATCH v2 0/3] pci: resource reserve capability found) - my task queue has blown up and I'm unsure when I'll get to reviewing this set. The same applies to the SeaBIOS counterpart. This is just to say that you should feel free to go ahead and work with the (sub)maintainers; I'll try to get back to this as time allows, but don't wait for me. If further versions are necessary, I'd appreciate being CC'd on those, just so I know what to look at when I find the time again. Thanks! Laszlo

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RS232 mouse in Qemu
by Peter Fodrek ml Aug. 16, 2018

Aug. 16, 2018

Dear Seabios experts, I am asking here, because only aswer to my questions to Qemu experts or Another opensource forums was that this feature is needed be supported by QEMU or SeaBIOS. Our company would like to use QEMU for DOS based program that requires msmouse driver - seems to work only with RS232 mouse- from year of 1998., yet But in Qemu it cannot use this mouse even tried to use several command line options in Windows based machine. Another function sworks well, as well as not so accurate pointing via arrow keys. Is there anybody, who is able to send recommendation fo me, please? If so I would be happy to receive tips in thje reply,please I look forward hearing from you. Yours faithfully Peter Fodrek

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Re: [SeaBIOS] [PATCH v2 3/3] pci: recognize RH PCI legacy bridge resource reservation capability
by Liu, Jing2 Aug. 16, 2018

Aug. 16, 2018

On 8/16/2018 1:06 PM, Zihan Yang wrote: > Liu, Jing2 <jing2.liu(a)linux.intel.com> 于2018年8月16日周四上午10:39写道： >> >> Hi Zihan, >> >> I copy your comments of this patch several days ago here, >> and hope we could continue some discussion in this serial. > > Hi Jing, > > Sorry for the delay. I tested at the code just now and find that pcie > bridge does not > use a vendor specific capability. I met this warning in another > ongoing patch so I just > added pcie bridge to suppress the warning. > > Now that it turns out pcie bridge does not use this vendor specific > capability, I think you > might want to stick with your original patch, and add it in the future > when redhat decides > to add specific capabilities in pcie bridge. Yes, I agree. I'm not quite an expert > in this field, so unfortunately > I don't have much insights to give, but I'm open for a discussion. > Thanks, Jing

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[PATCH v2 0/3] pci: resource reserve capability found
by Jing Liu Aug. 15, 2018

Aug. 15, 2018

This patch serial is about QEMU resource reserve capability finding in firmware. Firstly, this fixes a logic bug. When the capability is truncated, return zero instead of the truncated offset. Secondly, this modified the debug messages when the capability is not found and when the vendor ID or device Id doesn't match REDHAT special ones. Last, this enables the firmware recongizing the REDHAT PCI BRIDGE device ID, so that QEMU can also reserve PCI bridge resource capability. Jing Liu (3): pci: fix the return value for truncated capability pci: clean up the debug message for pci capability found pci: recognize RH PCI legacy bridge resource reservation capability src/fw/pciinit.c | 45 ++++++++++++++++++++++++++++----------------- src/hw/pci_ids.h | 1 + 2 files changed, 29 insertions(+), 17 deletions(-) -- 1.8.3.1

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