SeaBIOS September 2012

seabios@seabios.org

27 participants
112 discussions

[PATCH] add acpi pmtimer support
by Gerd Hoffmann 11 Sep '12

11 Sep '12

This patch makes seabios use the acpi pmtimer instead of tsc for timekeeping. The pmtimer has a fixed frequency and doesn't need calibration, thus it doesn't suffer from calibration errors due to a loaded host machine. [ v4: mask port ioport read ] [ v2: add CONFIG_PMTIMER ] Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/Kconfig | 6 ++++++ src/clock.c | 31 +++++++++++++++++++++++++++++++ src/pciinit.c | 5 +++++ src/util.h | 1 + 4 files changed, 43 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6de3e71..b5dd63b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -222,6 +222,12 @@ menu "Hardware support" default y help Initialize the Memory Type Range Registers (on emulators). + config PMTIMER + depends on !COREBOOT + bool "Use ACPI timer" + default y + help + Use the ACPI timer instead of the TSC for timekeeping (on qemu). endmenu menu "BIOS interfaces" diff --git a/src/clock.c b/src/clock.c index 69e9f17..71b913e 100644 --- a/src/clock.c +++ b/src/clock.c @@ -129,11 +129,42 @@ emulate_tsc(void) return ret; } +u16 pmtimer_ioport VAR16VISIBLE; +u32 pmtimer_wraps VARLOW; +u32 pmtimer_last VARLOW; + +void pmtimer_init(u16 ioport, u32 khz) +{ + if (!CONFIG_PMTIMER) + return; + dprintf(1, "Using pmtimer, ioport 0x%x, freq %d kHz\n", ioport, khz); + SET_GLOBAL(pmtimer_ioport, ioport); + SET_GLOBAL(cpu_khz, khz); +} + +static u64 pmtimer_get(void) +{ + u16 ioport = GET_GLOBAL(pmtimer_ioport); + u32 wraps = GET_LOW(pmtimer_wraps); + u32 pmtimer = inl(ioport) & 0xffffff; + + if (pmtimer < GET_LOW(pmtimer_last)) { + wraps++; + SET_LOW(pmtimer_wraps, wraps); + } + SET_LOW(pmtimer_last, pmtimer); + + dprintf(9, "pmtimer: %u:%u\n", wraps, pmtimer); + return (u64)wraps << 24 | pmtimer; +} + static u64 get_tsc(void) { if (unlikely(GET_GLOBAL(no_tsc))) return emulate_tsc(); + if (CONFIG_PMTIMER && GET_GLOBAL(pmtimer_ioport)) + return pmtimer_get(); return rdtscll(); } diff --git a/src/pciinit.c b/src/pciinit.c index 68f302a..31115ee 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -180,6 +180,9 @@ static const struct pci_device_id pci_class_tbl[] = { PCI_DEVICE_END, }; +/* PM Timer ticks per second (HZ) */ +#define PM_TIMER_FREQUENCY 3579545 + /* PIIX4 Power Management device (for ACPI) */ static void piix4_pm_init(struct pci_device *pci, void *arg) { @@ -191,6 +194,8 @@ static void piix4_pm_init(struct pci_device *pci, void *arg) pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */ pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1); pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */ + + pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000); } static const struct pci_device_id pci_device_tbl[] = { diff --git a/src/util.h b/src/util.h index 062eea3..7723bb1 100644 --- a/src/util.h +++ b/src/util.h @@ -282,6 +282,7 @@ void lpt_setup(void); // clock.c #define PIT_TICK_RATE 1193180 // Underlying HZ of PIT #define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer +void pmtimer_init(u16 ioport, u32 khz); int check_tsc(u64 end); void timer_setup(void); void ndelay(u32 count); -- 1.7.1

3 2

[PATCH 3/6] vgabios: vbe 15h func returns constructed EDID
by Hiroshi Miura 10 Sep '12

10 Sep '12

The Bochs VGA ROM now return an information about a recent WIDE monitor. It is constructed from defitions at run time. Returning an EDID with decent timings may be necessary in case we want to use a resolution superior to 1024x768 with Xorg. Signed-off-by: Hiroshi Miura <miurahr(a)linux.com> --- vgasrc/bochsvga.c | 202 ++++++++++++++++++++++++++++++++--------------------- vgasrc/vbe_edid.h | 134 +++++++++++++++++++++++++++++++++++ 2 files changed, 255 insertions(+), 81 deletions(-) create mode 100644 vgasrc/vbe_edid.h

2 4

Re: [SeaBIOS] Stance on TPM?
by Peter Stuge 10 Sep '12

10 Sep '12

Fred . wrote: > What is SeaBIOS stance on Trusted Platform Module (TPM) ? I guess that there is no stance until you or someone else sends patches that we can discuss. //Peter

3 2

Re: [SeaBIOS] [PATCH 04/15] Report stdvga modes in VBE via int10 (AX = 4F00h)
by Kevin O'Connor 10 Sep '12

10 Sep '12

On Tue, Sep 04, 2012 at 08:45:34AM +0200, Christian Gmeiner wrote: > 2012/9/3 Kevin O'Connor <kevin(a)koconnor.net>: > > All the modes work in the sense that one can switch to them. (I've > > tested that.) However, I think that some modes (eg, cga) wont be > > represented correctly by vbe_104f01. > > > > Can you look at it? Sure - see below. I don't really have a way to test this though. -Kevin >From 91f80cd11898a254c9b38ebb857a86c1a4beb9b0 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor <kevin(a)koconnor.net> Date: Tue, 4 Sep 2012 18:39:51 -0400 Subject: [PATCH] vgabios: Add support text and cga modes to vbe_104f01(). To: seabios(a)seabios.org Attempt to handle cga and text modes in the vbe get_mode_info call. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/vbe.c | 108 +++++++++++++++++++++++++++++++++++------------------------ 1 file changed, 64 insertions(+), 44 deletions(-) diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c index f44231b..d962333 100644 --- a/vgasrc/vbe.c +++ b/vgasrc/vbe.c @@ -82,15 +82,8 @@ vbe_104f01(struct bregs *regs) } memset_far(seg, info, 0, sizeof(*info)); - u16 mode_attr = VBE_MODE_ATTRIBUTE_SUPPORTED | - VBE_MODE_ATTRIBUTE_EXTENDED_INFORMATION_AVAILABLE | - VBE_MODE_ATTRIBUTE_COLOR_MODE | - VBE_MODE_ATTRIBUTE_GRAPHICS_MODE | - VBE_MODE_ATTRIBUTE_NOT_VGA_COMPATIBLE; - u32 framebuffer = GET_GLOBAL(VBE_framebuffer); - if (framebuffer) - mode_attr |= VBE_MODE_ATTRIBUTE_LINEAR_FRAME_BUFFER_MODE; - SET_FARVAR(seg, info->mode_attributes, mode_attr); + + // Basic information about video controller. u32 win_granularity = GET_GLOBAL(VBE_win_granularity); SET_FARVAR(seg, info->winA_attributes, (win_granularity ? VBE_WINDOW_ATTRIBUTE_RELOCATABLE : 0) | @@ -104,6 +97,7 @@ vbe_104f01(struct bregs *regs) extern void entry_104f05(void); SET_FARVAR(seg, info->win_func_ptr , SEGOFF(get_global_seg(), (u32)entry_104f05)); + // Basic information about mode. int width = GET_GLOBAL(vmode_g->width); int height = GET_GLOBAL(vmode_g->height); int linesize = DIV_ROUND_UP(width * vga_bpp(vmode_g), 8); @@ -113,18 +107,50 @@ vbe_104f01(struct bregs *regs) SET_FARVAR(seg, info->xcharsize, GET_GLOBAL(vmode_g->cwidth)); SET_FARVAR(seg, info->ycharsize, GET_GLOBAL(vmode_g->cheight)); int depth = GET_GLOBAL(vmode_g->depth); - int planes = (depth == 4) ? 4 : 1; - SET_FARVAR(seg, info->planes, planes); SET_FARVAR(seg, info->bits_per_pixel, depth); - SET_FARVAR(seg, info->banks, 1); - SET_FARVAR(seg, info->mem_model, GET_GLOBAL(vmode_g->memmodel)); - SET_FARVAR(seg, info->bank_size, 0); - u32 pages = GET_GLOBAL(VBE_total_memory) / ALIGN(height * linesize, 64*1024); - SET_FARVAR(seg, info->pages, (pages / planes) - 1); + u8 memmodel = GET_GLOBAL(vmode_g->memmodel); + SET_FARVAR(seg, info->mem_model, memmodel); SET_FARVAR(seg, info->reserved0, 1); - u8 r_size, r_pos, g_size, g_pos, b_size, b_pos, a_size, a_pos; + // Mode specific info. + u16 mode_attr = VBE_MODE_ATTRIBUTE_SUPPORTED | + VBE_MODE_ATTRIBUTE_EXTENDED_INFORMATION_AVAILABLE | + VBE_MODE_ATTRIBUTE_COLOR_MODE | + VBE_MODE_ATTRIBUTE_GRAPHICS_MODE | + VBE_MODE_ATTRIBUTE_NOT_VGA_COMPATIBLE; + u32 framebuffer = 0; + int planes = 1, banks = 1; + u32 pages = GET_GLOBAL(VBE_total_memory) / ALIGN(height * linesize, 64*1024); + switch (memmodel) { + case MM_TEXT: + mode_attr &= ~VBE_MODE_ATTRIBUTE_GRAPHICS_MODE; + mode_attr |= VBE_MODE_ATTRIBUTE_TTY_BIOS_SUPPORT; + if (GET_GLOBAL(vmode_g->sstart) == SEG_MTEXT) + mode_attr &= ~VBE_MODE_ATTRIBUTE_COLOR_MODE; + pages = 1; + break; + case MM_CGA: + pages = 1; + banks = 2; + SET_FARVAR(seg, info->bank_size, 8); + break; + case MM_PLANAR: + planes = 4; + pages /= 4; + break; + default: + framebuffer = GET_GLOBAL(VBE_framebuffer); + if (framebuffer) + mode_attr |= VBE_MODE_ATTRIBUTE_LINEAR_FRAME_BUFFER_MODE; + break; + } + SET_FARVAR(seg, info->mode_attributes, mode_attr); + SET_FARVAR(seg, info->planes, planes); + SET_FARVAR(seg, info->pages, pages - 1); + SET_FARVAR(seg, info->banks, banks); + // Pixel color breakdown + u8 r_size, r_pos, g_size, g_pos, b_size, b_pos, a_size, a_pos; switch (depth) { case 15: r_size = 5; r_pos = 10; g_size = 5; g_pos = 5; b_size = 5; b_pos = 0; a_size = 1; a_pos = 15; break; @@ -133,11 +159,13 @@ vbe_104f01(struct bregs *regs) case 24: r_size = 8; r_pos = 16; g_size = 8; g_pos = 8; b_size = 8; b_pos = 0; a_size = 0; a_pos = 0; break; case 32: r_size = 8; r_pos = 16; g_size = 8; g_pos = 8; - b_size = 8; b_pos = 0; a_size = 8; a_pos = 24; break; + b_size = 8; b_pos = 0; a_size = 8; a_pos = 24; + SET_FARVAR(seg, info->directcolor_info, + VBE_DIRECTCOLOR_RESERVED_BITS_AVAILABLE); + break; default: r_size = 0; r_pos = 0; g_size = 0; g_pos = 0; b_size = 0; b_pos = 0; a_size = 0; a_pos = 0; break; } - SET_FARVAR(seg, info->red_size, r_size); SET_FARVAR(seg, info->red_pos, r_pos); SET_FARVAR(seg, info->green_size, g_size); @@ -147,31 +175,23 @@ vbe_104f01(struct bregs *regs) SET_FARVAR(seg, info->alpha_size, a_size); SET_FARVAR(seg, info->alpha_pos, a_pos); - if (depth == 32) - SET_FARVAR(seg, info->directcolor_info, - VBE_DIRECTCOLOR_RESERVED_BITS_AVAILABLE); - else - SET_FARVAR(seg, info->directcolor_info, 0); - - if (depth > 4) - SET_FARVAR(seg, info->phys_base, GET_GLOBAL(VBE_framebuffer)); - else - SET_FARVAR(seg, info->phys_base, 0); - - SET_FARVAR(seg, info->reserved1, 0); - SET_FARVAR(seg, info->reserved2, 0); - SET_FARVAR(seg, info->linear_bytes_per_scanline, linesize); - SET_FARVAR(seg, info->bank_pages, 0); - SET_FARVAR(seg, info->linear_pages, 0); - SET_FARVAR(seg, info->linear_red_size, r_size); - SET_FARVAR(seg, info->linear_red_pos, r_pos); - SET_FARVAR(seg, info->linear_green_size, g_size); - SET_FARVAR(seg, info->linear_green_pos, g_pos); - SET_FARVAR(seg, info->linear_blue_size, b_size); - SET_FARVAR(seg, info->linear_blue_pos, b_pos); - SET_FARVAR(seg, info->linear_alpha_size, a_size); - SET_FARVAR(seg, info->linear_alpha_pos, a_pos); - SET_FARVAR(seg, info->pixclock_max, 0); + // Linear framebuffer info. + if (framebuffer) { + SET_FARVAR(seg, info->phys_base, framebuffer); + + SET_FARVAR(seg, info->reserved1, 0); + SET_FARVAR(seg, info->reserved2, 0); + SET_FARVAR(seg, info->linear_bytes_per_scanline, linesize); + SET_FARVAR(seg, info->linear_pages, 0); + SET_FARVAR(seg, info->linear_red_size, r_size); + SET_FARVAR(seg, info->linear_red_pos, r_pos); + SET_FARVAR(seg, info->linear_green_size, g_size); + SET_FARVAR(seg, info->linear_green_pos, g_pos); + SET_FARVAR(seg, info->linear_blue_size, b_size); + SET_FARVAR(seg, info->linear_blue_pos, b_pos); + SET_FARVAR(seg, info->linear_alpha_size, a_size); + SET_FARVAR(seg, info->linear_alpha_pos, a_pos); + } regs->ax = 0x004f; } -- 1.7.11.4

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[PATCH 1/3] vgasrc: Add skeleton for VBE function 15h (VBE/DDC Standard)
by Hiroshi Miura 10 Sep '12

10 Sep '12

posted in Wed Mar 7 03:41:06 CET 2012 Signed-off-by: Julian Pidancet <julian.pidancet(a)gmail.com> Signed-off-by: Hiroshi Miura <miurahr(a)linux.com> --- src/vbe.h | 5 +++++ vgasrc/stdvga.c | 11 +++++++++++ vgasrc/stdvga.h | 2 ++ vgasrc/vbe.c | 34 ++++++++++++++++++++++++++++++++++ vgasrc/vgahw.h | 8 ++++++++ 5 files changed, 60 insertions(+) diff --git a/src/vbe.h b/src/vbe.h index 386613c..b5aedc6 100644 --- a/src/vbe.h +++ b/src/vbe.h @@ -154,4 +154,9 @@ struct vbe_crtc_info { #define VBE_DIRECTCOLOR_COLOR_RAMP_PROGRAMMABLE 0x01 #define VBE_DIRECTCOLOR_RESERVED_BITS_AVAILABLE 0x02 +/* Display Data Channel (DDC) */ +#define VBE_DDC1_PROTOCOL_SUPPORTED 0x01 +#define VBE_DDC2_PROTOCOL_SUPPORTED 0x02 +#define VBE_DDC_BLANK_DURING_TRANSFER 0x04 + #endif diff --git a/vgasrc/stdvga.c b/vgasrc/stdvga.c index ae6c0be..270cd65 100644 --- a/vgasrc/stdvga.c +++ b/vgasrc/stdvga.c @@ -499,3 +499,14 @@ stdvga_init(void) return 0; } + +int stdvga_get_ddc_capabilities(u16 unit) +{ + return -1; +} + +int stdvga_read_edid(u16 unit, u16 block, u16 seg, void *data) +{ + return -1; +} + diff --git a/vgasrc/stdvga.h b/vgasrc/stdvga.h index c9a9ba1..e3bd447 100644 --- a/vgasrc/stdvga.h +++ b/vgasrc/stdvga.h @@ -108,5 +108,7 @@ int stdvga_save_state(u16 seg, void *data, int states); int stdvga_restore_state(u16 seg, void *data, int states); void stdvga_enable_video_addressing(u8 disable); int stdvga_init(void); +int stdvga_get_ddc_capabilities(u16 unit); +int stdvga_read_edid(u16 unit, u16 block, u16 seg, void *data); #endif // stdvga.h diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c index 227a244..ed7c6ee 100644 --- a/vgasrc/vbe.c +++ b/vgasrc/vbe.c @@ -384,6 +384,39 @@ vbe_104f10(struct bregs *regs) } static void +vbe_104f15(struct bregs *regs) +{ + int ret; + u16 seg = regs->es; + void *data = (void *)(regs->di+0); + u16 unit = regs->cx; + u16 block = regs->dx; + + switch (regs->bl) { + case 0x00: /* Report VBE/DDC Capabilities */ + ret = vgahw_get_ddc_capabilities(unit); + if (ret < 0) + goto fail; + regs->bh = ret >> 8; /* Approx. time in seconds, rounded up, to transfer + one EDID block (128 bytes) */ + regs->bl = ret & 0xff; /* DDC level supported */ + break; + case 0x01: /* Read EDID */ + ret = vgahw_read_edid(unit, block, seg, data); + if (ret < 0) + goto fail; + break; + default: + goto fail; + } + regs->ax = 0x004f; + return; + +fail: + regs->ax = 0x014f; +} + +static void vbe_104fXX(struct bregs *regs) { debug_stub(regs); @@ -410,6 +443,7 @@ handle_104f(struct bregs *regs) case 0x08: vbe_104f08(regs); break; case 0x0a: vbe_104f0a(regs); break; case 0x10: vbe_104f10(regs); break; + case 0x15: vbe_104f15(regs); break; default: vbe_104fXX(regs); break; } } diff --git a/vgasrc/vgahw.h b/vgasrc/vgahw.h index 044cd32..01d2609 100644 --- a/vgasrc/vgahw.h +++ b/vgasrc/vgahw.h @@ -129,4 +129,12 @@ static inline int vgahw_restore_state(u16 seg, void *data, int states) { return stdvga_restore_state(seg, data, states); } +static inline int vgahw_get_ddc_capabilities(u16 unit) { + return stdvga_get_ddc_capabilities(unit); +} + +static inline int vgahw_read_edid(u16 unit, u16 block, u16 seg, void *data) { + return stdvga_read_edid(unit, block, seg, data); +} + #endif // vgahw.h -- 1.7.9.5

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[PATCH 2/3] bochsvga: Implement vbe 15h function
by Hiroshi Miura 10 Sep '12

10 Sep '12

This patch adds the ability for the Bochs VGA ROM to return information about a HD wide monitor. It is constructed from definitions at run time. Inspired by this patch I digged out from the vgabios mailing list: http://old.nabble.com/VBE-BIOS-support-for-monitor-information-(EDID)-td229… Signed-off-by: Hiroshi Miura <miurahr(a)linux.com> --- Makefile | 3 +- vgasrc/bochsedid.c | 147 ++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/bochsedid.h | 136 ++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/vgahw.h | 5 ++ 4 files changed, 290 insertions(+), 1 deletion(-) create mode 100644 vgasrc/bochsedid.c create mode 100644 vgasrc/bochsedid.h diff --git a/Makefile b/Makefile index 45ea48a..d3e22b9 100644 --- a/Makefile +++ b/Makefile @@ -189,7 +189,8 @@ $(OUT)bios.bin.elf $(OUT)bios.bin: $(OUT)rom.o tools/checkrom.py SRCVGA=src/output.c src/util.c src/pci.c \ vgasrc/vgabios.c vgasrc/vgafb.c vgasrc/vgafonts.c vgasrc/vbe.c \ vgasrc/stdvga.c vgasrc/stdvgamodes.c vgasrc/stdvgaio.c \ - vgasrc/clext.c vgasrc/bochsvga.c vgasrc/geodevga.c + vgasrc/clext.c vgasrc/bochsvga.c vgasrc/geodevga.c \ + vgasrc/bochsedid.c CFLAGS16VGA = $(CFLAGS16INC) -Isrc diff --git a/vgasrc/bochsedid.c b/vgasrc/bochsedid.c new file mode 100644 index 0000000..5a40593 --- /dev/null +++ b/vgasrc/bochsedid.c @@ -0,0 +1,147 @@ +// VESA VBE EDID capability for virtual display +// +// Copyright (C) 2012 Hiroshi Miura <miurahr(a)linux.com> +// +// This file may be distributed under the terms of the GNU LGPLv3 license. + +#include "vbe.h" // VBE_CAPABILITY_8BIT_DAC +#include "biosvar.h" // GET_GLOBAL +#include "util.h" // dprintf +#include "config.h" // CONFIG_* +#include "bochsedid.h" + +int bochs_get_ddc_capabilities(u16 unit) +{ + if (unit != 0) + return -1; + + return (1 << 8) | VBE_DDC1_PROTOCOL_SUPPORTED; +} + +u8 most_chromaticity[8] VAR16 = {0xA6,0x55,0x48,0x9B,0x26,0x12,0x50,0x54}; +unsigned char vgabios_name[] VAR16 = "Sea VGABIOS"; +struct edid_detailed_timing edid_dtd_1280x1024 VAR16 = { + 0x2a30, 0x00, 0x98, 0x51, 0x00, 0x2A, + 0x40, 0x30, 0x70, 0x13, 0x00, 0x2C, 0xE1, 0x10, + 0x00, 0x00, 0x1E}; +struct edid_detailed_timing edid_dtd_1152x864 VAR16 = { + 0x2a30, 0x80, 0xC0, 0x41, 0x60, 0x24, + 0x30, 0x40, 0x80, 0x13, 0x00, 0x2C, 0xE1, 0x10, + 0x00, 0x00, 0x1E}; +struct edid_detailed_timing edid_dtd_1600x1200 VAR16 = { + 0x3c8c, 0x40, 0x30, 0x62, 0xB0, 0x32, + 0x40, 0x40, 0xC0, 0x13, 0x00, 0x2C, 0xE1, 0x10, + 0x00, 0x00, 0x1E}; +struct edid_detailed_timing edid_dtd_1920x1200 VAR16 = { + 0x4B7D, 0xB0, 0xA0, 0x72, 0xB0, 0x2D, + 0x40, 0x88, 0xC8, 0x55, 0x75, 0x21, + 0x00, 0x00, 0x1C}; +struct edid_monitor_range_limit edid_range_limit VAR16 = { + {0x00,0x00,0x00,0xfD,0x00}, + 50,150, /* Vertical 50Hz - 150Hz */ + 31,135, /* Horiz 31kHz - 135kHz */ + 20, /* clock 200MHz */ + 0, /* no ext */ + 0x0A,0x20,0x20, + 0x2020, + 0x20,0x20 /* padding */ + }; + +int bochs_read_edid_block0(u16 unit, u16 block, u16 seg, void *data, u8 next) +{ + struct edid_info *info = data; + int i; + + memset_far(seg, info, 0, sizeof(*info)); + /* header */ + SET_FARVAR(seg, info->header[0], 0); + for (i = 1; i < 7; i++) { + SET_FARVAR(seg, info->header[i], 0xFF); + } + SET_FARVAR(seg, info->header[7], 0); + /* Vendor/Product/Serial/Date */ + SET_FARVAR(seg, info->vendor, 0x2104); + SET_FARVAR(seg, info->product,0xCDAB); + SET_FARVAR(seg, info->serial, 0x00000000); + /* date/version */ + SET_FARVAR(seg, info->week,36); + SET_FARVAR(seg, info->year,22); /* 2012 */ + SET_FARVAR(seg, info->major_version,1); + SET_FARVAR(seg, info->minor_version,3); /* 1.3 */ + /* video prameters */ + SET_FARVAR(seg, info->video_setup,0x0F); + /* Video signal interface (analogue, 0.700 : 0.300 : 1.000 V p-p, + Video Setup: Blank Level = Black Level, Separate Sync H & V Signals are + supported, Composite Sync Signal on Horizontal is supported, Composite + Sync Signal on Green Video is supported, Serration on the Vertical Sync + is supported) */ + SET_FARVAR(seg, info->screen_width,0x21); + SET_FARVAR(seg, info->screen_height,0x19); /* 330 mm * 250 mm */ + SET_FARVAR(seg, info->gamma,0x78); /* 2.2 */ + SET_FARVAR(seg, info->feature_flag,0x0F); /* no DMPS states, RGB, display is continuous frequency, prefered mode */ + SET_FARVAR(seg, info->least_chromaticity[0],0x78); + SET_FARVAR(seg, info->least_chromaticity[1],0xF5); + memcpy_far(seg, info->most_chromaticity, get_global_seg(), most_chromaticity, + sizeof (most_chromaticity)); + + SET_FARVAR(seg, info->established_timing[0], 0xFF); + SET_FARVAR(seg, info->established_timing[1], 0xEF); + SET_FARVAR(seg, info->established_timing[2], 0x80); + /* 720x400@70Hz, 720x400@88Hz, 640x480@60Hz, 640x480@67Hz, 640x480@72Hz, 640x480@75Hz, + 800x600@56Hz, 800x600@60Hz, 800x600@72Hz, 800x600@75Hz, 832x624@75Hz, 1152x870@75Hz, + not 1024x768@87Hz(I), 1024x768@60Hz, 1024x768@70Hz, 1024x768@75Hz, 1280x1024@75Hz */ + /* standard timings */ + SET_FARVAR(seg, info->standard_timing[0], EDID_STD_640x480_85Hz); + SET_FARVAR(seg, info->standard_timing[1], EDID_STD_800x600_85Hz); + SET_FARVAR(seg, info->standard_timing[2], EDID_STD_1024x768_85Hz); + SET_FARVAR(seg, info->standard_timing[3], EDID_STD_1280x720_70Hz); + SET_FARVAR(seg, info->standard_timing[4], EDID_STD_1280x960_60Hz); + SET_FARVAR(seg, info->standard_timing[5], EDID_STD_1440x900_60Hz); + SET_FARVAR(seg, info->standard_timing[6], EDID_STD_1600x1200_60Hz); + SET_FARVAR(seg, info->standard_timing[7], EDID_STD_NOP); + /* detailed timing blocks */ + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1600x1200, + sizeof (edid_dtd_1600x1200)); + /* monitor range */ + memcpy_far(seg, &(info->desc[1].mrld), get_global_seg(), &edid_range_limit, + sizeof(edid_range_limit)); + /* serial */ + for (i = 0; i < 5; i++) { + SET_FARVAR(seg, info->desc[2].mtxtd.header[i], 0); + } + SET_FARVAR(seg, info->desc[2].mtxtd.header[3], 0xFF); + for (i = 0; i < 10; i++) { + SET_FARVAR(seg, info->desc[2].mtxtd.text[i], i+0x30); + } + SET_FARVAR(seg, info->desc[2].mtxtd.text[10], 0x0A); + SET_FARVAR(seg, info->desc[2].mtxtd.text[11], 0x20); + SET_FARVAR(seg, info->desc[2].mtxtd.text[12], 0x20); + /* monitor name */ + for (i = 0; i < 5; i++) { + SET_FARVAR(seg, info->desc[3].mtxtd.header[i], 0); + } + SET_FARVAR(seg, info->desc[3].mtxtd.header[3], 0xFC); + memcpy_far(seg, info->desc[3].mtxtd.text, get_global_seg(), vgabios_name, 12); + SET_FARVAR(seg, info->desc[3].mtxtd.text[12], 0x0A); + /* ext */ + SET_FARVAR(seg, info->extensions, next); + + /* checksum */ + u8 sum = -checksum_far(get_global_seg(), info, sizeof(info)); + SET_FARVAR(seg, info->checksum, sum); + + return 0; +} + +int bochs_read_edid(u16 unit, u16 block, u16 seg, void *data) +{ + if (unit != 0) + return -1; + + switch (block) { + case 0: + return bochs_read_edid_block0(unit, block, seg, data, 0); + default: + return -1; + } +} diff --git a/vgasrc/bochsedid.h b/vgasrc/bochsedid.h new file mode 100644 index 0000000..0f925df --- /dev/null +++ b/vgasrc/bochsedid.h @@ -0,0 +1,136 @@ +#ifndef __BOCHEDID_H +#define __BOCHEDID_H + +/* EDID infomation definitions */ +/* Detailed Timing Descriptor */ +struct edid_detailed_timing { + u16 pixel_clock; + u8 horizontal_addressable_low; + u8 horizontal_blanking_low; + u8 horizontal_high; + u8 vertical_addressable_low; + u8 vertical_blanking_low; + u8 vertical_high; + u8 horizontal_front_porch_low; + u8 horizontal_sync_pulse_low; + u8 vertical_low4; + u8 horizontal_vertical_sync_hi; + u8 horizontal_video_image_low; + u8 vertical_video_image_low; + u8 video_image_high; + u8 horizontal_border; + u8 vertical_border; + u8 features; +} PACKED; + +/* Other Monitor Descriptors */ +/* + 0xFF: Monitor serial number (text) + 0xFE: Unspecified text (text) + 0xFC: Monitor name (text) + */ +struct edid_monitor_text { + u8 header[5]; + u8 text[13]; +} PACKED; + +/* Monitor Range Limits Descriptor */ +/* + 0xFD: Monitor range limits. 6- or 13-byte binary descriptor. + */ +struct edid_monitor_range_limit { + u8 header[5]; + u8 vertical_rate_min; + u8 vertical_rate_max; + u8 horizontal_rate_min; + u8 horizontal_rate_max; + u8 pixel_clock_max; + u8 extended_timing_type; + u8 reserved; + u8 start_frequency; + u8 gtf_c_val; + u16 gtf_m_val; + u8 gtf_k_val; + u8 gtf_j_val; +} PACKED; + +/* White point Descriptor */ +/* + 0xFB: Additional white point data. 2Ã 5-byte descriptors, padded with 0A 20 20. + 0xFA: Additional standard timing identifiers. 6Ã 2-byte descriptors, padded with 0A + */ +struct edid_wp_desc { + u8 index; + u8 least; + u8 x; + u8 y; + u8 gamma; +} PACKED; + +struct edid_white_point { + u8 header[5]; + struct edid_wp_desc desc[2]; + u8 padding[3]; +} PACKED; + +struct edid_additional_timing { + u8 header[5]; + u16 standard_timing[6]; + u8 padding; +} PACKED; + +union edid_descriptors { + struct edid_detailed_timing dtd; + struct edid_monitor_range_limit mrld; + struct edid_monitor_text mtxtd; + struct edid_white_point wpd; + struct edid_additional_timing astd; +} PACKED; + +struct edid_info { + u8 header[8]; + u16 vendor; + u16 product; + u32 serial; + u8 week; + u8 year; + u8 major_version; + u8 minor_version; + u8 video_setup; + u8 screen_width; + u8 screen_height; + u8 gamma; + u8 feature_flag; + u8 least_chromaticity[2]; + u8 most_chromaticity[8]; + u8 established_timing[3]; + u16 standard_timing[8]; + union edid_descriptors desc[4]; + u8 extensions; + u8 checksum; +} PACKED; + +/* EDID Standard Timing Description */ + +/* First byte: X resolution, divided by 8, less 31 (256â2288 pixels) */ +/* bit 7-6, X:Y pixel ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9 */ +/* bit 5-0, Vertical frequency, less 60 (60â123 Hz), nop 01 01 in Big Endian*/ +#define EDID_STD_640x480_85Hz 0x5931 +#define EDID_STD_800x600_85Hz 0x5945 +#define EDID_STD_1024x768_85Hz 0x5961 +#define EDID_STD_1152x864_70Hz 0x4A71 +#define EDID_STD_1280x720_70Hz 0xCA81 +#define EDID_STD_1280x800_70Hz 0x0A81 +#define EDID_STD_1280x960_60Hz 0x4081 +#define EDID_STD_1280x1024_60Hz 0x8081 +#define EDID_STD_1440x900_60Hz 0x0095 +#define EDID_STD_1600x1200_60Hz 0x40A9 +#define EDID_STD_1600x900_60Hz 0xC0A9 +#define EDID_STD_1680x1050_60Hz 0x00B3 +#define EDID_STD_1920x1080_60Hz 0xC0D1 +#define EDID_STD_1920x1200_60Hz 0x00D1 +#define EDID_STD_NOP 0x0101 + +int bochs_get_ddc_capabilities(u16 unit); +int bochs_read_edid(u16 unit, u16 block, u16 seg, void *data); +#endif /* bochedid.h */ diff --git a/vgasrc/vgahw.h b/vgasrc/vgahw.h index 01d2609..130462c 100644 --- a/vgasrc/vgahw.h +++ b/vgasrc/vgahw.h @@ -8,6 +8,7 @@ #include "bochsvga.h" // bochsvga_set_mode #include "stdvga.h" // stdvga_set_mode #include "geodevga.h" // geodevga_init +#include "bochsedid.h" static inline struct vgamode_s *vgahw_find_mode(int mode) { if (CONFIG_VGA_CIRRUS) @@ -130,10 +131,14 @@ static inline int vgahw_restore_state(u16 seg, void *data, int states) { } static inline int vgahw_get_ddc_capabilities(u16 unit) { + if (CONFIG_VGA_BOCHS) + return bochs_get_ddc_capabilities(unit); return stdvga_get_ddc_capabilities(unit); } static inline int vgahw_read_edid(u16 unit, u16 block, u16 seg, void *data) { + if (CONFIG_VGA_BOCHS) + return bochs_read_edid(unit, block, seg, data); return stdvga_read_edid(unit, block, seg, data); } -- 1.7.9.5

2 1

[PATCH 0/3] EDID support for vgabios
by Hiroshi Miura 09 Sep '12

09 Sep '12

rework of EDID support in bochs vgabios tested with mint linux 13 resulted Xorg.0.log is as follows: [ 62.165] (II) VESA(0): VESA VBE DDC supported [ 62.165] (II) VESA(0): VESA VBE DDC Level 1 [ 62.165] (II) VESA(0): VESA VBE DDC transfer in appr. 1 sec. [ 62.237] (II) VESA(0): VESA VBE DDC read successfully [ 62.251] (II) VESA(0): Manufacturer: AAA Model: cdab Serial#: 0 [ 62.251] (II) VESA(0): Year: 2012 Week: 36 [ 62.251] (II) VESA(0): EDID Version: 1.3 [ 62.251] (II) VESA(0): Analog Display Input, Input Voltage Level: 0.700/0.300 V [ 62.251] (II) VESA(0): Sync: Separate Composite SyncOnGreenSerration on. V.Sync Pulse req. if CompSync or SyncOnGreen [ 62.251] (II) VESA(0): Max Image Size [cm]: horiz.: 33 vert.: 25 [ 62.251] (II) VESA(0): Gamma: 2.20 [ 62.251] (II) VESA(0): No DPMS capabilities specified; RGB/Color Display [ 62.251] (II) VESA(0): Default color space is primary color space [ 62.251] (II) VESA(0): First detailed timing is preferred mode [ 62.251] (II) VESA(0): GTF timings supported [ 62.251] (II) VESA(0): redX: 0.649 redY: 0.335 greenX: 0.283 greenY: 0.605 [ 62.251] (II) VESA(0): blueX: 0.151 blueY: 0.073 whiteX: 0.313 whiteY: 0.329 [ 62.252] (II) VESA(0): Supported established timings: [ 62.252] (II) VESA(0): 720x400@70Hz [ 62.252] (II) VESA(0): 720x400@88Hz [ 62.252] (II) VESA(0): 640x480@60Hz [ 62.252] (II) VESA(0): 640x480@67Hz [ 62.252] (II) VESA(0): 640x480@72Hz [ 62.252] (II) VESA(0): 640x480@75Hz [ 62.252] (II) VESA(0): 800x600@56Hz [ 62.252] (II) VESA(0): 800x600@60Hz [ 62.252] (II) VESA(0): 800x600@72Hz [ 62.252] (II) VESA(0): 800x600@75Hz [ 62.252] (II) VESA(0): 832x624@75Hz [ 62.252] (II) VESA(0): 1024x768@60Hz [ 62.252] (II) VESA(0): 1024x768@70Hz [ 62.252] (II) VESA(0): 1024x768@75Hz [ 62.252] (II) VESA(0): 1280x1024@75Hz [ 62.252] (II) VESA(0): 1152x864@75Hz [ 62.252] (II) VESA(0): Manufacturer's mask: 0 [ 62.252] (II) VESA(0): Supported standard timings: [ 62.252] (II) VESA(0): #0: hsize: 640 vsize 480 refresh: 85 vid: 22833 [ 62.252] (II) VESA(0): #1: hsize: 800 vsize 600 refresh: 85 vid: 22853 [ 62.252] (II) VESA(0): #2: hsize: 1440 vsize 900 refresh: 60 vid: 149 [ 62.252] (II) VESA(0): #3: hsize: 1920 vsize 1200 refresh: 60 vid: 209 [ 62.252] (II) VESA(0): Supported detailed timing: [ 62.252] (II) VESA(0): clock: 193.2 MHz Image Size: 33 x 0 mm [ 62.252] (II) VESA(0): h_active: 1968 h_sync: 2360 h_sync_end 3328 h_blank_end 2640 h_border: 28 [ 62.252] (II) VESA(0): v_active: 1200 v_sync: 1221 v_sync_end 1242 v_blanking: 1245 v_border: 0 [ 62.252] (II) VESA(0): Ranges: V min: 50 V max: 150 Hz, H min: 31 H max: 135 kHz, PixClock max 205 MHz [ 62.253] (II) VESA(0): Serial No: 0123456789 [ 62.253] (II) VESA(0): Monitor name: Sea VGABIOS [ 62.253] (II) VESA(0): EDID (in hex): [ 62.253] (II) VESA(0): 00ffffffffffff000421abcd00000000 [ 62.253] (II) VESA(0): 241601030f2119780f78f5a655489b26 [ 62.253] (II) VESA(0): 125054ffef80315945599500d1000101 [ 62.253] (II) VESA(0): 0101010101017d4bb0a072b02d4088c8 [ 62.253] (II) VESA(0): 55752100001c0000000000fd0032961f [ 62.253] (II) VESA(0): 8714000a202020202020000000ff0030 [ 62.253] (II) VESA(0): 3132333435363738390a2020000000fc [ 62.253] (II) VESA(0): 005365612056474142494f53000a00b2 [ 62.253] (II) VESA(0): EDID vendor "AAA", prod id 52651 [ 62.253] (II) VESA(0): DDCModeFromDetailedTiming: 1968x1200 Warning: We only handle separate sync. [ 62.253] (II) VESA(0): Using EDID range info for horizontal sync [ 62.253] (II) VESA(0): Using EDID range info for vertical refresh [ 62.253] (II) VESA(0): Printing DDC gathered Modelines: [ 62.253] (II) VESA(0): Modeline "800x600"x0.0 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz) [ 62.253] (II) VESA(0): Modeline "800x600"x0.0 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (35.2 kHz) [ 62.253] (II) VESA(0): Modeline "640x480"x0.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz) [ 62.253] (II) VESA(0): Modeline "640x480"x0.0 31.50 640 664 704 832 480 489 492 520 -hsync -vsync (37.9 kHz) [ 62.253] (II) VESA(0): Modeline "640x480"x0.0 30.24 640 704 768 864 480 483 486 525 -hsync -vsync (35.0 kHz) [ 62.253] (II) VESA(0): Modeline "640x480"x0.0 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz) [ 62.253] (II) VESA(0): Modeline "720x400"x0.0 35.50 720 738 846 900 400 421 423 449 -hsync -vsync (39.4 kHz) [ 62.253] (II) VESA(0): Modeline "720x400"x0.0 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz) [ 62.253] (II) VESA(0): Modeline "1280x1024"x0.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz) [ 62.253] (II) VESA(0): Modeline "1024x768"x0.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz) [ 62.253] (II) VESA(0): Modeline "1024x768"x0.0 75.00 1024 1048 1184 1328 768 771 777 806 -hsync -vsync (56.5 kHz) [ 62.253] (II) VESA(0): Modeline "1024x768"x0.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz) [ 62.253] (II) VESA(0): Modeline "832x624"x0.0 57.28 832 864 928 1152 624 625 628 667 -hsync -vsync (49.7 kHz) [ 62.253] (II) VESA(0): Modeline "800x600"x0.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz) [ 62.253] (II) VESA(0): Modeline "800x600"x0.0 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (48.1 kHz) [ 62.253] (II) VESA(0): Modeline "1152x864"x0.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz) [ 62.253] (II) VESA(0): Modeline "640x480"x0.0 36.00 640 696 752 832 480 481 484 509 -hsync -vsync (43.3 kHz) [ 62.253] (II) VESA(0): Modeline "800x600"x0.0 56.25 800 832 896 1048 600 601 604 631 +hsync +vsync (53.7 kHz) [ 62.253] (II) VESA(0): Modeline "1440x900"x0.0 106.50 1440 1520 1672 1904 900 903 909 934 -hsync +vsync (55.9 kHz) [ 62.253] (II) VESA(0): Modeline "1920x1200"x0.0 193.25 1920 2056 2256 2592 1200 1203 1209 1245 -hsync +vsync (74.6 kHz) [ 62.253] (II) VESA(0): Searching for matching VESA mode(s): [snip] [ 62.384] (II) VESA(0): Total Memory: 256 64KB banks (16384kB) [ 62.384] (II) VESA(0): <default monitor>: Using hsync range of 31.00-135.00 kHz [ 62.384] (II) VESA(0): <default monitor>: Using vrefresh range of 50.00-150.00 Hz [ 62.384] (II) VESA(0): <default monitor>: Using maximum pixel clock of 205.00 MHz [ 62.384] (WW) VESA(0): Unable to estimate virtual size [ 62.384] (II) VESA(0): Not using built-in mode "2560x1600" (no mode of this name) [ 62.385] (II) VESA(0): Not using built-in mode "1600x1200" (no mode of this name) [ 62.385] (II) VESA(0): Not using built-in mode "1680x1050" (no mode of this name) [ 62.385] (II) VESA(0): Not using built-in mode "1400x1050" (no mode of this name) [ 62.386] (II) VESA(0): Not using built-in mode "1280x960" (no mode of this name) [ 62.386] (II) VESA(0): Not using built-in mode "1280x800" (no mode of this name) [ 62.389] (II) VESA(0): Not using built-in mode "640x400" (no mode of this name) [ 62.389] (II) VESA(0): Not using built-in mode "320x200" (no mode of this name) [ 62.389] (--) VESA(0): Virtual size is 1920x1200 (pitch 1920) [ 62.389] (**) VESA(0): *Built-in mode "1920x1200" [ 62.389] (**) VESA(0): *Built-in mode "1280x1024" [ 62.389] (**) VESA(0): *Built-in mode "1440x900" [ 62.389] (**) VESA(0): *Built-in mode "1152x864" [ 62.389] (**) VESA(0): *Built-in mode "1024x768" [ 62.389] (**) VESA(0): *Built-in mode "800x600" [ 62.389] (**) VESA(0): *Built-in mode "640x480" [ 62.389] (**) VESA(0): Display dimensions: (330, 250) mm [ 62.389] (**) VESA(0): DPI set to (147, 121) Hiroshi Miura (3): vgasrc: Add skeleton for VBE function 15h (VBE/DDC Standard) bochsvga: Implement vbe 15h function bochsvga: dynamic generation of EDID Makefile | 3 +- src/vbe.h | 5 ++ vgasrc/bochsedid.c | 181 ++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/bochsedid.h | 137 +++++++++++++++++++++++++++++++++++++++ vgasrc/bochsvga.c | 2 + vgasrc/stdvga.c | 11 ++++ vgasrc/stdvga.h | 2 + vgasrc/vbe.c | 34 ++++++++++ vgasrc/vgahw.h | 13 ++++ 9 files changed, 387 insertions(+), 1 deletion(-) create mode 100644 vgasrc/bochsedid.c create mode 100644 vgasrc/bochsedid.h -- 1.7.9.5

1 0

Is there any sheduler for supporting USB 3.0 in SeaBIOS ?
by wx 08 Sep '12

08 Sep '12

Hi, Is there any plan for supporting USB 3.0?Thanks!

2 1

[PATCH] Use cpu_to_be32() (and related) instead of htonl (and related).
by Kevin O'Connor 08 Sep '12

08 Sep '12

Unify the syntax for byte swab calls. This also fixes a bug in coreboot due to the lack of a be64_to_cpu() call. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/ata.c | 3 ++- src/blockcmd.c | 17 +++++++------- src/byteorder.h | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/coreboot.c | 31 +++++++++++++------------- src/paravirt.c | 9 ++++---- src/util.h | 30 ------------------------- vgasrc/vgafb.c | 3 ++- 7 files changed, 103 insertions(+), 59 deletions(-) create mode 100644 src/byteorder.h diff --git a/src/ata.c b/src/ata.c index 7ff5f86..f604b37 100644 --- a/src/ata.c +++ b/src/ata.c @@ -8,6 +8,7 @@ #include "types.h" // u8 #include "ioport.h" // inb #include "util.h" // dprintf +#include "byteorder.h" // be16_to_cpu #include "cmos.h" // inb_cmos #include "pic.h" // enable_hwirq #include "biosvar.h" // GET_GLOBAL @@ -696,7 +697,7 @@ ata_extract_model(char *model, u32 size, u16 *buffer) // Read model name int i; for (i=0; i<size/2; i++) - *(u16*)&model[i*2] = ntohs(buffer[27+i]); + *(u16*)&model[i*2] = be16_to_cpu(buffer[27+i]); model[size] = 0x00; nullTrailingSpace(model); return model; diff --git a/src/blockcmd.c b/src/blockcmd.c index 97c72a6..77c690f 100644 --- a/src/blockcmd.c +++ b/src/blockcmd.c @@ -6,7 +6,8 @@ // This file may be distributed under the terms of the GNU LGPLv3 license. #include "biosvar.h" // GET_GLOBAL -#include "util.h" // htonl +#include "util.h" // dprintf +#include "byteorder.h" // be32_to_cpu #include "disk.h" // struct disk_op_s #include "blockcmd.h" // struct cdb_request_sense #include "ata.h" // atapi_cmd_data @@ -144,12 +145,12 @@ scsi_init_drive(struct drive_s *drive, const char *s, int prio) // READ CAPACITY returns the address of the last block. // We do not bother with READ CAPACITY(16) because BIOS does not support // 64-bit LBA anyway. - drive->blksize = ntohl(capdata.blksize); + drive->blksize = be32_to_cpu(capdata.blksize); if (drive->blksize != DISK_SECTOR_SIZE) { dprintf(1, "%s: unsupported block size %d\n", s, drive->blksize); return -1; } - drive->sectors = (u64)ntohl(capdata.sectors) + 1; + drive->sectors = (u64)be32_to_cpu(capdata.sectors) + 1; dprintf(1, "%s blksize=%d sectors=%d\n" , s, drive->blksize, (unsigned)drive->sectors); @@ -243,7 +244,7 @@ cdb_mode_sense_geom(struct disk_op_s *op, struct cdbres_mode_sense_geom *data) cmd.command = CDB_CMD_MODE_SENSE; cmd.flags = 8; /* DBD */ cmd.page = MODE_PAGE_HD_GEOMETRY; - cmd.count = htons(sizeof(*data)); + cmd.count = cpu_to_be16(sizeof(*data)); op->count = 1; op->buf_fl = data; return cdb_cmd_data(op, &cmd, sizeof(*data)); @@ -256,8 +257,8 @@ cdb_read(struct disk_op_s *op) struct cdb_rwdata_10 cmd; memset(&cmd, 0, sizeof(cmd)); cmd.command = CDB_CMD_READ_10; - cmd.lba = htonl(op->lba); - cmd.count = htons(op->count); + cmd.lba = cpu_to_be32(op->lba); + cmd.count = cpu_to_be16(op->count); return cdb_cmd_data(op, &cmd, GET_GLOBAL(op->drive_g->blksize)); } @@ -268,7 +269,7 @@ cdb_write(struct disk_op_s *op) struct cdb_rwdata_10 cmd; memset(&cmd, 0, sizeof(cmd)); cmd.command = CDB_CMD_WRITE_10; - cmd.lba = htonl(op->lba); - cmd.count = htons(op->count); + cmd.lba = cpu_to_be32(op->lba); + cmd.count = cpu_to_be16(op->count); return cdb_cmd_data(op, &cmd, GET_GLOBAL(op->drive_g->blksize)); } diff --git a/src/byteorder.h b/src/byteorder.h new file mode 100644 index 0000000..94e3a3b --- /dev/null +++ b/src/byteorder.h @@ -0,0 +1,69 @@ +#ifndef __BYTEORDER_H +#define __BYTEORDER_H + +static inline u16 __swab16_constant(u16 val) { + return (val<<8) | (val>>8); +} +static inline u32 __swab32_constant(u32 val) { + return (val<<24) | ((val&0xff00)<<8) | ((val&0xff0000)>>8) | (val>>24); +} +static inline u64 __swab64_constant(u64 val) { + return ((u64)__swab32_constant(val) << 32) | __swab32_constant(val>>32); +} +static inline u32 __swab32(u32 val) { + asm("bswapl %0" : "+r"(val)); + return val; +} +static inline u64 __swab64(u64 val) { + union u64_u32_u i, o; + i.val = val; + o.hi = __swab32(i.lo); + o.lo = __swab32(i.hi); + return o.val; +} + +#define swab16(x) __swab16_constant(x) +#define swab32(x) (__builtin_constant_p((u32)(x)) \ + ? __swab32_constant(x) : __swab32(x)) +#define swab64(x) (__builtin_constant_p((u64)(x)) \ + ? __swab64_constant(x) : __swab64(x)) + +static inline u16 cpu_to_le16(u16 x) { + return x; +} +static inline u32 cpu_to_le32(u32 x) { + return x; +} +static inline u64 cpu_to_le64(u64 x) { + return x; +} +static inline u16 le16_to_cpu(u16 x) { + return x; +} +static inline u32 le32_to_cpu(u32 x) { + return x; +} +static inline u32 le64_to_cpu(u64 x) { + return x; +} + +static inline u16 cpu_to_be16(u16 x) { + return swab16(x); +} +static inline u32 cpu_to_be32(u32 x) { + return swab32(x); +} +static inline u64 cpu_to_be64(u64 x) { + return swab64(x); +} +static inline u16 be16_to_cpu(u16 x) { + return swab16(x); +} +static inline u32 be32_to_cpu(u32 x) { + return swab32(x); +} +static inline u32 be64_to_cpu(u64 x) { + return swab64(x); +} + +#endif // byteorder.h diff --git a/src/coreboot.c b/src/coreboot.c index 55590ce..e4767f1 100644 --- a/src/coreboot.c +++ b/src/coreboot.c @@ -6,6 +6,7 @@ #include "memmap.h" // add_e820 #include "util.h" // dprintf +#include "byteorder.h" // be32_to_cpu #include "lzmadecode.h" // LzmaDecode #include "smbios.h" // smbios_init #include "boot.h" // boot_add_cbfs @@ -329,17 +330,17 @@ coreboot_cbfs_setup(void) return; struct cbfs_header *hdr = *(void **)CBFS_HEADPTR_ADDR; - if (hdr->magic != htonl(CBFS_HEADER_MAGIC)) { + if (hdr->magic != cpu_to_be32(CBFS_HEADER_MAGIC)) { dprintf(1, "Unable to find CBFS (ptr=%p; got %x not %x)\n" - , hdr, hdr->magic, htonl(CBFS_HEADER_MAGIC)); + , hdr, hdr->magic, cpu_to_be32(CBFS_HEADER_MAGIC)); return; } dprintf(1, "Found CBFS header at %p\n", hdr); - struct cbfs_file *cfile = (void *)(0 - ntohl(hdr->romsize) - + ntohl(hdr->offset)); + struct cbfs_file *cfile = (void *)(0 - be32_to_cpu(hdr->romsize) + + be32_to_cpu(hdr->offset)); for (;;) { - if (cfile < (struct cbfs_file *)(0xFFFFFFFF - ntohl(hdr->romsize))) + if (cfile < (struct cbfs_file *)(0xFFFFFFFF - be32_to_cpu(hdr->romsize))) break; u64 magic = cfile->magic; if (magic != CBFS_FILE_MAGIC) @@ -352,10 +353,10 @@ coreboot_cbfs_setup(void) memset(file, 0, sizeof(*file)); strtcpy(file->name, cfile->filename, sizeof(file->name)); dprintf(3, "Found CBFS file: %s\n", file->name); - file->size = file->rawsize = ntohl(cfile->len); + file->size = file->rawsize = be32_to_cpu(cfile->len); file->id = (u32)cfile; file->copy = cbfs_copyfile; - file->data = (void*)cfile + ntohl(cfile->offset); + file->data = (void*)cfile + be32_to_cpu(cfile->offset); int len = strlen(file->name); if (len > 5 && strcmp(&file->name[len-5], ".lzma") == 0) { // Using compression. @@ -365,7 +366,7 @@ coreboot_cbfs_setup(void) } romfile_add(file); - cfile = (void*)ALIGN((u32)file->data + file->size, ntohl(hdr->align)); + cfile = (void*)ALIGN((u32)file->data + file->size, be32_to_cpu(hdr->align)); } } @@ -394,13 +395,13 @@ cbfs_run_payload(struct cbfs_file *file) if (!CONFIG_COREBOOT || !CONFIG_COREBOOT_FLASH || !file) return; dprintf(1, "Run %s\n", file->filename); - struct cbfs_payload *pay = (void*)file + ntohl(file->offset); + struct cbfs_payload *pay = (void*)file + be32_to_cpu(file->offset); struct cbfs_payload_segment *seg = pay->segments; for (;;) { - void *src = (void*)pay + ntohl(seg->offset); - void *dest = (void*)ntohl((u32)seg->load_addr); - u32 src_len = ntohl(seg->len); - u32 dest_len = ntohl(seg->mem_len); + void *src = (void*)pay + be32_to_cpu(seg->offset); + void *dest = (void*)(u32)be64_to_cpu(seg->load_addr); + u32 src_len = be32_to_cpu(seg->len); + u32 dest_len = be32_to_cpu(seg->mem_len); switch (seg->type) { case PAYLOAD_SEGMENT_BSS: dprintf(3, "BSS segment %d@%p\n", dest_len, dest); @@ -415,12 +416,12 @@ cbfs_run_payload(struct cbfs_file *file) default: dprintf(3, "Segment %x %d@%p -> %d@%p\n" , seg->type, src_len, src, dest_len, dest); - if (seg->compression == htonl(CBFS_COMPRESS_NONE)) { + if (seg->compression == cpu_to_be32(CBFS_COMPRESS_NONE)) { if (src_len > dest_len) src_len = dest_len; memcpy(dest, src, src_len); } else if (CONFIG_LZMA - && seg->compression == htonl(CBFS_COMPRESS_LZMA)) { + && seg->compression == cpu_to_be32(CBFS_COMPRESS_LZMA)) { int ret = ulzma(dest, dest_len, src, src_len); if (ret < 0) return; diff --git a/src/paravirt.c b/src/paravirt.c index 2a98d53..4b5c441 100644 --- a/src/paravirt.c +++ b/src/paravirt.c @@ -8,7 +8,8 @@ // This file may be distributed under the terms of the GNU LGPLv3 license. #include "config.h" // CONFIG_COREBOOT -#include "util.h" // ntoh[ls] +#include "util.h" // dprintf +#include "byteorder.h" // be32_to_cpu #include "ioport.h" // outw #include "paravirt.h" // qemu_cfg_port_probe #include "smbios.h" // struct smbios_structure_header @@ -327,7 +328,7 @@ void qemu_cfg_romfile_setup(void) u32 count; qemu_cfg_read_entry(&count, QEMU_CFG_FILE_DIR, sizeof(count)); - count = ntohl(count); + count = be32_to_cpu(count); u32 e; for (e = 0; e < count; e++) { struct QemuCfgFile qfile; @@ -339,8 +340,8 @@ void qemu_cfg_romfile_setup(void) } memset(file, 0, sizeof(*file)); strtcpy(file->name, qfile.name, sizeof(file->name)); - file->size = ntohl(qfile.size); - file->id = ntohs(qfile.select); + file->size = be32_to_cpu(qfile.size); + file->id = be16_to_cpu(qfile.select); file->copy = qemu_cfg_read_file; romfile_add(file); dprintf(3, "Found fw_cfg file: %s (size=%d)\n", file->name, file->size); diff --git a/src/util.h b/src/util.h index 89e928c..062eea3 100644 --- a/src/util.h +++ b/src/util.h @@ -104,36 +104,6 @@ static inline u32 __fls(u32 word) return word; } -static inline u16 __htons_constant(u16 val) { - return (val<<8) | (val>>8); -} -static inline u32 __htonl_constant(u32 val) { - return (val<<24) | ((val&0xff00)<<8) | ((val&0xff0000)>>8) | (val>>24); -} -static inline u32 __htonl(u32 val) { - asm("bswapl %0" : "+r"(val)); - return val; -} -#define htonl(x) (__builtin_constant_p((u32)(x)) ? __htonl_constant(x) : __htonl(x)) -#define ntohl(x) htonl(x) -#define htons(x) __htons_constant(x) -#define ntohs(x) htons(x) - -static inline u16 cpu_to_le16(u16 x) -{ - return x; -} - -static inline u32 cpu_to_le32(u32 x) -{ - return x; -} - -static inline u32 le32_to_cpu(u32 x) -{ - return x; -} - static inline u32 getesp(void) { u32 esp; asm("movl %%esp, %0" : "=rm"(esp)); diff --git a/vgasrc/vgafb.c b/vgasrc/vgafb.c index 233f3d5..3b2f367 100644 --- a/vgasrc/vgafb.c +++ b/vgasrc/vgafb.c @@ -8,6 +8,7 @@ #include "vgabios.h" // vgafb_scroll #include "biosvar.h" // GET_BDA #include "util.h" // memset_far +#include "byteorder.h" // cpu_to_be16 #include "stdvga.h" // stdvga_planar4_plane @@ -272,7 +273,7 @@ write_gfx_char_cga(struct vgamode_s *vmode_g for (j = 0; j < 8; j++) if (fontline & (1<<j)) pixels |= (ca.attr & 0x03) << (j*2); - pixels = htons(pixels); + pixels = cpu_to_be16(pixels); if (ca.attr & 0x80) pixels ^= GET_FARVAR(SEG_GRAPH, *(u16*)dest_far); SET_FARVAR(SEG_CTEXT, *(u16*)dest_far, pixels); -- 1.7.11.2

2 3

Re: [SeaBIOS] [PATCH 0/6] vgabios: VBE int 15h EDID information
by Hiroshi Miura 08 Sep '12

08 Sep '12

Hi, , Christian Gmeiner wrote: > > > Will you provide some new patches in the next 1-2 days? I am asking because I > am waiting for your EDID stuff as I need them to and have some patches by my > own for it. > Yes, I'm now working for it. Thanks, Hiroshi

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SeaBIOS September 2012