SeaBIOS September 2012

seabios@seabios.org

27 participants
112 discussions

[PATCH 3/3] bochsvga: validate EDID resolution in init
by Hiroshi Miura 16 Sep '12

16 Sep '12

As same as bochsvga that init code disables modes that is larger than max_{x|y}res, bochsedid also disables STD_EDID that is larger than max_{x|y}res. The int15h returns largest and smaller edid mode than MAX_XRES, MAX_YRES. Signed-off-by: Hiroshi Miura <miurahr(a)linux.com> --- vgasrc/bochsedid.c | 74 ++++++++++++++++++++++++++++++++++++++++++++-------- vgasrc/bochsedid.h | 6 +++++ vgasrc/bochsvga.c | 6 ++++- 3 files changed, 74 insertions(+), 12 deletions(-) diff --git a/vgasrc/bochsedid.c b/vgasrc/bochsedid.c index 5a40593..022a850 100644 --- a/vgasrc/bochsedid.c +++ b/vgasrc/bochsedid.c @@ -20,6 +20,26 @@ int bochs_get_ddc_capabilities(u16 unit) u8 most_chromaticity[8] VAR16 = {0xA6,0x55,0x48,0x9B,0x26,0x12,0x50,0x54}; unsigned char vgabios_name[] VAR16 = "Sea VGABIOS"; +static struct bochs_edid_mode { + u16 mode; + u16 width; + u16 height; + u8 ratio; +} bochs_edid_modes[] VAR16 = { +{EDID_STD_1920x1200_60Hz,1920,1200, EDID_STD_RATIO_16_10}, +{EDID_STD_1920x1080_60Hz,1920,1080, EDID_STD_RATIO_16_9}, +{EDID_STD_1680x1050_60Hz,1680,1050, EDID_STD_RATIO_16_10}, +{EDID_STD_1600x1200_60Hz,1600,1200, EDID_STD_RATIO_4_3}, +{EDID_STD_1600x900_60Hz, 1600, 900, EDID_STD_RATIO_16_9}, +{EDID_STD_1440x900_60Hz, 1440, 900, EDID_STD_RATIO_16_10}, +{EDID_STD_1280x1024_60Hz,1280,1024, EDID_STD_RATIO_5_4}, +{EDID_STD_1280x960_60Hz, 1280, 960, EDID_STD_RATIO_4_3}, +{EDID_STD_1152x864_70Hz, 1152, 864, EDID_STD_RATIO_4_3}, +{EDID_STD_1024x768_85Hz, 1024, 768, EDID_STD_RATIO_4_3}, +{EDID_STD_800x600_85Hz, 800, 600, EDID_STD_RATIO_4_3}, +{EDID_STD_640x480_85Hz, 640, 480, EDID_STD_RATIO_4_3} +}; + struct edid_detailed_timing edid_dtd_1280x1024 VAR16 = { 0x2a30, 0x00, 0x98, 0x51, 0x00, 0x2A, 0x40, 0x30, 0x70, 0x13, 0x00, 0x2C, 0xE1, 0x10, @@ -47,6 +67,22 @@ struct edid_monitor_range_limit edid_range_limit VAR16 = { 0x20,0x20 /* padding */ }; +u16 max_xres VAR16, max_yres VAR16; + +void bochs_validate_edid_resolutions(u16 xres, u16 yres) { + struct bochs_edid_mode *m = bochs_edid_modes; + for (; m < &bochs_edid_modes[ARRAY_SIZE(bochs_edid_modes)]; m++){ + u16 width = GET_GLOBAL(m->width); + u16 height = GET_GLOBAL(m->height); + if (width > xres || height > yres) { + dprintf(1, "Removing edid mode %x\n", GET_GLOBAL(m->mode)); + SET_VGA(m->mode, EDID_STD_NOP); + } + } + SET_VGA(max_xres, xres); + SET_VGA(max_yres, yres); +} + int bochs_read_edid_block0(u16 unit, u16 block, u16 seg, void *data, u8 next) { struct edid_info *info = data; @@ -90,18 +126,33 @@ int bochs_read_edid_block0(u16 unit, u16 block, u16 seg, void *data, u8 next) /* 720x400@70Hz, 720x400@88Hz, 640x480@60Hz, 640x480@67Hz, 640x480@72Hz, 640x480@75Hz, 800x600@56Hz, 800x600@60Hz, 800x600@72Hz, 800x600@75Hz, 832x624@75Hz, 1152x870@75Hz, not 1024x768@87Hz(I), 1024x768@60Hz, 1024x768@70Hz, 1024x768@75Hz, 1280x1024@75Hz */ + /* standard timings */ - SET_FARVAR(seg, info->standard_timing[0], EDID_STD_640x480_85Hz); - SET_FARVAR(seg, info->standard_timing[1], EDID_STD_800x600_85Hz); - SET_FARVAR(seg, info->standard_timing[2], EDID_STD_1024x768_85Hz); - SET_FARVAR(seg, info->standard_timing[3], EDID_STD_1280x720_70Hz); - SET_FARVAR(seg, info->standard_timing[4], EDID_STD_1280x960_60Hz); - SET_FARVAR(seg, info->standard_timing[5], EDID_STD_1440x900_60Hz); - SET_FARVAR(seg, info->standard_timing[6], EDID_STD_1600x1200_60Hz); - SET_FARVAR(seg, info->standard_timing[7], EDID_STD_NOP); - /* detailed timing blocks */ - memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1600x1200, - sizeof (edid_dtd_1600x1200)); + struct bochs_edid_mode *m = bochs_edid_modes; + for (i = 0; (i < 8) && (m < &bochs_edid_modes[ARRAY_SIZE(bochs_edid_modes)]); m++){ + if (GET_GLOBAL(m->mode) != EDID_STD_NOP) { + SET_FARVAR(seg, info->standard_timing[i], GET_GLOBAL(m->mode)); + i++; + } + } + for (; i < 8; i++) { /* if rest, fill with NOP */ + SET_FARVAR(seg, info->standard_timing[i], EDID_STD_NOP); + } + /* detailed timing block */ + /* select one that is largest and lower than max_xres */ + if (GET_GLOBAL(max_xres) < 1280) { + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1152x864, + sizeof (struct edid_detailed_timing)); + } else if (GET_GLOBAL(max_xres) < 1600) { + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1280x1024, + sizeof (struct edid_detailed_timing)); + } else if (GET_GLOBAL(max_xres) >= 1600 && GET_GLOBAL(max_xres) < 1920) { + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1600x1200, + sizeof (struct edid_detailed_timing)); + } else { + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1920x1200, + sizeof (struct edid_detailed_timing)); + } /* monitor range */ memcpy_far(seg, &(info->desc[1].mrld), get_global_seg(), &edid_range_limit, sizeof(edid_range_limit)); @@ -145,3 +196,4 @@ int bochs_read_edid(u16 unit, u16 block, u16 seg, void *data) return -1; } } + diff --git a/vgasrc/bochsedid.h b/vgasrc/bochsedid.h index 0f925df..8f82316 100644 --- a/vgasrc/bochsedid.h +++ b/vgasrc/bochsedid.h @@ -131,6 +131,12 @@ struct edid_info { #define EDID_STD_1920x1200_60Hz 0x00D1 #define EDID_STD_NOP 0x0101 +#define EDID_STD_RATIO_16_10 (1) +#define EDID_STD_RATIO_4_3 (1 << 1) +#define EDID_STD_RATIO_5_4 (1 << 2) +#define EDID_STD_RATIO_16_9 (1 << 3) + +void bochs_validate_edid_resolutions(u16 xres, u16 yres); int bochs_get_ddc_capabilities(u16 unit); int bochs_read_edid(u16 unit, u16 block, u16 seg, void *data); #endif /* bochedid.h */ diff --git a/vgasrc/bochsvga.c b/vgasrc/bochsvga.c index 2a8aeb1..9fcbdae 100644 --- a/vgasrc/bochsvga.c +++ b/vgasrc/bochsvga.c @@ -369,12 +369,14 @@ bochsvga_init(void) dprintf(1, "VBE DISPI: lfb_addr=%x, size %d MB\n", lfb_addr, totalmem >> 20); - // Validate modes + // Validate modes and edid resolutions u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE); dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS); u16 max_xres = dispi_read(VBE_DISPI_INDEX_XRES); + u16 max_yres = dispi_read(VBE_DISPI_INDEX_YRES); u16 max_bpp = dispi_read(VBE_DISPI_INDEX_BPP); dispi_write(VBE_DISPI_INDEX_ENABLE, en); + /* modes */ struct bochsvga_mode *m = bochsvga_modes; for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++) { u16 width = GET_GLOBAL(m->info.width); @@ -388,6 +390,8 @@ bochsvga_init(void) SET_VGA(m->mode, 0xffff); } } + /* edid resolutions */ + bochs_validate_edid_resolutions(max_xres, max_yres); return 0; } -- 1.7.9.5

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[PATCH 0/3] EDID support for vgabios (take3)
by Hiroshi Miura 16 Sep '12

16 Sep '12

Rework of EDID support in bochs vgabios (take3) Now remove selection of preferred mode. There only validate modes against MAX_XRES, YRES as same as bochsvga_init doing. Hiroshi Miura (3): vgasrc: Add skeleton for VBE function 15h (VBE/DDC Standard) bochsvga: Implement vbe 15h function bochsvga: validate EDID resolution in init Makefile | 3 +- src/vbe.h | 5 ++ vgasrc/bochsedid.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/bochsedid.h | 142 +++++++++++++++++++++++++++++++++++++ vgasrc/bochsvga.c | 6 +- vgasrc/stdvga.c | 11 +++ vgasrc/stdvga.h | 2 + vgasrc/vbe.c | 34 +++++++++ vgasrc/vgahw.h | 13 ++++ 9 files changed, 413 insertions(+), 2 deletions(-) create mode 100644 vgasrc/bochsedid.c create mode 100644 vgasrc/bochsedid.h -- 1.7.9.5

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Geode register functions
by Kevin O'Connor 15 Sep '12

15 Sep '12

Hi Christian, It would be nice if the geode code could use the same style register access functions that the stdvga code uses. I put together a patch (totally untested) below. Is this okay? -Kevin >From f47461f455207b7384bb828831a084bd7811f19e Mon Sep 17 00:00:00 2001 Message-Id: <f47461f455207b7384bb828831a084bd7811f19e.1346690012.git.kevin(a)koconnor.net> In-Reply-To: <cover.1346690012.git.kevin(a)koconnor.net> References: <cover.1346690012.git.kevin(a)koconnor.net> From: Kevin O'Connor <kevin(a)koconnor.net> Date: Mon, 3 Sep 2012 12:32:01 -0400 Subject: [PATCH] Geode vga: Use standard format read/write_mask register functions. To: seabios(a)seabios.org Rework the Geode code to use the same style register accessors as the standard vga code. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/geodevga.c | 116 +++++++++++++++++++++++++++++------------------------- 1 file changed, 62 insertions(+), 54 deletions(-) diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c index 35382d5..ed41be6 100644 --- a/vgasrc/geodevga.c +++ b/vgasrc/geodevga.c @@ -20,7 +20,7 @@ * MSR and High Mem access through VSA Virtual Register ****************************************************************/ -static union u64_u32_u geode_msrRead(u32 msrAddr) +static u64 geode_msr_read(u32 msrAddr) { union u64_u32_u val; asm __volatile__ ( @@ -33,11 +33,14 @@ static union u64_u32_u geode_msrRead(u32 msrAddr) : "c"(msrAddr) : "cc" ); - return val; + return val.val; } -static void geode_msrWrite(u32 msrAddr,u32 andhi, u32 andlo, u32 orhi, u32 orlo) +static void geode_msr_mask(u32 msrAddr, u64 off, u64 on) { + union u64_u32_u uand, uor; + uand.val = ~off; + uor.val = on; asm __volatile__ ( "push %%eax \n" "movw $0x0AC1C, %%dx \n" @@ -47,12 +50,12 @@ static void geode_msrWrite(u32 msrAddr,u32 andhi, u32 andlo, u32 orhi, u32 orlo) "pop %%eax \n" "outw %%ax, %%dx \n" : - : "c"(msrAddr), "S" (andhi), "D" (andlo), "b" (orhi), "a" (orlo) + : "c"(msrAddr), "S" (uand.hi), "D" (uand.lo), "b" (uor.hi), "a" (uor.lo) : "%edx","cc" ); } -static u32 geode_memRead(u32 addr) +static u32 geode_mem_read(u32 addr) { u32 val; asm __volatile__ ( @@ -69,7 +72,7 @@ static u32 geode_memRead(u32 addr) return val; } -static void geode_memWrite(u32 addr, u32 and, u32 or ) +static void geode_mem_mask(u32 addr, u32 off, u32 or) { asm __volatile__ ( "movw $0x0AC1C, %%dx \n" @@ -78,7 +81,7 @@ static void geode_memWrite(u32 addr, u32 and, u32 or ) "addb $2, %%dl \n" "outw %%ax, %%dx \n" : - : "b"(addr), "S" (and), "D" (or) + : "b"(addr), "S" (~off), "D" (or) : "%eax","cc" ); } @@ -94,50 +97,62 @@ struct geode { }; struct geode geode VAR16; -static u32 read_dc(int reg) +static u32 geode_dc_read(int reg) { - u32 val = geode_memRead(geode.dc + reg); + u32 val = geode_mem_read(geode.dc + reg); dprintf(4, "%s(0x%08x) = 0x%08x\n", __func__, geode.dc + reg, val); return val; } -static u32 read_vp(int reg) +static void geode_dc_write(int reg, u32 val) +{ + dprintf(4, "%s(0x%08x, 0x%08x)\n", __func__, geode.dc + reg, val); + geode_mem_mask(geode.dc + reg, ~0, val); +} + +static void geode_dc_mask(int reg, u32 off, u32 on) { - u32 val = geode_memRead(geode.vp + reg); + dprintf(4, "%s(0x%08x, 0x%08x, 0x%08x)\n", __func__, geode.dc + reg, off, on); + geode_mem_mask(geode.dc + reg, off, on); +} + +static u32 geode_vp_read(int reg) +{ + u32 val = geode_mem_read(geode.vp + reg); dprintf(4, "%s(0x%08x) = 0x%08x\n", __func__, geode.vp + reg, val); return val; } -static void write_dc(int reg, u32 val) +static void geode_vp_write(int reg, u32 val) { - dprintf(4, "%s(0x%08x, 0x%08x)\n", __func__, geode.dc + reg, val); - geode_memWrite(geode.dc + reg, 0x0, val); + dprintf(4, "%s(0x%08x, 0x%08x)\n", __func__, geode.vp + reg, val); + geode_mem_mask(geode.vp + reg, ~0, val); } -static void write_vp(int reg, u32 val) +static void geode_vp_mask(int reg, u32 off, u32 on) { - dprintf(4, "%s(0x%08x, 0x%08x)\n", __func__, geode.vp + reg, val); - geode_memWrite(geode.vp + reg, 0x0, val); + dprintf(4, "%s(0x%08x, 0x%08x, 0x%08x)\n", __func__, geode.vp + reg, off, on); + geode_mem_mask(geode.vp + reg, off, on); } static int legacyio_check(void) { int ret=0; - union u64_u32_u val; + u64 val; if (CONFIG_VGA_GEODEGX2) - val=geode_msrRead(GLIU0_P2D_BM_4); + val = geode_msr_read(GLIU0_P2D_BM_4); else - val=geode_msrRead(MSR_GLIU0_BASE4); - if (val.lo != 0x0A0fffe0) + val = geode_msr_read(MSR_GLIU0_BASE4); + if ((val & 0xffffffff) != 0x0A0fffe0) ret|=1; - val=geode_msrRead(GLIU0_IOD_BM_0); - if (val.lo != 0x3c0ffff0) + val = geode_msr_read(GLIU0_IOD_BM_0); + if ((val & 0xffffffff) != 0x3c0ffff0) ret|=2; - val=geode_msrRead(GLIU0_IOD_BM_1); - if (val.lo != 0x3d0ffff0) + val = geode_msr_read(GLIU0_IOD_BM_1); + if ((val & 0xffffffff) != 0x3d0ffff0) ret|=4; return ret; @@ -145,9 +160,6 @@ static int legacyio_check(void) static u32 framebuffer_size(void) { - u32 val; - union u64_u32_u msr; - /* We use the P2D_R0 msr to read out the number of pages. * One page has a size of 4k * @@ -156,12 +168,12 @@ static u32 framebuffer_size(void) * 19:0 PMIX Physical Memory Address Min * */ - msr = geode_msrRead(GLIU0_P2D_RO); + u64 msr = geode_msr_read(GLIU0_P2D_RO); - u32 pmax = ((msr.hi & 0xff) << 12) | ((msr.lo & 0xfff00000) >> 20); - u32 pmin = (msr.lo & 0x000fffff); - - val = pmax - pmin; + u32 pmax = (msr >> 20) & 0x000fffff; + u32 pmin = msr & 0x000fffff; + + u32 val = pmax - pmin; val += 1; /* The page size is 4k */ @@ -177,27 +189,25 @@ static u32 framebuffer_size(void) */ static void dc_setup(void) { - u32 dc_fb; - dprintf(2, "DC_SETUP\n"); - write_dc(DC_UNLOCK, DC_LOCK_UNLOCK); + geode_dc_write(DC_UNLOCK, DC_LOCK_UNLOCK); /* zero memory config */ - write_dc(DC_FB_ST_OFFSET, 0x0); - write_dc(DC_CB_ST_OFFSET, 0x0); - write_dc(DC_CURS_ST_OFFSET, 0x0); + geode_dc_write(DC_FB_ST_OFFSET, 0x0); + geode_dc_write(DC_CB_ST_OFFSET, 0x0); + geode_dc_write(DC_CURS_ST_OFFSET, 0x0); /* read fb-bar from pci, then point dc to the fb base */ - dc_fb = read_dc(DC_GLIU0_MEM_OFFSET); + u32 dc_fb = geode_dc_read(DC_GLIU0_MEM_OFFSET); if (geode.fb != dc_fb) { - write_dc(DC_GLIU0_MEM_OFFSET, geode.fb); + geode_dc_write(DC_GLIU0_MEM_OFFSET, geode.fb); } - geode_memWrite(geode.dc + DC_DISPLAY_CFG, DC_CFG_MSK, DC_GDEN+DC_TRUP); - write_dc(DC_GENERAL_CFG, DC_VGAE); + geode_dc_mask(DC_DISPLAY_CFG, ~DC_CFG_MSK, DC_GDEN|DC_TRUP); + geode_dc_write(DC_GENERAL_CFG, DC_VGAE); - write_dc(DC_UNLOCK, DC_LOCK_LOCK); + geode_dc_write(DC_UNLOCK, DC_LOCK_LOCK); u32 fb_size = framebuffer_size(); // in byte dprintf(1, "%d KB of video memory at 0x%08x\n", fb_size / 1024, geode.fb); @@ -215,30 +225,28 @@ static void dc_setup(void) */ static void vp_setup(void) { - u32 reg; - dprintf(2,"VP_SETUP\n"); /* set output to crt and RGB/YUV */ if (CONFIG_VGA_GEODEGX2) - geode_msrWrite(VP_MSR_CONFIG_GX2, ~0, ~0xf8, 0, 0); + geode_msr_mask(VP_MSR_CONFIG_GX2, 0xf8, 0); else - geode_msrWrite(VP_MSR_CONFIG_LX, ~0, ~0xf8, 0, 0); + geode_msr_mask(VP_MSR_CONFIG_LX, 0xf8, 0); /* Set mmio registers * there may be some timing issues here, the reads seem * to slow things down enough work reliably */ - reg = read_vp(VP_MISC); + u32 reg = geode_vp_read(VP_MISC); dprintf(1,"VP_SETUP VP_MISC=0x%08x\n",reg); - write_vp(VP_MISC, VP_BYP_BOTH); - reg = read_vp(VP_MISC); + geode_vp_write(VP_MISC, VP_BYP_BOTH); + reg = geode_vp_read(VP_MISC); dprintf(1,"VP_SETUP VP_MISC=0x%08x\n",reg); - reg = read_vp(VP_DCFG); + reg = geode_vp_read(VP_DCFG); dprintf(1,"VP_SETUP VP_DCFG=0x%08x\n",reg); - geode_memWrite(geode.vp + VP_DCFG, ~0,VP_CRT_EN+VP_HSYNC_EN+VP_VSYNC_EN+VP_DAC_BL_EN+VP_CRT_SKEW); - reg = read_vp(VP_DCFG); + geode_vp_mask(VP_DCFG, 0, VP_CRT_EN|VP_HSYNC_EN|VP_VSYNC_EN|VP_DAC_BL_EN|VP_CRT_SKEW); + reg = geode_vp_read(VP_DCFG); dprintf(1,"VP_SETUP VP_DCFG=0x%08x\n",reg); } -- 1.7.11.4

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[PATCH 3/3] bochsvga: dynamic generation of EDID
by Hiroshi Miura 15 Sep '12

15 Sep '12

Generate EDID according to preferred resolution from VBE_DISPI interface. Signed-off-by: Hiroshi Miura <miurahr(a)linux.com> --- vgasrc/bochsedid.c | 54 ++++++++++++++++++++++++++++++++++++++++++---------- vgasrc/bochsedid.h | 1 + vgasrc/bochsvga.c | 2 ++ 3 files changed, 47 insertions(+), 10 deletions(-) diff --git a/vgasrc/bochsedid.c b/vgasrc/bochsedid.c index 5a40593..6bea389 100644 --- a/vgasrc/bochsedid.c +++ b/vgasrc/bochsedid.c @@ -47,6 +47,23 @@ struct edid_monitor_range_limit edid_range_limit VAR16 = { 0x20,0x20 /* padding */ }; +u16 prefered_xres VAR16, prefered_yres VAR16; + +void bochs_init_preferred_resolution(u16 max_xres, u16 max_yres) { + + if (max_xres >= 1920 && max_yres >= 1200){ + max_xres = 1920; max_yres = 1200; + } else if (max_xres >= 1600 && max_yres >= 1200){ + max_xres = 1600; max_yres = 1200; + } else if (max_xres >= 1280 && max_yres >= 1024){ + max_xres = 1280; max_yres = 1024; + } else { + max_xres = 1152; max_yres = 864; + } + SET_VGA(prefered_xres,max_xres); + SET_VGA(prefered_yres,max_yres); +} + int bochs_read_edid_block0(u16 unit, u16 block, u16 seg, void *data, u8 next) { struct edid_info *info = data; @@ -90,18 +107,34 @@ int bochs_read_edid_block0(u16 unit, u16 block, u16 seg, void *data, u8 next) /* 720x400@70Hz, 720x400@88Hz, 640x480@60Hz, 640x480@67Hz, 640x480@72Hz, 640x480@75Hz, 800x600@56Hz, 800x600@60Hz, 800x600@72Hz, 800x600@75Hz, 832x624@75Hz, 1152x870@75Hz, not 1024x768@87Hz(I), 1024x768@60Hz, 1024x768@70Hz, 1024x768@75Hz, 1280x1024@75Hz */ - /* standard timings */ + /* standard timings & detailed timing block */ SET_FARVAR(seg, info->standard_timing[0], EDID_STD_640x480_85Hz); SET_FARVAR(seg, info->standard_timing[1], EDID_STD_800x600_85Hz); - SET_FARVAR(seg, info->standard_timing[2], EDID_STD_1024x768_85Hz); - SET_FARVAR(seg, info->standard_timing[3], EDID_STD_1280x720_70Hz); - SET_FARVAR(seg, info->standard_timing[4], EDID_STD_1280x960_60Hz); - SET_FARVAR(seg, info->standard_timing[5], EDID_STD_1440x900_60Hz); - SET_FARVAR(seg, info->standard_timing[6], EDID_STD_1600x1200_60Hz); - SET_FARVAR(seg, info->standard_timing[7], EDID_STD_NOP); - /* detailed timing blocks */ - memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1600x1200, - sizeof (edid_dtd_1600x1200)); + if (GET_GLOBAL(prefered_xres) < 1280) { + SET_FARVAR(seg, info->standard_timing[2], EDID_STD_1024x768_85Hz); + SET_FARVAR(seg, info->standard_timing[3], EDID_STD_1152x864_70Hz); + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1152x864, + sizeof (struct edid_detailed_timing)); + } else if (GET_GLOBAL(prefered_xres) < 1600) { + SET_FARVAR(seg, info->standard_timing[2], EDID_STD_1024x768_85Hz); + SET_FARVAR(seg, info->standard_timing[3], EDID_STD_1280x1024_60Hz); + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1280x1024, + sizeof (struct edid_detailed_timing)); + } else if (GET_GLOBAL(prefered_xres) >= 1600 && GET_GLOBAL(prefered_xres) < 1920) { + SET_FARVAR(seg, info->standard_timing[2], EDID_STD_1440x900_60Hz); + SET_FARVAR(seg, info->standard_timing[3], EDID_STD_1600x1200_60Hz); + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1600x1200, + sizeof (struct edid_detailed_timing)); + } else { + SET_FARVAR(seg, info->standard_timing[2], EDID_STD_1440x900_60Hz); + SET_FARVAR(seg, info->standard_timing[3], EDID_STD_1920x1200_60Hz); + memcpy_far(seg, &(info->desc[0].dtd), get_global_seg(), &edid_dtd_1920x1200, + sizeof (struct edid_detailed_timing)); + } + for (i = 4; i < 8; i++) { /* FILL with NOP */ + SET_FARVAR(seg, info->standard_timing[i], EDID_STD_NOP); + } + /* detailed timing block here has already set with standard timings */ /* monitor range */ memcpy_far(seg, &(info->desc[1].mrld), get_global_seg(), &edid_range_limit, sizeof(edid_range_limit)); @@ -145,3 +178,4 @@ int bochs_read_edid(u16 unit, u16 block, u16 seg, void *data) return -1; } } + diff --git a/vgasrc/bochsedid.h b/vgasrc/bochsedid.h index 0f925df..be60f9f 100644 --- a/vgasrc/bochsedid.h +++ b/vgasrc/bochsedid.h @@ -131,6 +131,7 @@ struct edid_info { #define EDID_STD_1920x1200_60Hz 0x00D1 #define EDID_STD_NOP 0x0101 +void bochs_init_preferred_resolution(u16 max_xres, u16 max_yres); int bochs_get_ddc_capabilities(u16 unit); int bochs_read_edid(u16 unit, u16 block, u16 seg, void *data); #endif /* bochedid.h */ diff --git a/vgasrc/bochsvga.c b/vgasrc/bochsvga.c index 2a8aeb1..72240c3 100644 --- a/vgasrc/bochsvga.c +++ b/vgasrc/bochsvga.c @@ -373,6 +373,7 @@ bochsvga_init(void) u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE); dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS); u16 max_xres = dispi_read(VBE_DISPI_INDEX_XRES); + u16 max_yres = dispi_read(VBE_DISPI_INDEX_YRES); u16 max_bpp = dispi_read(VBE_DISPI_INDEX_BPP); dispi_write(VBE_DISPI_INDEX_ENABLE, en); struct bochsvga_mode *m = bochsvga_modes; @@ -388,6 +389,7 @@ bochsvga_init(void) SET_VGA(m->mode, 0xffff); } } + bochs_init_preferred_resolution(max_xres, max_yres); return 0; } -- 1.7.9.5

2 4

Re: [SeaBIOS] [PATCH 0/9] q35 seabios support take #1
by Paolo Bonzini 14 Sep '12

14 Sep '12

Il 13/09/2012 22:12, Jason Baron ha scritto: > Subject: [PATCH 0/9] q35 seabios support take #1 > > Hi, > > Seabios bits for q35 support, I'm posting the qemu changes separately. The > patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the > qemu command line. Hopefully, we can make it the default for x86 at some future > point when we feel comfortable with it. The main question, IMHO, is how to proceed for supporting both PIIX4 and q35. The two extreme possibilities are: - use a single binary for everything - use two binaries for everything Right now, you do a mix of the two, where you have two DSDTs and one binary. Furthermore, PIIX4 is still a "preferred" chipset in that its DSDT is embedded in SeaBIOS and q35's isn't. With more than one chipset being supported, and with the desire to support OVMF/UEFI as an alternative firmware, I think it makes sense to move QEMU towards a model more similar to CoreBoot's, where QEMU itself makes the default ACPI tables and passes them to SeaBIOS or OVMF via fw_cfg. So my favorite choice is to move the DSDT to fw_cfg, and keep a single binary for everything else. I don't really care whether the DSDT sources live in the SeaBIOS or QEMU repository, though the former makes more sense until all things ACPI are done in QEMU. Paolo

2 2

Re: [SeaBIOS] (no subject)
by Gerd Hoffmann 14 Sep '12

14 Sep '12

On 09/13/12 22:12, Jason Baron wrote: > jan.kiszka(a)siemens.com, juzhang(a)redhat.com, agraf(a)suse.de, yamahata(a)valinux.co.jp, mkletzan(a)redhat.com, afaerber(a)suse.de, armbru(a)redhat.com, lcapitulino(a)redhat.com, alex.williamson(a)redhat.com > Message-Id: <491ff0e77a2359c098540aa24fbbfeec573bea91.1347565443.git.jbaron(a)redhat.com> > In-Reply-To: <cover.1347565443.git.jbaron(a)redhat.com> > References: <cover.1347565443.git.jbaron(a)redhat.com> > Subject: [PATCH 9/9] seabios: q35: add basic hotplug support > > Add support for acpi hotplug to q35. Copied from the piix acpi table. Do we really wanna bring that in? q35 has pcie slots which are hot-pluggable. qemu also has a pci-pci bridge which supports hotplug for all devices behind it. It's not like we can't hotplug pci devices at all like it used to be back in the days when acpi hotplug was added to piix4. cheers, Gerd

2 1

Unable to compile under NetBSD with gcc 4.1.3
by Roger Pau Monne 14 Sep '12

14 Sep '12

Hello, I'm trying to compile SeaBIOS under NetBSD 5.1.2, that comes with gcc 4.1.3, and I'm getting the following error (I'm pasting the whole build log, since it's not really long, and may help in debugging): Working around non-functional -fwhole-program Build Kconfig config file Compiling IASL out/acpi-dsdt.hex ASL Input: out/acpi-dsdt.dsl.i - 621 lines, 22543 bytes, 334 keywords AML Output: out/acpi-dsdt.aml - 4585 bytes, 156 named objects, 178 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 257 Optimizations Compiling IASL out/ssdt-proc.hex ASL Input: out/ssdt-proc.dsl.i - 36 lines, 765 bytes, 8 keywords AML Output: out/ssdt-proc.aml - 120 bytes, 6 named objects, 2 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations Compiling IASL out/ssdt-pcihp.hex ASL Input: out/ssdt-pcihp.dsl.i - 52 lines, 755 bytes, 6 keywords AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations Compiling IASL out/ssdt-susp.hex ASL Input: out/ssdt-susp.dsl.i - 53 lines, 690 bytes, 4 keywords AML Output: out/ssdt-susp.aml - 78 bytes, 4 named objects, 0 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations Compiling whole program out/ccode32flat.o Compiling whole program out/code32seg.o Compiling whole program out/ccode16.o Compiling to assembler out/asm-offsets.s Generating offset file out/asm-offsets.h Compiling (16bit) out/romlayout.o Building ld scripts Version: rel-1.7.1-25-g455a7c8-20120914_095529-.uk.xensource.com Fixed space: 0xe05b-0x10000 total: 8101 slack: 5 Percent slack: 0.1% 16bit size: 55072 32bit segmented size: 2118 32bit flat size: 19418 32bit flat init size: 61824 Lowmem size: 2176 Linking out/rom16.o Stripping out/rom16.strip.o Linking out/rom32seg.o Stripping out/rom32seg.strip.o Linking out/rom.o out/romlayout32flat.lds:2042: undefined symbol `code32flat_start' referenced in expression gmake: *** [out/rom.o] Error 1 This error only happens when compiling with gcc 4.1.3, with gcc 4.5.3 (under NetBSD also) the build process is successful. Since I guess it's a compiler problem, is there anyway I can workaround this issue? Thanks, Roger.

2 2

Re: [SeaBIOS] (no subject)
by Gerd Hoffmann 14 Sep '12

14 Sep '12

On 09/13/12 22:12, Jason Baron wrote: > add dsdt for q35 chipset of qemu. Not used anywhere. We probaby want build it into the seabios binary so we don't depend on qemu passing it to us. Or we just make qemu pass the dsdt to seabios unconditionally. Not sure if that is possible given the dsdt patching we do. Guess we want CONFIG_QEMU_PIIX and CONFIG_QEMU_Q35 to build the two bios variants[1]. Or include both acpi tables, then select at runtime. cheers, Gerd [1] And while being at it also CONFIG_QEMU so we can replace the slightly irritating "if (!CONFIG_COREBOOT)" with "if (CONFIG_QEMU)"

2 1

Re: [SeaBIOS] (no subject)
by Gerd Hoffmann 14 Sep '12

14 Sep '12

On 09/13/12 22:12, Jason Baron wrote: > jan.kiszka(a)siemens.com, juzhang(a)redhat.com, agraf(a)suse.de, yamahata(a)valinux.co.jp, mkletzan(a)redhat.com, afaerber(a)suse.de, armbru(a)redhat.com, lcapitulino(a)redhat.com, alex.williamson(a)redhat.com > Message-Id: <e9be57cd1e9aba8c97fc1518055a05e28533904c.1347565443.git.jbaron(a)redhat.com> > In-Reply-To: <cover.1347565443.git.jbaron(a)redhat.com> > References: <cover.1347565443.git.jbaron(a)redhat.com> > Subject: [PATCH 2/9] seabios: pciinit: initialize pcimem_start and pcimem_end depending on chipset. > > From: Isaku Yamahata <yamahata(a)valinux.co.jp> > > initialize pcimem_start and pcimem_end based on chipset. Should not be needed. There is no hard-coded range any more. PCI address space starts above lowmem (see pcimem_start assignment in pci_bios_map_devices()). Probably the q35 dsdt table must be updated to handle this (see \_SB.PCI0._CRS). Probably you also want to grab some address space for mmconfig, i.e. place mmconfig above lowmem and set pcimem_start to the end of mmconfig space. cheers, Gerd

1 0

(no subject)
by Jason Baron 13 Sep '12

13 Sep '12

jan.kiszka(a)siemens.com, juzhang(a)redhat.com, agraf(a)suse.de, yamahata(a)valinux.co.jp, mkletzan(a)redhat.com, afaerber(a)suse.de, armbru(a)redhat.com, lcapitulino(a)redhat.com, alex.williamson(a)redhat.com Message-Id: <491ff0e77a2359c098540aa24fbbfeec573bea91.1347565443.git.jbaron(a)redhat.com> In-Reply-To: <cover.1347565443.git.jbaron(a)redhat.com> References: <cover.1347565443.git.jbaron(a)redhat.com> Subject: [PATCH 9/9] seabios: q35: add basic hotplug support Add support for acpi hotplug to q35. Copied from the piix acpi table. Signed-off-by: Jason Baron <jbaron(a)redhat.com> --- src/q35-acpi-dsdt.dsl | 61 +++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 56 insertions(+), 5 deletions(-) diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl index 3180624..a6cca0e 100644 --- a/src/q35-acpi-dsdt.dsl +++ b/src/q35-acpi-dsdt.dsl @@ -83,6 +83,21 @@ DefinitionBlock ( Name (_ADR, 0x00) Name (_UID, 1) + + OperationRegion(PCST, SystemIO, 0xae00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32, + } + + OperationRegion(SEJ, SystemIO, 0xae08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32, + } + + // _OSC: based on sample of ACPI3.0b spec Name(SUPP,0) // PCI _OSC Support Field value Name(CTRL,0) // PCI _OSC Control Field value @@ -812,6 +827,41 @@ DefinitionBlock ( } } +/**************************************************************** + * PCI hotplug + ****************************************************************/ + + Scope(\_SB.PCI0) { + /* Methods called by bulk generated PCI devices below */ + + /* Methods called by hotplug devices */ + Method (PCEJ, 1, NotSerialized) { + // _EJ0 method - eject callback + Store(ShiftLeft(1, Arg0), B0EJ) + Return (0x0) + } + + /* Hotplug notification method supplied by SSDT */ + External (\_SB.PCI0.PCNT, MethodObj) + + /* PCI hotplug notify method */ + Method(PCNF, 0) { + // Local0 = iterator + Store (Zero, Local0) + While (LLess(Local0, 31)) { + Increment(Local0) + If (And(PCIU, ShiftLeft(1, Local0))) { + PCNT(Local0, 1) + } + If (And(PCID, ShiftLeft(1, Local0))) { + PCNT(Local0, 3) + } + } + Return(One) + } + + } + Scope (\_GPE) { Name(_HID, "ACPI0006") @@ -819,12 +869,13 @@ DefinitionBlock ( Method(_L00) { Return(0x01) } - Method(_L01) { - // CPU hotplug event - Return(\_SB.PRSC()) + Method(_E01) { + // PCI hotplug event + Return(\_SB.PCI0.PCNF()) } - Method(_L02) { - Return(0x01) + Method(_E02) { + // CPU hotplug event + Return(\_SB.PRSC()) } Method(_L03) { Return(0x01) -- 1.7.1

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SeaBIOS September 2012