November 2012 - SeaBIOS - mail.coreboot.org

by dunedain1990

Hi, I'm using seaBIOS 1.7.1 in a BOCHS 2.6. I'm loading my own SO from USB but it crashes. My bochsout after select the boot option: 18279385688iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> Space available for UMB: 000ca800-000ef000 18279411495iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> Returned 53248 bytes of ZoneHigh 18279411930iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> e820 map has 6 items: 18279413017iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> 0: 0000000000000000 - 000000000009fc00 = 1 RAM 18279414210iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 18279415416iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 18279416584iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> 3: 0000000000100000 - 000000001fffd000 = 1 RAM 18279417834iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> 4: 000000001fffd000 - 0000000020000000 = 2 RESERVED 18279419084iBIOS <http://sourceforge.net/p/bochs/discussion/39592/thread/BIOS> 5: 00000000fffc0000 - 0000000100000000 = 2 RESERVED When i see this error i ask in bochs mailing list and they reply me: SeaBIOS seems to have a problem with your small image. It detects the logical geometry 0/16/63 which is invalid, since a disk cannot have 0 cylinders.The only way to fix this is to increase the image size to minimum 1.44 MB (2880 sectors). This is a value that works here. Is there any solution for not increase the image size of my img?

6 years, 12 months

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Issues on initialization of PCI devices below root.

by lautriv

Hello, i tried to get seabios up via payload from coreboot and failed on the initialisation of neccessary devices. The board in Question is a Tyan S4882, consisting of K8 northbridge, 8131 southbridge, 8111 southbridge and Winbond w83627hf SuperIO. You will see on the following pastebin-url that coreboot does a proper init and can see all relevant devices. I was also able to get VGA up via coreboot ( to reflect an accessible device below root ) but not from within seabios. It probes only against PCI 00:18.0 ... 00:18.3 which are on the northbridge itself. I had a look on the sources and found it should see and init the whole tree, also checked my sources against some patches i found on the net and they are all applied or superseded. the seabios was 1.7.1 and master from git The relevant startup can be found here : http://pastebin.com/wZvRWm1Z feel free to send me something to test out if there are unanswered questions or contact me in #coreboot on freenode's IRC. I'm not omnipresent but 8-12AM and 9-12PM CET should be fine ;) Best regards, lautriv.

6 years, 12 months

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Building & running coreboot & seabios

by Shraddha Kamat

I am looking for a document on building & running coreboot seabios to work with qemu-kvm. Do we have such documents for newbies ? -- Shraddha

7 years

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[PATCH 00/11] q35: acpi bits

by Gerd Hoffmann

Hi, This series adds the q35 acpi bits (as is, first two patches), then goes cleanup stuff my subsequently moving reusable stuff to separate include files and make both piix and q35 include them. Kept fine-gained splitted for now so it is easy to reorder/squash stuff for merge. Unsolved issues: ISA devices. See patch #11 for an idea how to tackle this, I don't like it that much though. /me is open for better ideas. VGA. It's in slot 2 for piix and slot 1 for q35. So the current q35 dsdt is simply plain wrong as it declares the vga for slot 2. Is there some way to deal with that in AML code? Note: That this isn't q35 specific issue. Recent qemu versions allow to place the vga in any slot (try "qemu -vga none -device VGA,addr=0a.0"). Comments & Reviews are welcome. cheers, Gerd Gerd Hoffmann (9): acpi: move DBUG() to separate file acpi: move DBUG() to separate file [q35] acpi: move \_SB.HPET to separate file acpi: move \_SB.HPET to separate file [q35] acpi: move \_SB.PCI0._CRS to separate file acpi: move \_SB.PCI0._CRS to separate file [q35] acpi: move cpu hotplug to separate file acpi: move cpu hotplug to separate file [q35] [RfC] acpi: rework enable bits Isaku Yamahata (1): seabios: q35: add dsdt Jan Kiszka (1): seabios: q35: Register PCI IRQs as active high in APIC mode Makefile | 2 +- src/acpi-dsdt-cpu-hotplug.dsl | 78 +++++ src/acpi-dsdt-dbug.dsl | 30 ++ src/acpi-dsdt-hpet.dsl | 36 ++ src/acpi-dsdt-pci-crs.dsl | 104 ++++++ src/acpi-dsdt.dsl | 344 ++++---------------- src/q35-acpi-dsdt.dsl | 717 +++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1023 insertions(+), 288 deletions(-) create mode 100644 src/acpi-dsdt-cpu-hotplug.dsl create mode 100644 src/acpi-dsdt-dbug.dsl create mode 100644 src/acpi-dsdt-hpet.dsl create mode 100644 src/acpi-dsdt-pci-crs.dsl create mode 100644 src/q35-acpi-dsdt.dsl

7 years

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[PATCH 0/4] misc fixes

by Gerd Hoffmann

Hi, These patches are mostly cherry-picked from Jason's q35 patch series. It carries some bugfixes and preparations for the q35 chipset support, but not yet the q35 code itself. Should be ready for merge. cheers, Gerd Gerd Hoffmann (1): piix: fix mtrr setup Isaku Yamahata (2): seabios: acpi, fadt: make while fadt initialization chipset specific seabios: pci: enable SERR of normal device. Jason Baron (1): seabios: make mttr UC area setup dynamic src/acpi.c | 34 ++++++++++++++++++---------------- src/config.h | 1 - src/mtrr.c | 5 +++-- src/pci.h | 1 + src/pciinit.c | 24 +++++++++++++++++++++++- src/post.c | 6 +++--- 6 files changed, 48 insertions(+), 23 deletions(-)

7 years

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[PATCH] Collapse PCI device tables in pci_bios_init_devices().

by Kevin O'Connor

Use just one "struct pci_device_id" device table list in the pci_bios_init_devices initialization code instead of three separate tables. There isn't any compelling reason to use multiple tables. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/pciinit.c | 68 ++++++++++++++++++++++++----------------------------------- 1 file changed, 27 insertions(+), 41 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index 31115ee..d61f0a8 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -119,16 +119,6 @@ static void piix_isa_bridge_init(struct pci_device *pci, void *arg) dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]); } -static const struct pci_device_id pci_isa_bridge_tbl[] = { - /* PIIX3/PIIX4 PCI to ISA bridge */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, - piix_isa_bridge_init), - PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, - piix_isa_bridge_init), - - PCI_DEVICE_END -}; - static void storage_ide_init(struct pci_device *pci, void *arg) { /* IDE: we map it as in ISA mode */ @@ -158,28 +148,6 @@ static void apple_macio_init(struct pci_device *pci, void *arg) pci_set_io_region_addr(pci, 0, 0x80800000, 0); } -static const struct pci_device_id pci_class_tbl[] = { - /* STORAGE IDE */ - PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, - PCI_CLASS_STORAGE_IDE, piix_ide_init), - PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, - PCI_CLASS_STORAGE_IDE, piix_ide_init), - PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - storage_ide_init), - - /* PIC, IBM, MIPC & MPIC2 */ - PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC, - pic_ibm_init), - PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC, - pic_ibm_init), - - /* 0xff00 */ - PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init), - PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init), - - PCI_DEVICE_END, -}; - /* PM Timer ticks per second (HZ) */ #define PM_TIMER_FREQUENCY 3579545 @@ -199,10 +167,34 @@ static void piix4_pm_init(struct pci_device *pci, void *arg) } static const struct pci_device_id pci_device_tbl[] = { + /* PIIX3/PIIX4 PCI to ISA bridge */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, + piix_isa_bridge_init), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + piix_isa_bridge_init), + + /* STORAGE IDE */ + PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, + PCI_CLASS_STORAGE_IDE, piix_ide_init), + PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, + PCI_CLASS_STORAGE_IDE, piix_ide_init), + PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + storage_ide_init), + + /* PIC, IBM, MIPC & MPIC2 */ + PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC, + pic_ibm_init), + PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC, + pic_ibm_init), + /* PIIX4 Power Management device (for ACPI) */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, piix4_pm_init), + /* 0xff00 */ + PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init), + PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init), + PCI_DEVICE_END, }; @@ -213,17 +205,15 @@ static void pci_bios_init_device(struct pci_device *pci) , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf) , pci->vendor, pci->device); - pci_init_device(pci_class_tbl, pci, NULL); - - /* enable memory mappings */ - pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); - /* map the interrupt */ int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN); if (pin != 0) pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin)); pci_init_device(pci_device_tbl, pci, NULL); + + /* enable memory mappings */ + pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); } static void pci_bios_init_devices(void) @@ -232,10 +222,6 @@ static void pci_bios_init_devices(void) foreachpci(pci) { pci_bios_init_device(pci); } - - foreachpci(pci) { - pci_init_device(pci_isa_bridge_tbl, pci, NULL); - } } -- 1.7.11.7

7 years

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[PATCH seabios] lsi: enable busmaster

by Gerd Hoffmann

The HBA does DMA, thus we must enable the busmaster bit, otherwise dma access will fail with recent qemu versions. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/lsi-scsi.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/lsi-scsi.c b/src/lsi-scsi.c index b70b3a5..f8d715b 100644 --- a/src/lsi-scsi.c +++ b/src/lsi-scsi.c @@ -177,6 +177,8 @@ init_lsi_scsi(struct pci_device *pci) u32 iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0) & PCI_BASE_ADDRESS_IO_MASK; + pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_MASTER); + dprintf(1, "found lsi53c895a at %02x:%02x.%x, io @ %x\n", pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf), iobase); -- 1.7.1

7 years

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Re: [SeaBIOS] [Qemu-devel] [BUG] qemu crash when using "lsilogic"

by Avi Kivity

On 11/20/2012 11:01 AM, Wanlong Gao wrote: >> $ git bisect good >> d22b096ef6e0b20810193b68a1d472f3fb8a4f9e is the first bad commit >> commit d22b096ef6e0b20810193b68a1d472f3fb8a4f9e >> Author: Avi Kivity <avi(a)redhat.com> >> Date: Sun Sep 30 22:21:11 2012 +0200 >> >> kvm: use separate MemoryListeners for memory and I/O >> >> The construct >> >> if (address_space == get_system_memory()) { >> // memory thing >> } else { >> // io thing >> } >> >> fails if we have more than two address spaces. Use a separate listener >> for memory and I/O, and utilize MemoryListener's address space filtering to >> fix this. >> >> Signed-off-by: Avi Kivity <avi(a)redhat.com> >> >> :100644 100644 92a71374ed1e040cef5ad70a6cb00adabf671dd4 c69e01200461c7a87440f7a915bd171a9fc8f318 M kvm-all.c >> >> >> Ooooops, I didn't find any error in above patch, can you guys help to investigate this bug? > > I confirmed again and found that "lsi" can't work on the upstream qemu. > Any thoughts? > I appears to be a bug in Seabios: (gdb) thread 3 [Switching to thread 3 (Thread 0x7fffebfff700 (LWP 19032))] #0 0x000055555586df2c in access_with_adjusted_size (addr=29563620, value=0x7fffebffe5f0, size=4, access_size_min=0, access_size_max=0, access= 0x55555586ddbb <memory_region_read_accessor>, opaque=0x55555655dd00) at /home/tlv/akivity/qemu/memory.c:349 349 { (gdb) bt #0 0x000055555586df2c in access_with_adjusted_size (addr=29563620, value=0x7fffebffe5f0, size=4, access_size_min=0, access_size_max=0, access= 0x55555586ddbb <memory_region_read_accessor>, opaque=0x55555655dd00) at /home/tlv/akivity/qemu/memory.c:349 #1 0x0000555555870a4e in memory_region_dispatch_read1 (mr=0x55555655dd00, addr=29563620, size=4) at /home/tlv/akivity/qemu/memory.c:862 #2 0x0000555555870b3e in memory_region_dispatch_read (mr=0x55555655dd00, addr=29563620, size=4) at /home/tlv/akivity/qemu/memory.c:894 #3 0x0000555555873c2d in io_mem_read (mr=0x55555655dd00, addr=29563620, size=4) at /home/tlv/akivity/qemu/memory.c:1575 #4 0x00005555558054ed in address_space_rw (as=0x555556629d78, addr=29563620, buf=0x7fffebffe874 "", len=4, is_write=false) at /home/tlv/akivity/qemu/exec.c:3428 #5 0x00005555556bf4c3 in dma_memory_rw_relaxed (dma=0x555556603cf0, addr=29563620, buf=0x7fffebffe874, len=4, dir=DMA_DIRECTION_TO_DEVICE) at /home/tlv/akivity/qemu/dma.h:130 #6 0x00005555556bf558 in dma_memory_rw (dma=0x555556603cf0, addr=29563620, buf=0x7fffebffe874, len=4, dir=DMA_DIRECTION_TO_DEVICE) at /home/tlv/akivity/qemu/dma.h:156 #7 0x00005555556bf5fb in pci_dma_rw (dev=0x555556629b60, addr=29563620, buf=0x7fffebffe874, len=4, dir=DMA_DIRECTION_TO_DEVICE) at /home/tlv/akivity/qemu/hw/pci.h:607 #8 0x00005555556bf65b in pci_dma_read (dev=0x555556629b60, addr=29563620, buf=0x7fffebffe874, len=4) at /home/tlv/akivity/qemu/hw/pci.h:614 #9 0x00005555556bfc08 in read_dword (s=0x555556629b60, addr=29563620) at /home/tlv/akivity/qemu/hw/lsi53c895a.c:385 #10 0x00005555556c1937 in lsi_execute_script (s=0x555556629b60) at /home/tlv/akivity/qemu/hw/lsi53c895a.c:1040 #11 0x00005555556c3c82 in lsi_reg_writeb (s=0x555556629b60, offset=47, val=0 '\000') at /home/tlv/akivity/qemu/hw/lsi53c895a.c:1781 #12 0x00005555556c513c in lsi_io_write (opaque=0x555556629b60, addr=47, val=0, size=1) at /home/tlv/akivity/qemu/hw/lsi53c895a.c:1953 #13 0x000055555586def2 in memory_region_write_accessor (opaque=0x55555662a340, addr=47, value=0x7fffebffeab0, size=1, shift=0, mask=255) at /home/tlv/akivity/qemu/memory.c:334 #14 0x000055555586dfd4 in access_with_adjusted_size (addr=47, value=0x7fffebffeab0, size=1, access_size_min=1, access_size_max=1, access=0x55555586de6d <memory_region_write_accessor>, opaque=0x55555662a340) at /home/tlv/akivity/qemu/memory.c:364 #15 0x000055555586e43c in memory_region_iorange_write (iorange=0x7fffe4000ed0, offset=47, width=1, data=0) at /home/tlv/akivity/qemu/memory.c:439 #16 0x0000555555866acc in ioport_writeb_thunk (opaque=0x7fffe4000ed0, addr=49199, data=0) at /home/tlv/akivity/qemu/ioport.c:212 #17 0x00005555558664a6 in ioport_write (index=0, address=49199, data=0) at /home/tlv/akivity/qemu/ioport.c:83 #18 0x0000555555867046 in cpu_outb (addr=49199, val=0 '\000') at /home/tlv/akivity/qemu/ioport.c:289 #19 0x000055555586a958 in kvm_handle_io (port=49199, data=0x7ffff7ff3000, direction=1, size=1, count=1) at /home/tlv/akivity/qemu/kvm-all.c:1423 #20 0x000055555586af5e in kvm_cpu_exec (env=0x55555659b0b0) at /home/tlv/akivity/qemu/kvm-all.c:1571 #21 0x00005555557f74e4 in qemu_kvm_cpu_thread_fn (arg=0x55555659b0b0) at /home/tlv/akivity/qemu/cpus.c:757 #22 0x00007ffff6727d14 in start_thread () from /lib64/libpthread.so.0 #23 0x00007ffff533667d in clone () from /lib64/libc.so.6 (gdb) fr 4 #4 0x00005555558054ed in address_space_rw (as=0x555556629d78, addr=29563620, buf=0x7fffebffe874 "", len=4, is_write=false) at /home/tlv/akivity/qemu/exec.c:3428 3428 val = io_mem_read(section->mr, addr1, 4); (gdb) p as.root.name $1 = 0x55555662cc80 "bus master" (gdb) p as.root.enabled $2 = false We're executing a scsi script without enabling the lsi bus master bit. There is also a bug in the lsi code: 1038 again: 1039 insn_processed++; 1040 insn = read_dword(s, s->dsp); 1041 if (!insn) { 1042 /* If we receive an empty opcode increment the DSP by 4 bytes 1043 instead of 8 and execute the next opcode at that location */ 1044 s->dsp += 4; 1045 goto again; Which causes the script interpreter to go into an infinite loop. This should be moved to a bottom half or thread. -- error compiling committee.c: too many arguments to function

7 years

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[PATCH][v2] megasas: Add boot support for LSI MegaRAID SAS

by Hannes Reinecke

This patch adds boot support for LSI MegaRAID SAS controllers. Signed-off-by: Hannes Reinecke <hare(a)suse.de> Cc: Kevin O'Connor <kevin(a)koconnor.net> Cc: Gerd Hofmann <kraxel(a)redhat.com> Cc: Alex Graf <agraf(a)suse.de> Cc: Paolo Bonzini <pbonzini(a)redhat.com> diff --git a/Makefile b/Makefile index 5486f88..b0e2031 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ SRCBOTH=misc.c stacks.c pmm.c output.c util.c block.c floppy.c ata.c mouse.c \ pnpbios.c pirtable.c vgahooks.c ramdisk.c pcibios.c blockcmd.c \ usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c \ virtio-ring.c virtio-pci.c virtio-blk.c virtio-scsi.c apm.c ahci.c \ - usb-uas.c lsi-scsi.c esp-scsi.c + usb-uas.c lsi-scsi.c esp-scsi.c megasas.c SRC16=$(SRCBOTH) system.c disk.c font.c SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ diff --git a/src/Kconfig b/src/Kconfig index ee6fdb6..0b112ed 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -141,6 +141,12 @@ menu "Hardware support" default y help Support boot from qemu-emulated lsi53c895a scsi storage. + config MEGASAS + depends on DRIVES + bool "LSI MegaRAID SAS controllers" + default y + help + Support boot from LSI MegaRAID SAS scsi storage. config FLOPPY depends on DRIVES bool "Floppy controller" diff --git a/src/block.c b/src/block.c index 243428e..cfe5c33 100644 --- a/src/block.c +++ b/src/block.c @@ -336,6 +336,7 @@ process_op(struct disk_op_s *op) case DTYPE_VIRTIO_SCSI: case DTYPE_LSI_SCSI: case DTYPE_ESP_SCSI: + case DTYPE_MEGASAS: return process_scsi_op(op); default: op->count = 0; diff --git a/src/blockcmd.c b/src/blockcmd.c index 77c690f..81b191b 100644 --- a/src/blockcmd.c +++ b/src/blockcmd.c @@ -17,6 +17,7 @@ #include "virtio-scsi.h" // virtio_scsi_cmd_data #include "lsi-scsi.h" // lsi_scsi_cmd_data #include "esp-scsi.h" // esp_scsi_cmd_data +#include "megasas.h" // megasas_cmd_data #include "boot.h" // boot_add_hd // Route command to low-level handler. @@ -39,6 +40,8 @@ cdb_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize) return lsi_scsi_cmd_data(op, cdbcmd, blocksize); case DTYPE_ESP_SCSI: return esp_scsi_cmd_data(op, cdbcmd, blocksize); + case DTYPE_MEGASAS: + return megasas_cmd_data(op, cdbcmd, blocksize); default: op->count = 0; return DISK_RET_EPARAM; diff --git a/src/disk.h b/src/disk.h index 3d07372..21debec 100644 --- a/src/disk.h +++ b/src/disk.h @@ -235,6 +235,7 @@ struct drive_s { #define DTYPE_UAS 0x0b #define DTYPE_LSI_SCSI 0x0c #define DTYPE_ESP_SCSI 0x0d +#define DTYPE_MEGASAS 0x0e #define MAXDESCSIZE 80 diff --git a/src/megasas.c b/src/megasas.c new file mode 100644 index 0000000..f710cd7 --- /dev/null +++ b/src/megasas.c @@ -0,0 +1,399 @@ +// MegaRAID SAS boot support. +// +// Copyright (C) 2012 Hannes Reinecke, SUSE Linux Products GmbH +// +// Authors: +// Hannes Reinecke <hare(a)suse.de> +// +// based on virtio-scsi.c which is written by: +// Paolo Bonzini <pbonzini(a)redhat.com> +// +// This file may be distributed under the terms of the GNU LGPLv3 license. + +#include "util.h" // dprintf +#include "pci.h" // foreachpci +#include "config.h" // CONFIG_* +#include "biosvar.h" // GET_GLOBAL +#include "pci_ids.h" // PCI_DEVICE_ID_XXX +#include "pci_regs.h" // PCI_VENDOR_ID +#include "boot.h" // bootprio_find_scsi_device +#include "blockcmd.h" // scsi_init_drive +#include "disk.h" + +#define MFI_DB 0x0 // Doorbell +#define MFI_OMSG0 0x18 // Outbound message 0 +#define MFI_IDB 0x20 // Inbound doorbell +#define MFI_ODB 0x2c // Outbound doorbell +#define MFI_IQP 0x40 // Inbound queue port +#define MFI_OSP0 0xb0 // Outbound scratch pad0 +#define MFI_IQPL 0xc0 // Inbound queue port (low bytes) +#define MFI_IQPH 0xc4 // Inbound queue port (high bytes) + +#define MFI_STATE_MASK 0xf0000000 +#define MFI_STATE_WAIT_HANDSHAKE 0x60000000 +#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 +#define MFI_STATE_READY 0xb0000000 +#define MFI_STATE_OPERATIONAL 0xc0000000 +#define MFI_STATE_FAULT 0xf0000000 + +/* MFI Commands */ +typedef enum { + MFI_CMD_INIT = 0x00, + MFI_CMD_LD_READ, + MFI_CMD_LD_WRITE, + MFI_CMD_LD_SCSI_IO, + MFI_CMD_PD_SCSI_IO, + MFI_CMD_DCMD, + MFI_CMD_ABORT, + MFI_CMD_SMP, + MFI_CMD_STP +} mfi_cmd_t; + +struct megasas_cmd_frame { + u8 cmd; /*00h */ + u8 sense_len; /*01h */ + u8 cmd_status; /*02h */ + u8 scsi_status; /*03h */ + + u8 target_id; /*04h */ + u8 lun; /*05h */ + u8 cdb_len; /*06h */ + u8 sge_count; /*07h */ + + u32 context; /*08h */ + u32 context_64; /*0Ch */ + + u16 flags; /*10h */ + u16 timeout; /*12h */ + u32 data_xfer_len; /*14h */ + + union { + struct { + u32 opcode; /*18h */ + u8 mbox[12]; /*1Ch */ + u32 sgl_addr; /*28h */ + u32 sgl_len; /*32h */ + u32 pad; /*34h */ + } dcmd; + struct { + u32 sense_buf_lo; /*18h */ + u32 sense_buf_hi; /*1Ch */ + u8 cdb[16]; /*20h */ + u32 sgl_addr; /*30h */ + u32 sgl_len; /*34h */ + } pthru; + struct { + u8 pad[22]; /*18h */ + } gen; + }; +} __attribute__ ((packed)); + +struct mfi_ld_list_s { + u32 count; + u32 reserved_0; + struct { + u8 target; + u8 lun; + u16 seq; + u8 state; + u8 reserved_1[3]; + u64 size; + } lds[64]; +} __attribute__ ((packed)); + +#define MEGASAS_POLL_TIMEOUT 60000 // 60 seconds polling timeout + +struct megasas_lun_s { + struct drive_s drive; + struct pci_device *pci; + struct megasas_cmd_frame *frame; + u32 iobase; + u8 target; + u8 lun; +}; + +static int megasas_fire_cmd(u16 pci_id, u32 ioaddr, + struct megasas_cmd_frame *frame) +{ + u32 frame_addr = (u32)frame; + int frame_count = 1; + u8 cmd_state; + u64 end; + + dprintf(2, "Frame 0x%x\n", frame_addr); + if (pci_id == PCI_DEVICE_ID_LSI_SAS2004 || + pci_id == PCI_DEVICE_ID_LSI_SAS2008) { + outl(0, ioaddr + MFI_IQPH); + outl(frame_addr | frame_count << 1 | 1, ioaddr + MFI_IQPL); + } else if (pci_id == PCI_DEVICE_ID_DELL_PERC5 || + pci_id == PCI_DEVICE_ID_LSI_SAS1064R || + pci_id == PCI_DEVICE_ID_LSI_VERDE_ZCR) { + outl(frame_addr >> 3 | frame_count, ioaddr + MFI_IQP); + } else { + outl(frame_addr | frame_count << 1 | 1, ioaddr + MFI_IQP); + } + + end = calc_future_tsc(MEGASAS_POLL_TIMEOUT); + do { + for (;;) { + cmd_state = GET_LOWFLAT(frame->cmd_status); + if (cmd_state != 0xff) + break; + if (check_tsc(end)) { + warn_timeout(); + return -1; + } + yield(); + } + } while (cmd_state == 0xff); + + if (cmd_state == 0 || cmd_state == 0x2d) + return 0; + dprintf(1, "ERROR: Frame 0x%x, status 0x%x\n", frame_addr, cmd_state); + return -1; +} + +int +megasas_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize) +{ + struct megasas_lun_s *mlun = + container_of(op->drive_g, struct megasas_lun_s, drive); + u8 *cdb = cdbcmd; + struct megasas_cmd_frame *frame = GET_GLOBAL(mlun->frame); + u16 pci_id = GET_GLOBAL(mlun->pci->device); + int i; + + if (!CONFIG_MEGASAS) + return DISK_RET_EBADTRACK; + + memset_fl(frame, 0, sizeof(*frame)); + SET_LOWFLAT(frame->cmd, MFI_CMD_LD_SCSI_IO); + SET_LOWFLAT(frame->cmd_status, 0xFF); + SET_LOWFLAT(frame->target_id, GET_GLOBAL(mlun->target)); + SET_LOWFLAT(frame->lun, GET_GLOBAL(mlun->lun)); + SET_LOWFLAT(frame->flags, 0x0001); + SET_LOWFLAT(frame->data_xfer_len, op->count * blocksize); + SET_LOWFLAT(frame->cdb_len, 16); + + for (i = 0; i < 16; i++) { + SET_LOWFLAT(frame->pthru.cdb[i], cdb[i]); + } + dprintf(2, "pthru cmd 0x%x count %d bs %d\n", + cdb[0], op->count, blocksize); + + if (op->count) { + SET_LOWFLAT(frame->pthru.sgl_addr, (u32)op->buf_fl); + SET_LOWFLAT(frame->pthru.sgl_len, op->count * blocksize); + SET_LOWFLAT(frame->sge_count, 1); + } + SET_LOWFLAT(frame->context, (u32)frame); + + if (megasas_fire_cmd(pci_id, GET_GLOBAL(mlun->iobase), frame) == 0) + return DISK_RET_SUCCESS; + + dprintf(2, "pthru cmd 0x%x failed\n", cdb[0]); + return DISK_RET_EBADTRACK; +} + +static int +megasas_add_lun(struct pci_device *pci, u32 iobase, u8 target, u8 lun) +{ + struct megasas_lun_s *mlun = malloc_fseg(sizeof(*mlun)); + char *name; + int prio, ret = 0; + + if (!mlun) { + warn_noalloc(); + return -1; + } + memset(mlun, 0, sizeof(*mlun)); + mlun->drive.type = DTYPE_MEGASAS; + mlun->drive.cntl_id = pci->bdf; + mlun->pci = pci; + mlun->target = target; + mlun->lun = lun; + mlun->iobase = iobase; + mlun->frame = memalign_low(256, sizeof(struct megasas_cmd_frame)); + if (!mlun->frame) { + warn_noalloc(); + free(mlun); + return -1; + } + name = znprintf(36, "MegaRAID SAS (PCI %02x:%02x.%x) LD %d:%d", + pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf), + pci_bdf_to_fn(pci->bdf), target, lun); + prio = bootprio_find_scsi_device(pci, target, lun); + ret = scsi_init_drive(&mlun->drive, name, prio); + free(name); + if (ret) { + free(mlun->frame); + free(mlun); + ret = -1; + } + + return ret; +} + +static void megasas_scan_target(struct pci_device *pci, u32 iobase) +{ + struct mfi_ld_list_s ld_list; + struct megasas_cmd_frame *frame = memalign_tmp(256, sizeof(*frame)); + int i; + + memset(&ld_list, 0, sizeof(ld_list)); + memset_fl(frame, 0, sizeof(*frame)); + + frame->cmd = MFI_CMD_DCMD; + frame->cmd_status = 0xFF; + frame->sge_count = 1; + frame->flags = 0x0011; + frame->data_xfer_len = sizeof(ld_list); + frame->dcmd.opcode = 0x03010000; + frame->dcmd.sgl_addr = (u32)MAKE_FLATPTR(GET_SEG(SS), &ld_list); + frame->dcmd.sgl_len = sizeof(ld_list); + frame->context = (u32)frame; + + if (megasas_fire_cmd(pci->device, iobase, frame) == 0) { + dprintf(2, "%d LD found\n", ld_list.count); + for (i = 0; i < ld_list.count; i++) { + dprintf(2, "LD %d:%d state 0x%x\n", + ld_list.lds[i].target, ld_list.lds[i].lun, + ld_list.lds[i].state); + if (ld_list.lds[i].state != 0) { + megasas_add_lun(pci, iobase, + ld_list.lds[i].target, ld_list.lds[i].lun); + } + } + } +} + +static int megasas_transition_to_ready(struct pci_device *pci, u32 ioaddr) +{ + u32 fw_state = 0, new_state, mfi_flags = 0; + u64 end; + + if (pci->device == PCI_DEVICE_ID_LSI_SAS1064R || + pci->device == PCI_DEVICE_ID_DELL_PERC5) + new_state = inl(ioaddr + MFI_OMSG0) & MFI_STATE_MASK; + else + new_state = inl(ioaddr + MFI_OSP0) & MFI_STATE_MASK; + + while (fw_state != new_state) { + switch (new_state) { + case MFI_STATE_FAULT: + dprintf(1, "ERROR: fw in fault state\n"); + return -1; + break; + case MFI_STATE_WAIT_HANDSHAKE: + mfi_flags = 0x08; + /* fallthrough */ + case MFI_STATE_BOOT_MESSAGE_PENDING: + mfi_flags |= 0x10; + if (pci->device == PCI_DEVICE_ID_LSI_SAS2004 || + pci->device == PCI_DEVICE_ID_LSI_SAS2008 || + pci->device == PCI_DEVICE_ID_LSI_SAS2208 || + pci->device == PCI_DEVICE_ID_LSI_SAS3108) { + outl(ioaddr + MFI_DB, mfi_flags); + } else { + outl(ioaddr + MFI_IDB, mfi_flags); + } + break; + case MFI_STATE_OPERATIONAL: + mfi_flags = 0x07; + if (pci->device == PCI_DEVICE_ID_LSI_SAS2004 || + pci->device == PCI_DEVICE_ID_LSI_SAS2008 || + pci->device == PCI_DEVICE_ID_LSI_SAS2208 || + pci->device == PCI_DEVICE_ID_LSI_SAS3108) { + outl(ioaddr + MFI_DB, mfi_flags); + if (pci->device == PCI_DEVICE_ID_LSI_SAS2208 || + pci->device == PCI_DEVICE_ID_LSI_SAS3108) { + int j = 0; + u32 doorbell; + + while (j < MEGASAS_POLL_TIMEOUT) { + doorbell = inl(ioaddr + MFI_DB) & 1; + if (!doorbell) + break; + msleep(20); + j++; + } + } + } else { + outw(ioaddr + MFI_IDB, mfi_flags); + } + break; + case MFI_STATE_READY: + dprintf(2, "MegaRAID SAS fw ready\n"); + return 0; + } + // The current state should not last longer than poll timeout + end = calc_future_tsc(MEGASAS_POLL_TIMEOUT); + for (;;) { + if (check_tsc(end)) { + break; + } + yield(); + fw_state = new_state; + if (pci->device == PCI_DEVICE_ID_LSI_SAS1064R || + pci->device == PCI_DEVICE_ID_DELL_PERC5) + new_state = inl(ioaddr + MFI_OMSG0) & MFI_STATE_MASK; + else + new_state = inl(ioaddr + MFI_OSP0) & MFI_STATE_MASK; + if (new_state != fw_state) { + break; + } + } + } + dprintf(1, "ERROR: fw in state %x\n", new_state & MFI_STATE_MASK); + return -1; +} + +static void +init_megasas(struct pci_device *pci) +{ + u16 bdf = pci->bdf; + u32 iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_2) + & PCI_BASE_ADDRESS_IO_MASK; + + dprintf(1, "found MegaRAID SAS at %02x:%02x.%x, io @ %x\n", + pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), + pci_bdf_to_fn(bdf), iobase); + + pci_config_maskw(pci->bdf, PCI_COMMAND, 0, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + // reset + if (megasas_transition_to_ready(pci, iobase) == 0) + megasas_scan_target(pci, iobase); + + return; +} + +void +megasas_setup(void) +{ + ASSERT32FLAT(); + if (!CONFIG_MEGASAS) + return; + + dprintf(3, "init megasas\n"); + + struct pci_device *pci; + foreachpci(pci) { + if (pci->vendor != PCI_VENDOR_ID_LSI_LOGIC && + pci->vendor != PCI_VENDOR_ID_DELL) + continue; + if (pci->device != PCI_DEVICE_ID_LSI_SAS1064R || + pci->device != PCI_DEVICE_ID_LSI_SAS1078 || + pci->device != PCI_DEVICE_ID_LSI_SAS1078DE || + pci->device != PCI_DEVICE_ID_LSI_SAS2108 || + pci->device != PCI_DEVICE_ID_LSI_SAS2108E || + pci->device != PCI_DEVICE_ID_LSI_SAS2004 || + pci->device != PCI_DEVICE_ID_LSI_SAS2008 || + pci->device != PCI_DEVICE_ID_LSI_VERDE_ZCR || + pci->device != PCI_DEVICE_ID_DELL_PERC5 || + pci->device != PCI_DEVICE_ID_LSI_SAS2208 || + pci->device != PCI_DEVICE_ID_LSI_SAS3108) + continue; + init_megasas(pci); + } +} diff --git a/src/megasas.h b/src/megasas.h new file mode 100644 index 0000000..124042e --- /dev/null +++ b/src/megasas.h @@ -0,0 +1,8 @@ +#ifndef __MEGASAS_H +#define __MEGASAS_H + +struct disk_op_s; +int megasas_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize); +void megasas_setup(void); + +#endif /* __MEGASAS_H */ diff --git a/src/pci_ids.h b/src/pci_ids.h index 4b59585..665e945 100644 --- a/src/pci_ids.h +++ b/src/pci_ids.h @@ -199,6 +199,7 @@ #define PCI_DEVICE_ID_LSI_63C815 0x1000 #define PCI_DEVICE_ID_LSI_SAS1064 0x0050 #define PCI_DEVICE_ID_LSI_SAS1064R 0x0411 +#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 #define PCI_DEVICE_ID_LSI_SAS1066 0x005E #define PCI_DEVICE_ID_LSI_SAS1068 0x0054 #define PCI_DEVICE_ID_LSI_SAS1064A 0x005C @@ -206,6 +207,13 @@ #define PCI_DEVICE_ID_LSI_SAS1066E 0x005A #define PCI_DEVICE_ID_LSI_SAS1068E 0x0058 #define PCI_DEVICE_ID_LSI_SAS1078 0x0060 +#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C +#define PCI_DEVICE_ID_LSI_SAS2108E 0x0078 +#define PCI_DEVICE_ID_LSI_SAS2108 0x0079 +#define PCI_DEVICE_ID_LSI_SAS2208 0x005B +#define PCI_DEVICE_ID_LSI_SAS3108 0x005D +#define PCI_DEVICE_ID_LSI_SAS2004 0x0071 +#define PCI_DEVICE_ID_LSI_SAS2008 0x0073 #define PCI_VENDOR_ID_ATI 0x1002 /* Mach64 */ diff --git a/src/post.c b/src/post.c index 924b311..0133f75 100644 --- a/src/post.c +++ b/src/post.c @@ -29,7 +29,7 @@ #include "virtio-scsi.h" // virtio_scsi_setup #include "lsi-scsi.h" // lsi_scsi_setup #include "esp-scsi.h" // esp_scsi_setup - +#include "megasas.h" // megasas_setup /**************************************************************** * BIOS init @@ -198,6 +198,7 @@ init_hw(void) virtio_scsi_setup(); lsi_scsi_setup(); esp_scsi_setup(); + megasas_setup(); } // Begin the boot process by invoking an int0x19 in 16bit mode.

7 years

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[PATCH] DSDT: Fix HPET _CRS Method

by Gabriel L. Somlo

Updated _CRS method for HPET, bringing it in line with the way it is presented on recent hardware (e.g. Dell Latitude D630, MacPro5,1, etc); Allows it to be detected and utilized from Mac OS X; Also tested OK on Linux (F16 64-bit install DVD) and Windows (Win7 64-bit install DVD). Signed-off-by: Gabriel Somlo <somlo(a)cmu.edu> --- src/acpi-dsdt.dsl | 20 +++++++++----------- 1 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index d2575a5..065a3e5 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -251,6 +251,12 @@ DefinitionBlock ( Device(HPET) { Name(_HID, EISAID("PNP0103")) Name(_UID, 0) + Name(BUF0, ResourceTemplate() { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) OperationRegion(HPTM, SystemMemory , 0xFED00000, 0x400) Field(HPTM, DWordAcc, Lock, Preserve) { VEND, 32, @@ -268,17 +274,9 @@ DefinitionBlock ( } Return (0x0F) } - Name(_CRS, ResourceTemplate() { - DWordMemory( - ResourceConsumer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, - 0xFED00000, - 0xFED003FF, - 0x00000000, - 0x00000400 /* 1K memory: FED00000 - FED003FF */ - ) - }) + Method (_CRS, 0, NotSerialized) { + Return (BUF0) + } } } -- 1.7.7.6

7 years

6
16
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SeaBIOS November 2012