[PATCH 04/20] seabios: add q35 initialization functions.
by Gerd Hoffmann
From: Isaku Yamahata <yamahata(a)valinux.co.jp>
add q35 initialization functions.
[jbaron(a)redhat.com: restructured to current seabios base, updated pci base to 0xb0000000]
[kraxel(a)redhat.com: join the two lpc init funcs into one]
Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp>
Signed-off-by: Jason Baron <jbaron(a)redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com>
---
src/acpi.c | 32 ++++++++++++++++++++-
src/dev-q35.h | 46 +++++++++++++++++++++++++++++++
src/pciinit.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--
src/shadow.c | 13 +++++++++
src/smm.c | 37 +++++++++++++++++++++++++
5 files changed, 208 insertions(+), 5 deletions(-)
create mode 100644 src/dev-q35.h
diff --git a/src/acpi.c b/src/acpi.c
index 1fc170f..72c8fe8 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -13,6 +13,7 @@
#include "pci_regs.h" // PCI_INTERRUPT_LINE
#include "ioport.h" // inl
#include "paravirt.h" // qemu_cfg_irq0_override
+#include "dev-q35.h" // qemu_cfg_irq0_override
/****************************************************/
/* ACPI tables init */
@@ -260,11 +261,38 @@ static void piix4_fadt_init(struct pci_device *pci, void *arg)
(1 << 15));
}
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void ich9_lpc_fadt_init(struct pci_device *dev, void *arg)
+{
+ struct fadt_descriptor_rev1 *fadt = arg;
+
+ fadt->model = 1;
+ fadt->reserved1 = 0;
+ fadt->sci_int = cpu_to_le16(9);
+ fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
+ fadt->acpi_enable = ICH9_ACPI_ENABLE;
+ fadt->acpi_disable = ICH9_ACPI_DISABLE;
+ fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
+ fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
+ fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
+ fadt->gpe0_blk = cpu_to_le32(PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS);
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = ICH9_PMIO_GPE0_BLK_LEN;
+ fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
+ fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
+ /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */
+ fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) |
+ (1 << 7));
+}
+
static const struct pci_device_id fadt_init_tbl[] = {
/* PIIX4 Power Management device (for ACPI) */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
piix4_fadt_init),
-
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
+ ich9_lpc_fadt_init),
PCI_DEVICE_END
};
@@ -739,7 +767,7 @@ build_srat(void)
static const struct pci_device_id acpi_find_tbl[] = {
/* PIIX4 Power Management device. */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
-
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, NULL),
PCI_DEVICE_END,
};
diff --git a/src/dev-q35.h b/src/dev-q35.h
new file mode 100644
index 0000000..6ae039f
--- /dev/null
+++ b/src/dev-q35.h
@@ -0,0 +1,46 @@
+#ifndef __DEV_Q35_H
+#define __DEV_Q35_H
+
+#include "types.h" // u16
+
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
+#define Q35_HOST_BRIDGE_PAM0 0x90
+#define Q35_HOST_BRIDGE_SMRAM 0x9d
+#define Q35_HOST_BRIDGE_PCIEXBAR 0x60
+#define Q35_HOST_BRIDGE_PCIEXBAR_SIZE (256 * 1024 * 1024)
+#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR 0xb0000000
+#define Q35_HOST_BRIDGE_PCIEXBAREN ((u64)1)
+#define Q35_HOST_PCIE_PCI_SEGMENT 0
+#define Q35_HOST_PCIE_START_BUS_NUMBER 0
+#define Q35_HOST_PCIE_END_BUS_NUMBER 255
+
+#define PCI_DEVICE_ID_INTEL_ICH9_LPC 0x2918
+#define ICH9_LPC_PMBASE 0x40
+#define ICH9_LPC_PMBASE_RTE 0x1
+
+#define ICH9_LPC_ACPI_CTRL 0x44
+#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
+#define ICH9_LPC_PIRQA_ROUT 0x60
+#define ICH9_LPC_PIRQE_ROUT 0x68
+#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
+#define ICH9_LPC_PORT_ELCR1 0x4d0
+#define ICH9_LPC_PORT_ELCR2 0x4d1
+#define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930
+#define ICH9_SMB_SMB_BASE 0x20
+#define ICH9_SMB_HOSTC 0x40
+#define ICH9_SMB_HOSTC_HST_EN 0x01
+
+#define ICH9_ACPI_ENABLE 0x2
+#define ICH9_ACPI_DISABLE 0x3
+
+/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
+#define ICH9_PMIO_GPE0_STS 0x20
+#define ICH9_PMIO_GPE0_BLK_LEN 0x10
+#define ICH9_PMIO_SMI_EN 0x30
+#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
+
+/* FADT ACPI_ENABLE/ACPI_DISABLE */
+#define ICH9_APM_ACPI_ENABLE 0x2
+#define ICH9_APM_ACPI_DISABLE 0x3
+
+#endif // dev-q35.h
diff --git a/src/pciinit.c b/src/pciinit.c
index 565a0e4..5bec062 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -12,6 +12,11 @@
#include "ioport.h" // PORT_ATA1_CMD_BASE
#include "config.h" // CONFIG_*
#include "xen.h" // usingXen
+#include "memmap.h" // add_e820
+#include "dev-q35.h"
+
+/* PM Timer ticks per second (HZ) */
+#define PM_TIMER_FREQUENCY 3579545
#define PCI_DEVICE_MEM_MIN 0x1000
#define PCI_BRIDGE_IO_MIN 0x1000
@@ -121,6 +126,45 @@ static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
}
+/* ICH9 LPC PCI to ISA bridge */
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void mch_isa_bridge_init(struct pci_device *dev, void *arg)
+{
+ u16 bdf = dev->bdf;
+ int i, irq;
+ u8 elcr[2];
+
+ elcr[0] = 0x00;
+ elcr[1] = 0x00;
+
+ for (i = 0; i < 4; i++) {
+ irq = pci_irqs[i];
+ /* set to trigger level */
+ elcr[irq >> 3] |= (1 << (irq & 7));
+
+ /* activate irq remapping in LPC */
+
+ /* PIRQ[A-D] routing */
+ pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i,
+ irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+ /* PIRQ[E-H] routing */
+ pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i,
+ irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+ }
+ outb(elcr[0], ICH9_LPC_PORT_ELCR1);
+ outb(elcr[1], ICH9_LPC_PORT_ELCR2);
+ dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
+
+ /* pm io base */
+ pci_config_writel(bdf, ICH9_LPC_PMBASE,
+ PORT_ACPI_PM_BASE | ICH9_LPC_PMBASE_RTE);
+
+ /* acpi enable, SCI: IRQ9 000b = irq9*/
+ pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
+
+ pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
+}
+
static void storage_ide_init(struct pci_device *pci, void *arg)
{
/* IDE: we map it as in ISA mode */
@@ -150,9 +194,6 @@ static void apple_macio_init(struct pci_device *pci, void *arg)
pci_set_io_region_addr(pci, 0, 0x80800000, 0);
}
-/* PM Timer ticks per second (HZ) */
-#define PM_TIMER_FREQUENCY 3579545
-
/* PIIX4 Power Management device (for ACPI) */
static void piix4_pm_init(struct pci_device *pci, void *arg)
{
@@ -168,12 +209,27 @@ static void piix4_pm_init(struct pci_device *pci, void *arg)
pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
}
+/* ICH9 SMBUS */
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
+void ich9_smbus_init(struct pci_device *dev, void *arg)
+{
+ u16 bdf = dev->bdf;
+ /* map smbus into io space */
+ pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
+ PORT_SMB_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* enable SMBus */
+ pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
+}
+
static const struct pci_device_id pci_device_tbl[] = {
/* PIIX3/PIIX4 PCI to ISA bridge */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
piix_isa_bridge_init),
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
piix_isa_bridge_init),
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
+ mch_isa_bridge_init),
/* STORAGE IDE */
PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
@@ -192,6 +248,8 @@ static const struct pci_device_id pci_device_tbl[] = {
/* PIIX4 Power Management device (for ACPI) */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
piix4_pm_init),
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
+ ich9_smbus_init),
/* 0xff00 */
PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
@@ -240,9 +298,30 @@ void i440fx_mem_addr_init(struct pci_device *dev, void *arg)
pcimem_start = 0xc0000000;
}
+void mch_mem_addr_init(struct pci_device *dev, void *arg)
+{
+ u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
+ u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
+
+ /* setup mmconfig */
+ u16 bdf = dev->bdf;
+ u32 upper = addr >> 32;
+ u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
+ pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
+ pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
+ pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
+ add_e820(addr, size, E820_RESERVED);
+
+ /* setup pci i/o window (above mmconfig) */
+ pcimem_start = addr + size;
+ mtrr_base = addr + size;
+}
+
static const struct pci_device_id pci_platform_tbl[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
i440fx_mem_addr_init),
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
+ mch_mem_addr_init),
PCI_DEVICE_END
};
diff --git a/src/shadow.c b/src/shadow.c
index 11c4d5e..a2195da 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -11,6 +11,7 @@
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "pci_regs.h" // PCI_VENDOR_ID
#include "xen.h" // usingXen
+#include "dev-q35.h" // PCI_VENDOR_ID_INTEL
// On the emulators, the bios at 0xf0000 is also at 0xffff0000
#define BIOS_SRC_OFFSET 0xfff00000
@@ -101,9 +102,16 @@ static void i440fx_bios_make_readonly(struct pci_device *pci, void *arg)
make_bios_readonly_intel(pci->bdf, I440FX_PAM0);
}
+void mch_bios_make_readonly(struct pci_device *pci, void *arg)
+{
+ make_bios_readonly_intel(pci->bdf, Q35_HOST_BRIDGE_PAM0);
+}
+
static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
i440fx_bios_make_readonly),
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
+ mch_bios_make_readonly),
PCI_DEVICE_END
};
@@ -127,6 +135,11 @@ make_bios_writable(void)
make_bios_writable_intel(bdf, I440FX_PAM0);
return;
}
+ if (vendor == PCI_VENDOR_ID_INTEL
+ && device == PCI_DEVICE_ID_INTEL_Q35_MCH) {
+ make_bios_writable_intel(bdf, Q35_HOST_BRIDGE_PAM0);
+ return;
+ }
}
dprintf(1, "Unable to unlock ram - bridge not found\n");
}
diff --git a/src/smm.c b/src/smm.c
index d0d1476..7977ac7 100644
--- a/src/smm.c
+++ b/src/smm.c
@@ -11,6 +11,7 @@
#include "ioport.h" // outb
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "xen.h" // usingXen
+#include "dev-q35.h"
ASM32FLAT(
".global smm_relocation_start\n"
@@ -137,9 +138,45 @@ static void piix4_apmc_smm_init(struct pci_device *pci, void *arg)
pci_config_writeb(i440_pci->bdf, I440FX_SMRAM, 0x02 | 0x08);
}
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void ich9_lpc_apmc_smm_init(struct pci_device *dev, void *arg)
+{
+ struct pci_device *mch_dev;
+ int mch_bdf;
+
+ // This code is hardcoded for Q35 Power Management device.
+ mch_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_Q35_MCH);
+ mch_bdf = mch_dev->bdf;
+
+ if (mch_bdf < 0)
+ return;
+
+ /* check if SMM init is already done */
+ u32 value = inl(PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN);
+ if (value & ICH9_PMIO_SMI_EN_APMC_EN)
+ return;
+
+ /* enable the SMM memory window */
+ pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x48);
+
+ smm_save_and_copy();
+
+ /* enable SMI generation when writing to the APMC register */
+ outl(value | ICH9_PMIO_SMI_EN_APMC_EN,
+ PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN);
+
+ smm_relocate_and_restore();
+
+ /* close the SMM memory window and enable normal SMM */
+ pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x08);
+}
+
static const struct pci_device_id smm_init_tbl[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
piix4_apmc_smm_init),
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
+ ich9_lpc_apmc_smm_init),
PCI_DEVICE_END,
};
--
1.7.1
6 years, 5 months
[PATCH 03/20] seabios: pci: enable SERR of normal device.
by Gerd Hoffmann
From: Isaku Yamahata <yamahata(a)valinux.co.jp>
enable SERR of normal device for AER.
Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com>
Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp>
Signed-off-by: Jason Baron <jbaron(a)redhat.com>
---
src/pciinit.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/pciinit.c b/src/pciinit.c
index d5d01d2..565a0e4 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -215,7 +215,8 @@ static void pci_bios_init_device(struct pci_device *pci)
pci_init_device(pci_device_tbl, pci, NULL);
/* enable memory mappings */
- pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+ pci_config_maskw(bdf, PCI_COMMAND, 0,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
}
static void pci_bios_init_devices(void)
--
1.7.1
6 years, 5 months
[PATCH 02/20] seabios: acpi, fadt: make while fadt initialization chipset specific
by Gerd Hoffmann
From: Isaku Yamahata <yamahata(a)valinux.co.jp>
make while fadt initialization chipset specific.
Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com>
Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp>
Signed-off-by: Jason Baron <jbaron(a)redhat.com>
---
src/acpi.c | 34 ++++++++++++++++++----------------
1 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c
index 6d239fa..1fc170f 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -233,13 +233,31 @@ build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
#define PIIX4_GPE0_BLK 0xafe0
#define PIIX4_GPE0_BLK_LEN 4
+#define PIIX4_PM_INTRRUPT 9 // irq 9
+
static void piix4_fadt_init(struct pci_device *pci, void *arg)
{
struct fadt_descriptor_rev1 *fadt = arg;
+
+ fadt->model = 1;
+ fadt->reserved1 = 0;
+ fadt->sci_int = cpu_to_le16(PIIX4_PM_INTRRUPT);
+ fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
fadt->acpi_enable = PIIX4_ACPI_ENABLE;
fadt->acpi_disable = PIIX4_ACPI_DISABLE;
+ fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
+ fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
+ fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
+ fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
+ fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
+ /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */
+ fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) |
+ (1 << 15));
}
static const struct pci_device_id fadt_init_tbl[] = {
@@ -281,23 +299,7 @@ build_fadt(struct pci_device *pci)
fadt->firmware_ctrl = cpu_to_le32((u32)facs);
fadt->dsdt = 0; /* dsdt will be filled later in acpi_bios_init()
by fill_dsdt() */
- fadt->model = 1;
- fadt->reserved1 = 0;
- int pm_sci_int = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE);
- fadt->sci_int = cpu_to_le16(pm_sci_int);
- fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
- fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
- fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
- fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm_tmr_len = 4;
- fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
- fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
pci_init_device(fadt_init_tbl, pci, fadt);
- /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */
- fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) |
- (1 << 15));
build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
--
1.7.1
6 years, 5 months
[PATCH 01/20] seabios: make mttr UC area setup dynamic
by Gerd Hoffmann
From: Jason Baron <jbaron(a)redhat.com>
Set up the UC area of mtrr dynamically based on mtrr_base. This allows
the bios to work for other chipsets that might want to set the mtrr.
Since BUILD_MAX_HIGHMEM is no longer used we can remove the config parameter.
This change reverses the order of pci_setup() and smm_init() with
mtrr_setup().
Signed-off-by: Jason Baron <jbaron(a)redhat.com>
---
src/config.h | 1 -
src/mtrr.c | 5 +++--
src/pci.h | 1 +
src/pciinit.c | 2 ++
src/post.c | 6 +++---
5 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/config.h b/src/config.h
index 0d4066d..71c0b7e 100644
--- a/src/config.h
+++ b/src/config.h
@@ -44,7 +44,6 @@
#define BUILD_SMM_INIT_ADDR 0x38000
#define BUILD_SMM_ADDR 0xa8000
#define BUILD_SMM_SIZE 0x8000
-#define BUILD_MAX_HIGHMEM 0xe0000000
#define BUILD_PCIMEM_START 0xe0000000
#define BUILD_PCIMEM_END 0xfec00000 /* IOAPIC is mapped at */
diff --git a/src/mtrr.c b/src/mtrr.c
index 0957834..81a78c6 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -7,6 +7,7 @@
#include "util.h" // dprintf
#include "config.h" // CONFIG_*
#include "xen.h" // usingXen
+#include "pci.h" // mtrr_base
#define MSR_MTRRcap 0x000000fe
#define MSR_MTRRfix64K_00000 0x00000250
@@ -94,9 +95,9 @@ void mtrr_setup(void)
wrmsr_smp(MTRRphysMask_MSR(i), 0);
}
/* Mark 3.5-4GB as UC, anything not specified defaults to WB */
- wrmsr_smp(MTRRphysBase_MSR(0), BUILD_MAX_HIGHMEM | MTRR_MEMTYPE_UC);
+ wrmsr_smp(MTRRphysBase_MSR(0), mtrr_base | MTRR_MEMTYPE_UC);
wrmsr_smp(MTRRphysMask_MSR(0)
- , (-((1ull<<32)-BUILD_MAX_HIGHMEM) & phys_mask) | 0x800);
+ , (-((1ull<<32)-mtrr_base) & phys_mask) | 0x800);
// Enable fixed and variable MTRRs; set default type.
wrmsr_smp(MSR_MTRRdefType, 0xc00 | MTRR_MEMTYPE_WB);
diff --git a/src/pci.h b/src/pci.h
index fe663b8..104638d 100644
--- a/src/pci.h
+++ b/src/pci.h
@@ -56,6 +56,7 @@ struct pci_device {
// Local information on device.
int have_driver;
};
+extern u64 mtrr_base;
extern u64 pcimem_start, pcimem_end;
extern u64 pcimem64_start, pcimem64_end;
extern struct pci_device *PCIDevices;
diff --git a/src/pciinit.c b/src/pciinit.c
index 0e87ab0..d5d01d2 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -30,6 +30,8 @@ static const char *region_type_name[] = {
[ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
};
+u64 mtrr_base = BUILD_PCIMEM_START;
+
u64 pcimem_start = BUILD_PCIMEM_START;
u64 pcimem_end = BUILD_PCIMEM_END;
u64 pcimem64_start = BUILD_PCIMEM64_START;
diff --git a/src/post.c b/src/post.c
index 0133f75..ffb4717 100644
--- a/src/post.c
+++ b/src/post.c
@@ -232,13 +232,13 @@ maininit(void)
timer_setup();
mathcp_setup();
- // Initialize mtrr
- mtrr_setup();
-
// Initialize pci
pci_setup();
smm_init();
+ // Initialize mtrr
+ mtrr_setup();
+
// Setup Xen hypercalls
xen_init_hypercalls();
--
1.7.1
6 years, 5 months
[PATCH 00/20] q35 support patch series
by Gerd Hoffmann
Hi,
Next round of the q35 patch series, rebased to master.
Patches 1-6 carry the C code bits. They have been adapted to the recent
changes in master. mcfg acpi table generator simply uses the q35
constants as suggested by Kevin. Otherwise unmodified.
Patches 7+ carry the ACPI bits. First the original unmodified dsdt
patches, then a bunch of cleanup patches on top of that which for the
most part split sharable AML code into separate files.
cheers,
Gerd
PS: Anthony just pulled the q35 patches into qemu/master.
Gerd Hoffmann (14):
simplify chipset detection
acpi: add mcfg table for mmconfig
acpi: move DBUG() to separate file
acpi: move DBUG() to separate file [q35]
acpi: move \_SB.HPET to separate file
acpi: move \_SB.HPET to separate file [q35]
acpi: move \_SB.PCI0._CRS to separate file
acpi: move \_SB.PCI0._CRS to separate file [q35]
acpi: move cpu hotplug to separate file
acpi: move cpu hotplug to separate file [q35]
acpi: rework enable bits
acpi: move isa devices to separate file
acpi: move isa devices to separate file [q35]
q35: fix default vga address
Isaku Yamahata (4):
seabios: acpi, fadt: make while fadt initialization chipset specific
seabios: pci: enable SERR of normal device.
seabios: add q35 initialization functions.
seabios: q35: add dsdt
Jan Kiszka (1):
seabios: q35: Register PCI IRQs as active high in APIC mode
Jason Baron (1):
seabios: make mttr UC area setup dynamic
Makefile | 2 +-
src/acpi-dsdt-cpu-hotplug.dsl | 78 ++++++
src/acpi-dsdt-dbug.dsl | 30 +++
src/acpi-dsdt-hpet.dsl | 36 +++
src/acpi-dsdt-isa.dsl | 113 ++++++++
src/acpi-dsdt-pci-crs.dsl | 104 ++++++++
src/acpi-dsdt.dsl | 437 ++------------------------------
src/acpi.c | 108 +++++---
src/acpi.h | 17 ++
src/config.h | 1 -
src/dev-q35.h | 46 ++++
src/mtrr.c | 5 +-
src/pci.h | 3 +
src/pciinit.c | 97 +++++++-
src/post.c | 6 +-
src/q35-acpi-dsdt.dsl | 563 +++++++++++++++++++++++++++++++++++++++++
src/shadow.c | 13 +
src/smm.c | 37 +++
18 files changed, 1235 insertions(+), 461 deletions(-)
create mode 100644 src/acpi-dsdt-cpu-hotplug.dsl
create mode 100644 src/acpi-dsdt-dbug.dsl
create mode 100644 src/acpi-dsdt-hpet.dsl
create mode 100644 src/acpi-dsdt-isa.dsl
create mode 100644 src/acpi-dsdt-pci-crs.dsl
create mode 100644 src/dev-q35.h
create mode 100644 src/q35-acpi-dsdt.dsl
6 years, 5 months
[PATCH 2/2] floppy: Allow floppy code to be used with coreboot.
by Kevin O'Connor
Allow coreboot users to enable the floppy support (via CBFS files
etc/floppy0 and etc/floppy1) on real hardware. It is unknown if the
Bochs derived floppy controller support will work on real hardware,
but this option will make it easier for those wishing to test.
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
src/floppy.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/floppy.c b/src/floppy.c
index 3c8ae5a..f508559 100644
--- a/src/floppy.c
+++ b/src/floppy.c
@@ -126,7 +126,12 @@ floppy_setup(void)
dprintf(3, "init floppy drives\n");
if (CONFIG_COREBOOT) {
- // XXX - disable floppies on coreboot for now.
+ u8 type = romfile_loadint("etc/floppy0", 0);
+ if (type)
+ addFloppy(0, type);
+ type = romfile_loadint("etc/floppy1", 0);
+ if (type)
+ addFloppy(1, type);
} else {
u8 type = inb_cmos(CMOS_FLOPPY_DRIVE_TYPE);
if (type & 0xf0)
--
1.7.11.7
6 years, 5 months
[PATCH 1/2] floppy: Minor cleanup - reduce some cut-and-paste code.
by Kevin O'Connor
The diskette_param_table is a copy of diskette_param_table2 - just
memcpy it at runtime instead of duplicating the configuration in the
code.
Also, setup the floppy interrupt vector in the floppy.c code instead
of the post.c code.
Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net>
---
src/floppy.c | 22 ++++++----------------
src/post.c | 2 --
2 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/src/floppy.c b/src/floppy.c
index ce54d0c..3c8ae5a 100644
--- a/src/floppy.c
+++ b/src/floppy.c
@@ -47,22 +47,7 @@ struct floppy_ext_dbt_s diskette_param_table2 VAR16VISIBLE = {
.drive_type = 4, // drive type in cmos
};
-// Since no provisions are made for multiple drive types, most
-// values in this table are ignored. I set parameters for 1.44M
-// floppy here
-struct floppy_dbt_s diskette_param_table VAR16FIXED(0xefc7) = {
- .specify1 = 0xAF,
- .specify2 = 0x02,
- .shutoff_ticks = FLOPPY_MOTOR_TICKS,
- .bps_code = FLOPPY_SIZE_CODE,
- .sectors = 18,
- .interblock_len = FLOPPY_GAPLEN,
- .data_len = FLOPPY_DATALEN,
- .gap_len = FLOPPY_FORMAT_GAPLEN,
- .fill_byte = FLOPPY_FILLBYTE,
- .settle_time = 0x0F,
- .startup_time = 0x08,
-};
+struct floppy_dbt_s diskette_param_table VAR16FIXED(0xefc7);
struct floppyinfo_s {
struct chs_s chs;
@@ -131,6 +116,11 @@ addFloppy(int floppyid, int ftype)
void
floppy_setup(void)
{
+ memcpy(&diskette_param_table, &diskette_param_table2
+ , sizeof(diskette_param_table));
+ SET_IVT(0x1E, SEGOFF(SEG_BIOS
+ , (u32)&diskette_param_table2 - BUILD_BIOS_ADDR));
+
if (! CONFIG_FLOPPY)
return;
dprintf(3, "init floppy drives\n");
diff --git a/src/post.c b/src/post.c
index 0133f75..9a6dd3f 100644
--- a/src/post.c
+++ b/src/post.c
@@ -73,8 +73,6 @@ init_ivt(void)
// set vector 0x79 to zero
// this is used by 'gardian angel' protection system
SET_IVT(0x79, SEGOFF(0, 0));
-
- SET_IVT(0x1E, SEGOFF(SEG_BIOS, (u32)&diskette_param_table2 - BUILD_BIOS_ADDR));
}
static void
--
1.7.11.7
6 years, 5 months
[PATCH RfC 0/2] add q35 support
by Gerd Hoffmann
Hi,
The q35 C code bits for review. The confusing mcfg acpi table code is
largely rewritten, otherwise q35 initialization is almost unmodified.
DSDT isn't tackled yet.
cheers,
Gerd
Gerd Hoffmann (1):
pci/acpi: add mcfg table for mmconfig
Isaku Yamahata (1):
seabios: add q35 initialization functions.
src/acpi.c | 54 ++++++++++++++++++++++++++++++-
src/acpi.h | 17 ++++++++++
src/dev-q35.h | 46 +++++++++++++++++++++++++++
src/pci.h | 1 +
src/pciinit.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
src/shadow.c | 13 ++++++++
src/smm.c | 37 ++++++++++++++++++++++
7 files changed, 262 insertions(+), 3 deletions(-)
create mode 100644 src/dev-q35.h
6 years, 5 months
