New subject: Change in coreboot[master]: soc/amd/picasso: Add bootblock support

5 Dec 2019

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37490 )
Change subject: soc/amd/picasso: Add bootblock
......................................................................
soc/amd/picasso: Add bootblock
The original plan for Picasso was to always combine features of bootblock
with its romstage due to its unique way of coming out of reset.  The arch
and cpu implementations for RESET_VECTOR_IN_RAM are simplified now,
allowing the option of running a more traditional bootblock, albeit in
system DRAM.
Create a new early.c file to contain the initial steps required,
regardless of whether the first stage is bootblock or eventually
romstage.  Add bootblock files containing functions that lib/bootblock
expects. Modify Makefile.inc to automatically determine the BIOS image's
base and size.
Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
A src/soc/amd/picasso/bootblock/bootblock.c
A src/soc/amd/picasso/bootblock/pre_c.S
A src/soc/amd/picasso/early.c
A src/soc/amd/picasso/include/soc/early.h
6 files changed, 258 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37490/1

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 56c7da7..cbee93d 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -26,6 +26,7 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
+	select RESET_VECTOR_IN_RAM
    select X86_AMD_FIXED_MTRRS
    select X86_AMD_INIT_SIPI
    select ACPI_AMD_HARDWARE_SLEEP_VALUES
@@ -55,10 +56,6 @@
    select SSE2
    select RTC
-config HAVE_BOOTBLOCK
-	bool
-	default n
-
 config PRERAM_CBMEM_CONSOLE_SIZE
    hex
    default 0x1600
@@ -213,6 +210,28 @@
menu "PSP Configuration Options"
+config X86_RESET_VECTOR
+	hex
+	default 0x807fff0
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x80000
+
+config EARLYRAM_BSP_STACK_SIZE
+	hex
+	default 0x800
+	help
+	  The amount of stack allocated to the bootstrap core before ramstage.
+
+config RAM_RESET_VECTOR_STAGE_BSS_SIZE
+	hex
+	depends on RESET_VECTOR_IN_RAM
+	default 0x50000
+	help
+	  A common region of DRAM is allocated for use as .bss for all
+	  pre-ramstage stages.
+
 config AMDFW_OUTSIDE_CBFS
    bool "The AMD firmware is outside CBFS"
    default n
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 76a4d70..b0cce26 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -37,8 +37,19 @@
 subdirs-y += ../../../cpu/x86/pae
 subdirs-y += ../../../cpu/x86/smm
+bootblock-y += bootblock/pre_c.S
+bootblock-y += bootblock/bootblock.c
+bootblock-y += early.c
+bootblock-y += southbridge.c
+bootblock-y += i2c.c
+bootblock-$(CONFIG_PICASSO_UART) += uart.c
+bootblock-y += tsc_freq.c
+bootblock-y += gpio.c
+bootblock-y += smi_util.c
+
 romstage-y += i2c.c
 romstage-y += romstage.c
+romstage-y += early.c
 romstage-y += gpio.c
 romstage-y += pmutil.c
 romstage-y += reset.c
@@ -56,12 +67,6 @@
 verstage-$(CONFIG_PICASSO_UART) += uart.c
 verstage-y += tsc_freq.c
-postcar-y += monotonic_timer.c
-postcar-$(CONFIG_PICASSO_UART) += uart.c
-postcar-y += memmap.c
-postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
-postcar-y += tsc_freq.c
-
 ramstage-y += i2c.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
@@ -204,8 +209,15 @@
# type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR)
-PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE)
+PSP_ELF_FILE=$(obj)/cbfs/fallback/bootblock.elf
+PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE)
+PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE)))
+
+## INTERM=$(shell printf "%x" $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10))
+## $(warning INTERM: $(INTERM))
+
+## $(warning PSP_BIOSBIN_DEST: $(CONFIG_X86_RESET_VECTOR) $(INTERM): $(PSP_BIOSBIN_DEST))
+## #$(shell printf "%d" $(CONFIG_STACK_SIZE))
# type = 0x63
 PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS)
@@ -287,6 +299,12 @@
 OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode)
 OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config)
+$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
+	rm -f $@
+	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
+	$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
+		--maxsize $(PSP_BIOSBIN_SIZE)
+
 $(obj)/amdfw.rom:	$(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
    		$(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \
    		$(call strip_quotes, $(PSPBTLDR_FILE)) \
@@ -391,13 +409,6 @@
    	--location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \
    	--output	$@
-USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf
-$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS)
-	rm -f $@
-	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
-	$(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \
-		--maxsize $(PSP_BIOSBIN_SIZE)
-
 ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
 PHONY+=add_amdfw
 INTERMEDIATE+=add_amdfw
diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c
new file mode 100644
index 0000000..e448e1b
--- /dev/null
+++ b/src/soc/amd/picasso/bootblock/bootblock.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <bootblock_common.h>
+#include <soc/early.h>
+#include <timestamp.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	amd_initmmio();
+	set_caching();
+
+	bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+	soc_pre_console_init();
+}
+
+void bootblock_soc_init(void)
+{
+	soc_post_console_init();
+}
diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S
new file mode 100644
index 0000000..ccff7e6
--- /dev/null
+++ b/src/soc/amd/picasso/bootblock/pre_c.S
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/post_code.h>
+
+/*
+ * on entry:
+ *   mm0: BIST (ignored)
+ *   mm2_mm1: timestamp at bootblock_protected_mode_entry
+ */
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+	post_code(0xa0)
+
+	movl	$_eearlyram_stack, %esp
+
+	/* Align the stack and keep aligned for call to bootblock_c_entry() */
+	and	$0xfffffff0, %esp
+	sub	$8, %esp
+
+	movd	%mm2, %eax
+	pushl	%eax		/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax		/* tsc[31:0] */
+
+	post_code(0xa2)
+
+	call	bootblock_c_entry
+	/* Never reached */
+
+.halt_forever:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.halt_forever
diff --git a/src/soc/amd/picasso/early.c b/src/soc/amd/picasso/early.c
new file mode 100644
index 0000000..7b03a62
--- /dev/null
+++ b/src/soc/amd/picasso/early.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+#include <console/console.h>
+#include <soc/early.h>
+#include <soc/southbridge.h>
+
+void amd_initmmio(void)
+{
+	msr_t mmconf;
+
+	mmconf.hi = 0;
+	mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
+			| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
+	wrmsr(MMIO_CONF_BASE, mmconf);
+}
+
+static const unsigned int fixed_mtrrs[] = {
+	MTRR_FIX_64K_00000,
+	MTRR_FIX_16K_80000,
+	MTRR_FIX_16K_A0000,
+	MTRR_FIX_4K_C0000,
+	MTRR_FIX_4K_C8000,
+	MTRR_FIX_4K_D0000,
+	MTRR_FIX_4K_D8000,
+	MTRR_FIX_4K_E0000,
+	MTRR_FIX_4K_E8000,
+	MTRR_FIX_4K_F0000,
+	MTRR_FIX_4K_F8000,
+};
+
+void set_caching(void)
+{
+	msr_t deftype, syscfg, rwmem;
+	int mtrr;
+	int i;
+
+	syscfg = rdmsr(SYSCFG_MSR);
+	syscfg.lo |= SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn
+				| SYSCFG_MSR_MtrrVarDramEn;
+	wrmsr(SYSCFG_MSR, syscfg);
+
+	/* Write all as MTRR_READ_MEM | MTRR_WRITE_MEM to send cycles to DRAM */
+	rwmem.hi = rwmem.lo = 0x18181818;
+	for (i = 0 ; i < ARRAY_SIZE(fixed_mtrrs) ; i++)
+		wrmsr(fixed_mtrrs[i], rwmem);
+
+	syscfg.lo &= ~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn);
+	wrmsr(SYSCFG_MSR, syscfg);
+
+	deftype = rdmsr(MTRR_DEF_TYPE_MSR);
+	deftype.lo &= ~MTRR_DEF_TYPE_MASK;
+	deftype.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN | MTRR_TYPE_UNCACHEABLE;
+	wrmsr(MTRR_DEF_TYPE_MSR, deftype);
+
+	mtrr = get_free_var_mtrr();
+	if (mtrr < 0)
+		return;
+	set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	mtrr = get_free_var_mtrr();
+	if (mtrr < 0)
+		return;
+	set_var_mtrr(mtrr, RESET_VECTOR_STAGE_BASE, RESET_VECTOR_STAGE_SIZE,
+				MTRR_TYPE_WRBACK);
+
+	enable_cache();
+}
+
+void soc_pre_console_init(void)
+{
+	sb_reset_i2c_slaves();
+	fch_pre_init();
+}
+
+void soc_post_console_init(void)
+{
+	u32 val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+
+	fch_early_init();
+	i2c_soc_early_init();
+}
diff --git a/src/soc/amd/picasso/include/soc/early.h b/src/soc/amd/picasso/include/soc/early.h
new file mode 100644
index 0000000..8eb2645
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/early.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PICASSO_EARLY_H__
+#define __PICASSO_EARLY_H__
+
+#define RESET_VECTOR_STAGE_TOP (CONFIG_X86_RESET_VECTOR + 0x10)
+#define RESET_VECTOR_STAGE_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
+#define RESET_VECTOR_STAGE_BASE (RESET_VECTOR_STAGE_TOP - RESET_VECTOR_STAGE_SIZE)
+
+#if (RESET_VECTOR_STAGE_BASE & (RESET_VECTOR_STAGE_SIZE - 1))
+#error "Adjust reset vector and program size for better MTRR coverage"
+#endif
+
+void amd_initmmio(void);
+void set_caching(void);
+void soc_pre_console_init(void);
+void soc_post_console_init(void);
+
+#endif /* __PICASSO_EARLY_H__ */
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c
Gerrit-Change-Number: 37490
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-MessageType: newchange



    