6 comments:
File src/soc/amd/picasso/Kconfig:
Patch Set #7, Line 225: 0x807fff0
Is this architectural?
File src/soc/amd/picasso/Makefile.inc:
Patch Set #7, Line 44: bootblock-y += smi_util.c
What's this?
File src/soc/amd/picasso/bootblock/bootblock.c:
Patch Set #7, Line 14: static void amd_initmmio(void)
If this is only about PCI config space, please name it accordingly.
Um, wait... isn't this the same as enable_pci_mmconf()?
Patch Set #7, Line 34: sb_reset_i2c_slaves();
How is this expected to make a difference for consoles? Why is this done
before and in fch_pre_init()?
Also, I've peeked into it. It seems it might keep pins floating for a
moment if they are actually used as GPO instead of I2C for a board.
That is, if AMD allows such designs. Where is that documented?
Patch Set #7, Line 41: Family_Model
In its encoded form, it's usually called cpuid signature. You can decode
it with get_fms().
Patch Set #7, Line 44: i2c_soc_early_init();
I'm new to AMD. Is there any system behind these sb_, fch_, soc_ prefixes?
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