Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c --- A src/mainboard/asus/h110m-e_m2/6776.txt A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/gpio.txt A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 23 files changed, 1,875 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/1
diff --git a/src/mainboard/asus/h110m-e_m2/6776.txt b/src/mainboard/asus/h110m-e_m2/6776.txt new file mode 100644 index 0000000..9969ca7 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/6776.txt @@ -0,0 +1,10 @@ +acpi/superio.asl:#define NCT6776_SHOW_PP +acpi/superio.asl:#define NCT6776_SHOW_SP1 +acpi/superio.asl:#define NCT6776_SHOW_KBC +acpi/superio.asl:#define NCT6776_SHOW_HWM +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +acpi/superio.asl:#include <superio/nuvoton/nct6776/acpi/superio.asl> +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig b/src/mainboard/asus/h110m-e_m2/Kconfig new file mode 100644 index 0000000..55a21cf --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Kconfig @@ -0,0 +1,53 @@ +if BOARD_ASUS-H110M_E-M2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select GENERIC_SPD_BIN + select SUPERIO_NUVOTON_NCT5539D + select SUPERIO_NUVOTON_NCT5539D_COM_A + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asus/h110m" + +config MAINBOARD_PART_NUMBER + string + default "H110M" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig.name b/src/mainboard/asus/h110m-e_m2/Kconfig.name new file mode 100644 index 0000000..788594c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_H110M_E-M.2 + bool "H110M_E-M.2" diff --git a/src/mainboard/asus/h110m-e_m2/Makefile.inc b/src/mainboard/asus/h110m-e_m2/Makefile.inc new file mode 100644 index 0000000..ce6cf80 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asus/h110m-e_m2/acpi/ec.asl b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl diff --git a/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl diff --git a/src/mainboard/asus/h110m-e_m2/acpi/superio.asl b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asus/h110m-e_m2/acpi_tables.c b/src/mainboard/asus/h110m-e_m2/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi_tables.c diff --git a/src/mainboard/asus/h110m-e_m2/board_info.txt b/src/mainboard/asus/h110m-e_m2/board_info.txt new file mode 100644 index 0000000..23fd8e6 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/H110M-E-M-2/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/asus/h110m-e_m2/bootblock.c b/src/mainboard/asus/h110m-e_m2/bootblock.c new file mode 100644 index 0000000..eb019c2 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/bootblock.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5539d/nct5539d.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/asus/h110m-e_m2/cmos.default b/src/mainboard/asus/h110m-e_m2/cmos.default new file mode 100644 index 0000000..3296093 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asus/h110m-e_m2/cmos.layout b/src/mainboard/asus/h110m-e_m2/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/h110m-e_m2/data.vbt b/src/mainboard/asus/h110m-e_m2/data.vbt new file mode 100644 index 0000000..fb03cca --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/data.vbt Binary files differ diff --git a/src/mainboard/asus/h110m-e_m2/devicetree.cb b/src/mainboard/asus/h110m-e_m2/devicetree.cb new file mode 100644 index 0000000..cdc6c2d --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/devicetree.cb @@ -0,0 +1,388 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "SkipExtGfxScan" = "0" + register "PrimaryDisplay" = "Display_PEG" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "EnableLan" = "0" + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + register "PmTimerDisabled" = "0" + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x1901 + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on # Thermal Subsystem + subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1849 0xa102 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct5539d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct5539d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/asus/h110m-e_m2/dsdt.asl b/src/mainboard/asus/h110m-e_m2/dsdt.asl new file mode 100644 index 0000000..f3e216d --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads new file mode 100644 index 0000000..86a3a62 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi +-- Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h110m-e_m2/gpio.txt b/src/mainboard/asus/h110m-e_m2/gpio.txt new file mode 100644 index 0000000..3416eee --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/gpio.txt @@ -0,0 +1,580 @@ +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +include/gpio.h:#ifndef _GPIO_DVS_H +include/gpio.h:#define _GPIO_DVS_H +include/gpio.h: /* GPIO Group GPP_A */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_B */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_C */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_D */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_E */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_F */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_G */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_H */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +include/gpio.h: /* GPIO Group GPD */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_I */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_A */ +devicetree.cb: device pnp 2e.7 off end # GPIO6 +devicetree.cb: device pnp 2e.107 off end # GPIO7 +devicetree.cb: device pnp 2e.207 off end # GPIO8 +devicetree.cb: device pnp 2e.108 off end # GPIO0 +devicetree.cb: device pnp 2e.308 off end # GPIO base +devicetree.cb: device pnp 2e.708 off end # GPIO1 +devicetree.cb: device pnp 2e.9 off end # GPIO2 +devicetree.cb: device pnp 2e.109 off end # GPIO3 +devicetree.cb: device pnp 2e.209 off end # GPIO4 +devicetree.cb: device pnp 2e.309 off end # GPIO5 +devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +include/gpio.h:#ifndef _GPIO_DVS_H +include/gpio.h:#define _GPIO_DVS_H +include/gpio.h: /* GPIO Group GPP_A */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_B */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_C */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_D */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_E */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_F */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_G */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_H */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +include/gpio.h: /* GPIO Group GPD */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_I */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_A */ +devicetree.cb: device pnp 2e.7 off end # GPIO6 +devicetree.cb: device pnp 2e.107 off end # GPIO7 +devicetree.cb: device pnp 2e.207 off end # GPIO8 +devicetree.cb: device pnp 2e.108 off end # GPIO0 +devicetree.cb: device pnp 2e.308 off end # GPIO base +devicetree.cb: device pnp 2e.708 off end # GPIO1 +devicetree.cb: device pnp 2e.9 off end # GPIO2 +devicetree.cb: device pnp 2e.109 off end # GPIO3 +devicetree.cb: device pnp 2e.209 off end # GPIO4 +devicetree.cb: device pnp 2e.309 off end # GPIO5 +devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H +gpio.txt:include/gpio.h:#define _GPIO_DVS_H +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_B */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_C */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_D */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_E */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_F */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_G */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_H */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPD */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_I */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:devicetree.cb: device pnp 2e.7 off end # GPIO6 +gpio.txt:devicetree.cb: device pnp 2e.107 off end # GPIO7 +gpio.txt:devicetree.cb: device pnp 2e.207 off end # GPIO8 +gpio.txt:devicetree.cb: device pnp 2e.108 off end # GPIO0 +gpio.txt:devicetree.cb: device pnp 2e.308 off end # GPIO base +gpio.txt:devicetree.cb: device pnp 2e.708 off end # GPIO1 +gpio.txt:devicetree.cb: device pnp 2e.9 off end # GPIO2 +gpio.txt:devicetree.cb: device pnp 2e.109 off end # GPIO3 +gpio.txt:devicetree.cb: device pnp 2e.209 off end # GPIO4 +gpio.txt:devicetree.cb: device pnp 2e.309 off end # GPIO5 +gpio.txt:devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H +gpio.txt:include/gpio.h:#define _GPIO_DVS_H +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_B */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_C */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_D */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_E */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_F */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_G */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ diff --git a/src/mainboard/asus/h110m-e_m2/hda_verb.c b/src/mainboard/asus/h110m-e_m2/hda_verb.c new file mode 100644 index 0000000..1d1627b --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/hda_verb.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header ALC887 */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + + /* coreboot specific header */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h110m-e_m2/include/gpio.h b/src/mainboard/asus/h110m-e_m2/include/gpio.h new file mode 100644 index 0000000..a8a4d19 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/include/gpio.h @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_DVS_H +#define _GPIO_DVS_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + H110_PAD_DW0_DW1_CFG(GPP_A11, 0x44000502, 0x00003023), /* PME# */ + H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */ + H110_PAD_DW0_DW1_CFG(GPP_A16, 0x04000100, 0x00001028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A17, 0x04000100, 0x00001029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A18, 0x04000100, 0x0000102a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A19, 0x04000100, 0x0000102b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A20, 0x04000100, 0x0000102c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A21, 0x04000100, 0x0000102d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A22, 0x04000100, 0x0000102e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A23, 0x04000100, 0x0000102f), /* GPIO */ + /* GPIO Group GPP_B */ + H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B1, 0x04000100, 0x00001031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B3, 0x04000100, 0x00001033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B4, 0x04000100, 0x00001034), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B5, 0x44000702, 0x00000035), /* SRCCLKREQ0# */ + H110_PAD_DW0_DW1_CFG(GPP_B6, 0x04000100, 0x00001036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B7, 0x04000500, 0x00001037), /* SRCCLKREQ2# */ + H110_PAD_DW0_DW1_CFG(GPP_B8, 0x04000100, 0x00001038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B9, 0x04000500, 0x00001039), /* SRCCLKREQ4# */ + H110_PAD_DW0_DW1_CFG(GPP_B10, 0x04000500, 0x0000103a), /* SRCCLKREQ5# */ + H110_PAD_DW0_DW1_CFG(GPP_B11, 0x84000100, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B12, 0x84000100, 0x0000103c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B13, 0x84000600, 0x0000003d), /* PLTRST# */ + H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000003e), /* SPKR */ + H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000200, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B17, 0x04000100, 0x00001041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000100, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000100, 0x00001047), /* GPIO */ + /* GPIO Group GPP_C */ + H110_PAD_DW0_DW1_CFG(GPP_C0, 0x84000502, 0x00000048), /* SMBCLK */ + H110_PAD_DW0_DW1_CFG(GPP_C1, 0x84000502, 0x00000049), /* SMBDATA */ + H110_PAD_DW0_DW1_CFG(GPP_C2, 0x84000100, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C3, 0x84000502, 0x0000004b), /* SML0CLK */ + H110_PAD_DW0_DW1_CFG(GPP_C4, 0x84000502, 0x0000004c), /* SML0DATA */ + H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C6, 0x04000102, 0x0000104e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C7, 0x04000102, 0x0000104f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C8, 0x04000100, 0x00001050), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C9, 0x04000100, 0x00001051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C10, 0x04000100, 0x00001052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C11, 0x04000100, 0x00001053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C12, 0x04000100, 0x00000054), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C13, 0x04000100, 0x00001055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C15, 0x04000100, 0x00001057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C16, 0x04000100, 0x00001058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C17, 0x04000100, 0x00001059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C18, 0x04000100, 0x0000105a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C19, 0x04000100, 0x0000105b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000100, 0x0000005c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000100, 0x0000005d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000100, 0x0000005e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C23, 0x84000100, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + H110_PAD_DW0_DW1_CFG(GPP_D0, 0x04000100, 0x00001060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D1, 0x04000100, 0x00001061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D3, 0x04000100, 0x00001063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000100, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D5, 0x04000100, 0x00001065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D6, 0x04000100, 0x00001066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D7, 0x04000100, 0x00001067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D8, 0x04000100, 0x00001068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000100, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000100, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D11, 0x04000100, 0x0000106b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D12, 0x04000102, 0x0000106c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000100, 0x0000006d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000102, 0x0000006e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D16, 0x04000100, 0x00001070), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D17, 0x04000100, 0x00001071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D18, 0x04000100, 0x00001072), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D19, 0x04000100, 0x00001073), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D20, 0x04000100, 0x00001074), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D23, 0x04000100, 0x00001077), /* GPIO */ + /* GPIO Group GPP_E */ + H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000102, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000100, 0x0000001a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E3, 0x04000100, 0x0000101b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E4, 0x44000100, 0x0000001c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E5, 0x04000100, 0x0000101d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E6, 0x04000100, 0x0000101e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E7, 0x04000100, 0x0000101f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + H110_PAD_DW0_DW1_CFG(GPP_E9, 0x84000502, 0x00000021), /* USB_OC0# */ + H110_PAD_DW0_DW1_CFG(GPP_E10, 0x84000502, 0x00000022), /* USB_OC1# */ + H110_PAD_DW0_DW1_CFG(GPP_E11, 0x84000502, 0x00000023), /* USB_OC2# */ + H110_PAD_DW0_DW1_CFG(GPP_E12, 0x84000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000100, 0x00000025), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F1, 0x04000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F2, 0x04000100, 0x00001027), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F3, 0x04000100, 0x00001028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000100, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000100, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000100, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000100, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000100, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000100, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F10, 0x84000100, 0x0000002f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F11, 0x04000100, 0x00001030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F12, 0x04000100, 0x00001031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F13, 0x04000100, 0x00001032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F14, 0x04000100, 0x00001033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F15, 0x84000502, 0x00000034), /* USB_OC4# */ + H110_PAD_DW0_DW1_CFG(GPP_F16, 0x84000102, 0x00000035), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F17, 0x84000102, 0x00000036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000102, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F19, 0x04000100, 0x00001038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F20, 0x04000100, 0x00001039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F21, 0x04000100, 0x0000103a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F22, 0x04000100, 0x0000103b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F23, 0x04000100, 0x0000103c), /* GPIO */ + /* GPIO Group GPP_G */ + H110_PAD_DW0_DW1_CFG(GPP_G0, 0x04000100, 0x0000103d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G1, 0x04000100, 0x0000103e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G2, 0x04000100, 0x0000103f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G3, 0x04000100, 0x00001040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G4, 0x04000100, 0x00001041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G5, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G6, 0x84000100, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G7, 0x84000100, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G8, 0x04000100, 0x00001045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G9, 0x04000100, 0x00001046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G10, 0x04000100, 0x00001047), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G11, 0x04000100, 0x00001048), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G12, 0x04000100, 0x00001049), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G13, 0x04000100, 0x0000104a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G14, 0x84000100, 0x0000004b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000100, 0x0000004c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G16, 0x04000100, 0x0000104d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G17, 0x04000100, 0x0000104e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G18, 0x84000100, 0x0000104f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000100, 0x00001050), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G20, 0x04000100, 0x00001051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G21, 0x04000100, 0x00001052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G22, 0x04000100, 0x00001053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G23, 0x04000100, 0x00001054), /* GPIO */ + /* GPIO Group GPP_H */ + H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000100, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000702, 0x00000056), /* SRCCLKREQ7# */ + H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000100, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000100, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H4, 0x04000100, 0x00001059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000100, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H6, 0x04000100, 0x0000105b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H7, 0x04000100, 0x0000105c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H8, 0x44000702, 0x0000005d), /* SRCCLKREQ14# */ + H110_PAD_DW0_DW1_CFG(GPP_H9, 0x04000100, 0x0000105e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H10, 0x04000100, 0x0000105f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H11, 0x04000100, 0x00001060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H13, 0x44000100, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H14, 0x84000100, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H15, 0x04000100, 0x00001064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H16, 0x84000100, 0x00000065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H17, 0x04000100, 0x00001066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000100, 0x00000067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000100, 0x00000068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000100, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H23, 0x84000102, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD1, 0x84000102, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD2, 0x84000502, 0x0000001a), /* LAN_WAKE# */ + H110_PAD_DW0_DW1_CFG(GPD3, 0x84000502, 0x0000001b), /* PWRBTN# */ + H110_PAD_DW0_DW1_CFG(GPD4, 0x84000600, 0x0000001c), /* SLP_S3# */ + H110_PAD_DW0_DW1_CFG(GPD5, 0x84000600, 0x0000001d), /* SLP_S4# */ + H110_PAD_DW0_DW1_CFG(GPD6, 0x84000100, 0x0000001e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD8, 0x84000500, 0x00000020), /* SUSCLK */ + H110_PAD_DW0_DW1_CFG(GPD9, 0x04000100, 0x00000021), /* SLP_WLAN# */ + H110_PAD_DW0_DW1_CFG(GPD10, 0x84000100, 0x00000022), /* SLP_S5# */ + H110_PAD_DW0_DW1_CFG(GPD11, 0x04000102, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000500, 0x0000006d), /* DDPB_HPD0 */ + H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000500, 0x0000006e), /* DDPC_HPD1 */ + H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + H110_PAD_DW0_DW1_CFG(GPP_I4, 0x04000100, 0x00001071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00000073), + /* DDPB_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000502, 0x00000074), + /* DDPC_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000502, 0x00000075), + /* DDPC_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000100, 0x00000077), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */ +}; + +#endif diff --git a/src/mainboard/asus/h110m-e_m2/mainboard.c b/src/mainboard/asus/h110m-e_m2/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/h110m-e_m2/ramstage.c b/src/mainboard/asus/h110m-e_m2/ramstage.c new file mode 100644 index 0000000..c93e84c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/ramstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; + /* Enable Virtual Channel 1 */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/asus/h110m-e_m2/romstage.c b/src/mainboard/asus/h110m-e_m2/romstage.c new file mode 100644 index 0000000..ae5e297 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/romstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +}
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I'd like you to reexamine a change. Please visit
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c --- A src/mainboard/asus/h110m-e_m2/6776.txt A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/gpio.txt A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 23 files changed, 1,875 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/2
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I'd like you to reexamine a change. Please visit
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c --- A src/mainboard/asus/h110m-e_m2/6776.txt A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/gpio.txt A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 23 files changed, 1,875 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/3
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I'd like you to reexamine a change. Please visit
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c --- A src/mainboard/asus/h110m-e_m2/6776.txt A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/gpio.txt A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 23 files changed, 1,875 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/4
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,273 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/5
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/5/src/mainboard/asus/h110m-e_... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/5/src/mainboard/asus/h110m-e_... PS5, Line 28: {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34603/5/src/mainboard/asus/h110m-e_... PS5, Line 35: const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34603/5/src/mainboard/asus/h110m-e_... PS5, Line 58: { that open brace { should be on the previous line
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,273 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/6
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/6/src/mainboard/asus/h110m-e_... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/6/src/mainboard/asus/h110m-e_... PS6, Line 28: {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34603/6/src/mainboard/asus/h110m-e_... PS6, Line 35: const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34603/6/src/mainboard/asus/h110m-e_... PS6, Line 58: { that open brace { should be on the previous line
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,285 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/7/src/mainboard/asus/h110m-e_... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/7/src/mainboard/asus/h110m-e_... PS7, Line 31: memcpy(dq_map_ptr, dq_map, sizeof(dq_map) ); space prohibited before that close parenthesis ')'
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/8/src/mainboard/asus/h110m-e_... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/8/src/mainboard/asus/h110m-e_... PS8, Line 31: memcpy(dq_map_ptr, dq_map, sizeof(dq_map) ); space prohibited before that close parenthesis ')'
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,285 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/9/src/mainboard/asus/h110m-e_... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/9/src/mainboard/asus/h110m-e_... PS9, Line 31: memcpy(dq_map_ptr, dq_map, sizeof(dq_map) ); space prohibited before that close parenthesis ')'
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#10).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,285 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/10
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 10:
(6 comments)
Looks like you made Jenkins very angry... all the board failed to build :P
Some small things to fix, let's hope it works this time
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 1: BOARD_ASUS-H110M_E-M2 BOARD_ASUS_H110M_E_M2
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 26: h110m h110m-e_m2
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 30: H110M H110M-E/M.2
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 35: : config DEVICETREE : string : default "devicetree.cb" Can be removed
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 1: BOARD_ASUS_H110M_E-M.2 BOARD_ASUS_H110M_E_M2
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 2: H110M_E-M.2 H110M-E/M.2
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#11).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,273 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/11
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 11:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/11/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/11/src/mainboard/asus/h110m-e... PS11, Line 28: {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34603/11/src/mainboard/asus/h110m-e... PS11, Line 35: const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34603/11/src/mainboard/asus/h110m-e... PS11, Line 58: { that open brace { should be on the previous line
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#12).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,280 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/12
Hello Felix Held, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#13).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,280 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/13
Hello Felix Held, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#14).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,280 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/14
Hello Felix Held, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#15).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m_e_m2/Kconfig A src/mainboard/asus/h110m_e_m2/Kconfig.name A src/mainboard/asus/h110m_e_m2/Makefile.inc A src/mainboard/asus/h110m_e_m2/acpi/dptf.asl A src/mainboard/asus/h110m_e_m2/acpi/ec.asl A src/mainboard/asus/h110m_e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m_e_m2/acpi/superio.asl A src/mainboard/asus/h110m_e_m2/acpi_tables.c A src/mainboard/asus/h110m_e_m2/board_info.txt A src/mainboard/asus/h110m_e_m2/bootblock.c A src/mainboard/asus/h110m_e_m2/cmos.default A src/mainboard/asus/h110m_e_m2/cmos.layout A src/mainboard/asus/h110m_e_m2/data.vbt A src/mainboard/asus/h110m_e_m2/devicetree.cb A src/mainboard/asus/h110m_e_m2/dsdt.asl A src/mainboard/asus/h110m_e_m2/gma-mainboard.ads A src/mainboard/asus/h110m_e_m2/hda_verb.c A src/mainboard/asus/h110m_e_m2/include/gpio.h A src/mainboard/asus/h110m_e_m2/mainboard.c A src/mainboard/asus/h110m_e_m2/ramstage.c A src/mainboard/asus/h110m_e_m2/romstage.c 21 files changed, 1,280 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/15
Hello Felix Held, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#16).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m_e_m2/Kconfig A src/mainboard/asus/h110m_e_m2/Kconfig.name A src/mainboard/asus/h110m_e_m2/Makefile.inc A src/mainboard/asus/h110m_e_m2/acpi/dptf.asl A src/mainboard/asus/h110m_e_m2/acpi/ec.asl A src/mainboard/asus/h110m_e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m_e_m2/acpi/superio.asl A src/mainboard/asus/h110m_e_m2/acpi_tables.c A src/mainboard/asus/h110m_e_m2/board_info.txt A src/mainboard/asus/h110m_e_m2/bootblock.c A src/mainboard/asus/h110m_e_m2/cmos.default A src/mainboard/asus/h110m_e_m2/cmos.layout A src/mainboard/asus/h110m_e_m2/data.vbt A src/mainboard/asus/h110m_e_m2/devicetree.cb A src/mainboard/asus/h110m_e_m2/dsdt.asl A src/mainboard/asus/h110m_e_m2/gma-mainboard.ads A src/mainboard/asus/h110m_e_m2/hda_verb.c A src/mainboard/asus/h110m_e_m2/include/gpio.h A src/mainboard/asus/h110m_e_m2/mainboard.c A src/mainboard/asus/h110m_e_m2/ramstage.c A src/mainboard/asus/h110m_e_m2/romstage.c 21 files changed, 1,280 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/16
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 16:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 1: BOARD_ASUS-H110M_E-M2
BOARD_ASUS_H110M_E_M2
Done
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 26: h110m
h110m-e_m2
Done
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 30: H110M
H110M-E/M. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 35: : config DEVICETREE : string : default "devicetree.cb"
Can be removed
Done
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 1: BOARD_ASUS_H110M_E-M.2
BOARD_ASUS_H110M_E_M2
Done
https://review.coreboot.org/c/coreboot/+/34603/10/src/mainboard/asus/h110m-e... PS10, Line 2: H110M_E-M.2
H110M-E/M. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/16/src/mainboard/asus/h110m_e... File src/mainboard/asus/h110m_e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/16/src/mainboard/asus/h110m_e... PS16, Line 30: H110M_E_M2 H110M-E/M.2
Hello Felix Held, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#17).
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
src/mainboard/asus: Add h110m-e_m2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,280 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/17
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 17:
(1 comment)
As you told.
https://review.coreboot.org/c/coreboot/+/34603/16/src/mainboard/asus/h110m_e... File src/mainboard/asus/h110m_e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/16/src/mainboard/asus/h110m_e... PS16, Line 30: H110M_E_M2
H110M-E/M. […]
Done
Hello Felix Held, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#18).
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
src/mainboard/asus: Add H110M-E/M.2 mainboard support
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,280 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/18
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
sudo ./inteltool -g report on the machine, http://dpaste.com/1ZTC9V9
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
And in some other form.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
Need to work on the devicetree.cb, so will be some more patches for this :)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/18//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/18//COMMIT_MSG@8 PS18, Line 8: Remove `src/` from the prefix.
Please give a little more detail how you created the port.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
(16 comments)
Chapter bazillionth: The devicetree :)
Adding Maxim Polyakov as reviewer, as he ported asrock/h110m and probably knows Skylake stuff better than I do
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 78: # VR Settings Configuration for 5 Domains All the VR (Voltage Regulator) settings, if taken from asrock/h110m, should work.
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 145: register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V I think you don't need this
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 190: register "SerialIoDevMode" = "{ \ I don't think these should be enabled either
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 212: 6 In your case, this is root port 8
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 213: register "PcieRpEnable[5]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[5]" = "1" : # Use SRCCLKREQ1# : register "PcieRpClkReqNumber[5]" = "1" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[5]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[5]" = "1" : # Use CLK SRC 1 : register "PcieRpClkSrcNumber[5]" = "1" s/[5]/[7]
(replace '[5]' with '[7]' on this section)
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 225: # Enable Root port 5 (x1) for PCIE slot. This one is correct
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 240: 7 In your case, this is root port 9
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 241: register "PcieRpEnable[6]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[6]" = "1" : # Use SRCCLKREQ3# : register "PcieRpClkReqNumber[6]" = "3" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[6]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[6]" = "1" : # Use CLK SRC 3 : register "PcieRpClkSrcNumber[6]" = "3" : # Use Hot Plug subsystem : register "PcieRpHotPlug[6]" = "1" s/[6]/[8]
(replace '[6]' with '[8]' on this section)
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 278: device pci 14.2 on # Thermal Subsystem : subsystemid 0x1849 0xa131 : end Disable this device:
device pci 14.2 off end # Thermal Subsystem
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 285: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x1849 0xa131 : end Looks disabled on your board, but it might just be hidden
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 302: 1c.4 on 1c.4 off
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 303: 1c.5 on 1c.5 off
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 304: 1c.6 on 1c.6 off
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 305: 1c.7 off 1c.7 on
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 306: 1d.0 off 1d.0 on
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 319: c The values you should write here are the ones superiotool says. Make sure the LDNs (device pnp 2e.X) are correct.
If in doubt, send a log of 'superiotool -d'
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
(5 comments)
I'm sorry for the waiting. I urgently needed to finish the project at work.
as he ported asrock/h110m
This work isn't completed yet. Now I'm working on gpio, and after that I need to solve problems with superio.
and probably knows Skylake stuff better than I do
I'm not sure about that :)
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 64: need to add register "serirq_mode" = "SERIRQ_CONTINUOUS"
to set Continuous SIRQ mode
https://review.coreboot.org/c/coreboot/+/33801
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 94: 0x50 May be better to use the macro VR_CFG_AMP()
https://github.com/coreboot/coreboot/blob/ef7a3267870f126cc2f815812cfe545008...
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 145: register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
I think you don't need this
I agree with you
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 278: device pci 14.2 on # Thermal Subsystem : subsystemid 0x1849 0xa131 : end
Disable this device: […]
Are you sure about that? This device is always enabled on boards with AMI UEFI.
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 285: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x1849 0xa131 : end
Looks disabled on your board, but it might just be hidden
Probably me_cleaner was used to disable this device. However, we need to be very careful with ME: https://recon.cx/2014/slides/Recon%202014%20Skochinsky.pdf
I'm not sure, but I think this interface is needed for initial initialization, even if we disable ME later
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
(2 comments)
Patch Set 18: (5 comments) I'm sorry for the waiting. I urgently needed to finish the project at work.
No worries, there's no time pressure with this port. Any input is appreciated :D
as he ported asrock/h110m
This work isn't completed yet. Now I'm working on gpio, and after that I need to solve problems with superio.
Good luck :)
and probably knows Skylake stuff better than I do
I'm not sure about that :)
I don't have any Skylake hardware to look at :S
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 278: device pci 14.2 on # Thermal Subsystem : subsystemid 0x1849 0xa131 : end
Are you sure about that? This device is always enabled on boards with AMI UEFI.
I checked the lspci with vendor BIOS for that board and it is reported as disabled. (does not appear)
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 285: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x1849 0xa131 : end
Probably me_cleaner was used to disable this device. However, we need to be very careful with ME: […]
Could be me_cleaner, yes.
While doing the porting, I would recommend using a working ME firmware. Weird issues may happen with a me_cleaned firmware, and troubleshooting them is nearly impossible.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
(1 comment)
Good luck :)
Thank you very much :)
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 278: device pci 14.2 on # Thermal Subsystem : subsystemid 0x1849 0xa131 : end
I checked the lspci with vendor BIOS for that board and it is reported as disabled. […]
Maybe this can be enabled/disabled in the BIOS settings?
According to the documentation, the PCH Thermal Subsystem incorporates an on-die Digital Thermal Sensor for thermal management. This device may cause interruptions or shut down the system to S5 with a programmable catastrophic trip point:
https://github.com/coreboot/coreboot/blob/205d5ab20842e57ffd90b78e9d71db7e58... https://github.com/coreboot/coreboot/blob/8950cfb66f8f1fd4b047fbef2347134be0...
In addition, the coreboot uses this device for DPTF: https://github.com/coreboot/coreboot/blob/4f16049f17a4dcbf329d6b30f0d00f0a7f...
I think it would be better to enable device pci 14.2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
(1 comment)
Please also add Documentation.
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 23: static void mainboard_fill_dq_map_data(void *dq_map_ptr) why, seems it's only required for soldered memory?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ......................................................................
Patch Set 18:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 94: 0x50
May be better to use the macro VR_CFG_AMP() […]
this one would be VR_CFG_AMP(20), for instance
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 278: device pci 14.2 on # Thermal Subsystem : subsystemid 0x1849 0xa131 : end
Maybe this can be enabled/disabled in the BIOS settings? […]
Let's leave it enabled for now.
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 285: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x1849 0xa131 : end
Could be me_cleaner, yes. […]
me_cleaner was indeed used
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 320: d floppy doesn't seem to exist on this SIO
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 321: d parallel doesn't seem to exist either
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 336: d IR does not exist
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 359: d ACPI is on
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#19).
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
mainboard/asus: Add h110m-e_m2 mainboard support
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,238 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/19
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#20).
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
mainboard/asus: Add h110m-e_m2 mainboard support
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,238 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/20
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#21).
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
mainboard/asus: Add h110m-e_m2 mainboard support
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,238 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/21
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#22).
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
mainboard/asus: Add h110m-e_m2 mainboard support
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,238 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/22
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#23).
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
mainboard/asus: Add h110m-e_m2 mainboard support
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,236 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/23
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 23:
(2 comments)
Patch Set 18:
(1 comment)
done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 78: # VR Settings Configuration for 5 Domains
All the VR (Voltage Regulator) settings, if taken from asrock/h110m, should work.
Ack
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 225: # Enable Root port 5 (x1) for PCIE slot.
This one is correct
Ack
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#24).
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
mainboard/asus: Add h110m-e_m2 mainboard support
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,229 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/24
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 24:
(20 comments)
done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 78: # VR Settings Configuration for 5 Domains
Ack
Ack
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 94: 0x50
this one would be VR_CFG_AMP(20), for instance
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 145: register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
I agree with you
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 190: register "SerialIoDevMode" = "{ \
I don't think these should be enabled either
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 212: 6
In your case, this is root port 8
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 213: register "PcieRpEnable[5]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[5]" = "1" : # Use SRCCLKREQ1# : register "PcieRpClkReqNumber[5]" = "1" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[5]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[5]" = "1" : # Use CLK SRC 1 : register "PcieRpClkSrcNumber[5]" = "1"
s/[5]/[7] […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 240: 7
In your case, this is root port 9
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 241: register "PcieRpEnable[6]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[6]" = "1" : # Use SRCCLKREQ3# : register "PcieRpClkReqNumber[6]" = "3" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[6]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[6]" = "1" : # Use CLK SRC 3 : register "PcieRpClkSrcNumber[6]" = "3" : # Use Hot Plug subsystem : register "PcieRpHotPlug[6]" = "1"
s/[6]/[8] […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 278: device pci 14.2 on # Thermal Subsystem : subsystemid 0x1849 0xa131 : end
Let's leave it enabled for now.
Ack
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 285: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x1849 0xa131 : end
me_cleaner was indeed used
Ack
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 302: 1c.4 on
1c. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 303: 1c.5 on
1c. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 304: 1c.6 on
1c. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 305: 1c.7 off
1c. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 306: 1d.0 off
1d. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 320: d
floppy doesn't seem to exist on this SIO
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 321: d
parallel doesn't seem to exist either
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 336: d
IR does not exist
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 359: d
ACPI is on
Done
https://review.coreboot.org/c/coreboot/+/34603/16/src/mainboard/asus/h110m_e... File src/mainboard/asus/h110m_e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/16/src/mainboard/asus/h110m_e... PS16, Line 30: H110M_E_M2
Done
Done
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 24:
(1 comment)
Patch Set 18:
(1 comment)
Please also add Documentation.
Will do, might take some time.
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 23: static void mainboard_fill_dq_map_data(void *dq_map_ptr)
why, seems it's only required for soldered memory?
Done
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 24:
(2 comments)
Okay
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 64:
need to add […]
Done
https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 319: c
The values you should write here are the ones superiotool says. Make sure the LDNs (device pnp 2e. […]
Ack
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 24:
(1 comment)
done.
https://review.coreboot.org/c/coreboot/+/34603/18//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/18//COMMIT_MSG@8 PS18, Line 8:
Remove `src/` from the prefix. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 24:
(9 comments)
https://review.coreboot.org/c/coreboot/+/34603/24//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/24//COMMIT_MSG@7 PS24, Line 7: h110m-e_m2 very minor nit: this can be the pretty name:
Add ASUS H110M-E M/2 mainboard
(note that "support" has been omitted, as it's clear enough)
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 17: s You can remove this
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/superio.asl:
PS24: Maybe this needs an update.
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 98: .psi2threshold = 0x10, \ : .psi3threshold = 0x4, \ These can use VR_CFG_AMP too, see table above, column "SA"
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 110: .psi1threshold = 0x50, \ : .psi2threshold = 0x14, \ : .psi3threshold = 0x4, \ same VR_CFG_AMP thing, row is "IA"
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 123: .psi1threshold = 0x50, \ : .psi2threshold = 0x14, \ : .psi3threshold = 0x4, \ same, "GT unsliced"
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 136: .psi1threshold = 0x50, \ : .psi2threshold = 0x14, \ : .psi3threshold = 0x4, \ same, "GT"
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 253: subsystemid 0x1043 0x8694 inherit move to the previous line, before "device pci 00.0 on"
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 275: end these stale "end" could be moved on the previous line
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add h110m-e_m2 mainboard support ......................................................................
Patch Set 24:
(1 comment)
Hello ..
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/superio.asl:
PS24:
Maybe this needs an update.
Got any idea? Will it be like this ,https://pastebin.com/U3BqMe2G?
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#25).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,364 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/25
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#26).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,363 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/26
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/26/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/26/src/mainboard/asus/h110m-e... PS26, Line 253: device pci 00.0 on # Host Bridge trailing whitespace
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#27).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,363 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/27
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/27/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/27/src/mainboard/asus/h110m-e... PS27, Line 253: device pci 00.0 on # Host Bridge trailing whitespace
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#28).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,363 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/28
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#29).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,363 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/29
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#30).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,360 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/30
Hello Maxim Polyakov, Felix Held, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#31).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,359 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/31
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#32).
Change subject: mainboard/asus: Add ASUS H110M-E M/2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E M/2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,358 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/32
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#33).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,358 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/33
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 33:
(8 comments)
hmm
https://review.coreboot.org/c/coreboot/+/34603/24//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/24//COMMIT_MSG@7 PS24, Line 7: h110m-e_m2
very minor nit: this can be the pretty name: […]
Done
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 17: s
You can remove this
Done
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 98: .psi2threshold = 0x10, \ : .psi3threshold = 0x4, \
These can use VR_CFG_AMP too, see table above, column "SA"
Done
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 110: .psi1threshold = 0x50, \ : .psi2threshold = 0x14, \ : .psi3threshold = 0x4, \
same VR_CFG_AMP thing, row is "IA"
Done
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 123: .psi1threshold = 0x50, \ : .psi2threshold = 0x14, \ : .psi3threshold = 0x4, \
same, "GT unsliced"
Done
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 136: .psi1threshold = 0x50, \ : .psi2threshold = 0x14, \ : .psi3threshold = 0x4, \
same, "GT"
Done
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 253: subsystemid 0x1043 0x8694 inherit
move to the previous line, before "device pci 00. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... PS24, Line 275: end
these stale "end" could be moved on the previous line
Done
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#34).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,356 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/34
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/34/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/34/src/mainboard/asus/h110m-e... PS34, Line 92: #| IccMax | 7A | 34A | 34A | 35A | 35A | : #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | According to commits Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde and Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e these values are set automatically in src/soc/intel/skylake/vr_config.c
Please add information about this in the comments. For example #| IccMax* | 0 | 0 | 0 | 0 | 0 | #| VrVoltageLimit* | 0 | 0 | 0 | 0 | 0 | #+-----------------+---+----+----+---+---+ [*] Installed automatically for KBL-S and KBL-DT CPUs in the vr_config.c
Something like that
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 34:
Patch Set 34:
(1 comment)
Sorry, icc_max only
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#35).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,358 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/35
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 35:
(1 comment)
done.
https://review.coreboot.org/c/coreboot/+/34603/34/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/34/src/mainboard/asus/h110m-e... PS34, Line 92: #| IccMax | 7A | 34A | 34A | 35A | 35A | : #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
According to commits Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde and Change-Id: I849845ced0 […]
Done
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 35:
(1 comment)
Patch Set 34:
Patch Set 34:
(1 comment)
Sorry, icc_max only
https://review.coreboot.org/c/coreboot/+/34603/35/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/35/src/mainboard/asus/h110m-e... PS35, Line 93: * Sorry, I was wrong about the VrVoltageLimit icc_max only Thanks
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#36).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,358 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/36
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 36:
(1 comment)
:)
https://review.coreboot.org/c/coreboot/+/34603/35/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/35/src/mainboard/asus/h110m-e... PS35, Line 93: *
Sorry, I was wrong about the VrVoltageLimit […]
Ack
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#37).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,349 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/37
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 37:
Please also add a link to your h110m-e_m2.md file in the Documentation/mainboard/index.md
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#38).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,350 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/38
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#39).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/39
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 39:
(1 comment)
Thanks!
https://review.coreboot.org/c/coreboot/+/34603/24/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/superio.asl:
PS24:
Got any idea? Will it be like this ,https://pastebin. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 39:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/37/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/37/src/mainboard/asus/h110m-e... PS37, Line 88: #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | : #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | : #| ImonSlope | 0 | 0 | 0 | 0 | 0 | : #| ImonOffset | 0 | 0 | 0 | 0 | 0 | : #| IccMax* | 0 | 0 | 0 | 0 | 0 | oops!
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#40).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/40
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#41).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/41
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#42).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/42
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#43).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/43
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#44).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/44
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#45).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 22 files changed, 1,351 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/45
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 45:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/45/Documentation/mainboard/as... File Documentation/mainboard/asus/h110m-e_m2.md:
https://review.coreboot.org/c/coreboot/+/34603/45/Documentation/mainboard/as... PS45, Line 1: # ASUS H110M-E/M.2 document must be referenced from existing document, for example index.md
https://review.coreboot.org/c/coreboot/+/34603/45/Documentation/mainboard/as... PS45, Line 67: The flash chip is a 16 MiB socketed DIP-8 chip. Specifically, it's a can you provide a picture showing the position of the flash IC? It should be no bigger than 800px in width and have a low quality level.
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#46).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.jpg A Documentation/mainboard/asus/h110m-e_m2.md M Documentation/mainboard/index.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 24 files changed, 1,355 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/46
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 46:
(2 comments)
Thanks for all the suggestions and corrections.
https://review.coreboot.org/c/coreboot/+/34603/45/Documentation/mainboard/as... File Documentation/mainboard/asus/h110m-e_m2.md:
https://review.coreboot.org/c/coreboot/+/34603/45/Documentation/mainboard/as... PS45, Line 1: # ASUS H110M-E/M.2
document must be referenced from existing document, for example index. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/45/Documentation/mainboard/as... PS45, Line 67: The flash chip is a 16 MiB socketed DIP-8 chip. Specifically, it's a
can you provide a picture showing the position of the flash IC? […]
Done
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 46:
(1 comment)
Hmm.
https://review.coreboot.org/c/coreboot/+/34603/37/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/37/src/mainboard/asus/h110m-e... PS37, Line 88: #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | : #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | : #| ImonSlope | 0 | 0 | 0 | 0 | 0 | : #| ImonOffset | 0 | 0 | 0 | 0 | 0 | : #| IccMax* | 0 | 0 | 0 | 0 | 0 |
oops!
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 46:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/46//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/46//COMMIT_MSG@9 PS46, Line 9: This port is based on the Asrock H110M Could it be a variant?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 46:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/46/Documentation/mainboard/as... File Documentation/mainboard/asus/h110m-e_m2.md:
https://review.coreboot.org/c/coreboot/+/34603/46/Documentation/mainboard/as... PS46, Line 44: output is not required: to speed up the boot.
https://review.coreboot.org/c/coreboot/+/34603/46/Documentation/mainboard/as... PS46, Line 73: an Should fit on the line above.
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#47).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is a variant of the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.jpg A Documentation/mainboard/asus/h110m-e_m2.md M Documentation/mainboard/index.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 24 files changed, 1,355 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/47
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 47:
(2 comments)
Isn't it high time to test this change already? :D
https://review.coreboot.org/c/coreboot/+/34603/46//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/46//COMMIT_MSG@9 PS46, Line 9: This port is based on the Asrock H110M
Could it be a variant?
No, as the variants are under a mainboard vendor/model. In this case it's asus vs asrock, so not a good idea.
Plus, the thing is untested...
https://review.coreboot.org/c/coreboot/+/34603/47//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/47//COMMIT_MSG@9 PS47, Line 9: a variant of Please undo the commit message change
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 47:
(1 comment)
Patch Set 47:
(2 comments)
Isn't it high time to test this change already? :D
I broke the cs pin of the chip, so waiting for new chips to come from chine, will take months but I got no way, tried an winbond 16mb 8 pin spi flash but not working.
https://review.coreboot.org/c/coreboot/+/34603/46//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/46//COMMIT_MSG@9 PS46, Line 9: This port is based on the Asrock H110M
Could it be a variant?
could be.
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#48).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.jpg A Documentation/mainboard/asus/h110m-e_m2.md M Documentation/mainboard/index.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 24 files changed, 1,355 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/48
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#49).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.jpg A Documentation/mainboard/asus/h110m-e_m2.md M Documentation/mainboard/index.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 24 files changed, 1,378 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/49
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 49:
(1 comment)
o/
https://review.coreboot.org/c/coreboot/+/34603/49/Documentation/mainboard/in... File Documentation/mainboard/index.md:
https://review.coreboot.org/c/coreboot/+/34603/49/Documentation/mainboard/in... PS49, Line 11: - [H110M-E/M.2](asus/h110m-e_m2.md) Looks like until this port gets working and approved, the index.md file will keep updating and changing. So I can withheld it and can always add that as a final touch, no point in adding it to every patch.
Hello Maxim Polyakov, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#50).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A Documentation/mainboard/asus/h110m-e_m2.jpg A Documentation/mainboard/asus/h110m-e_m2.md A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 23 files changed, 1,353 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/50
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
So far the serial output of coreboot which leads to a blank display with a blinking cursor, https://pastebin.com/S9tLjhwb
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50: Code-Review+1
(19 comments)
Patch Set 50:
So far the serial output of coreboot which leads to a blank display with a blinking cursor, https://pastebin.com/S9tLjhwb
Well well well... It seems to hang when writing the SIO global registers. As I commented on the devtree, just remove these writes. Hope this helps.
https://review.coreboot.org/c/coreboot/+/34603/47//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/47//COMMIT_MSG@9 PS47, Line 9: a variant of
Please undo the commit message change
Done
https://review.coreboot.org/c/coreboot/+/34603/46/Documentation/mainboard/as... File Documentation/mainboard/asus/h110m-e_m2.md:
https://review.coreboot.org/c/coreboot/+/34603/46/Documentation/mainboard/as... PS46, Line 44: output is not required:
to speed up the boot.
Done
https://review.coreboot.org/c/coreboot/+/34603/46/Documentation/mainboard/as... PS46, Line 73: an
Should fit on the line above.
Done
https://review.coreboot.org/c/coreboot/+/34603/49/Documentation/mainboard/in... File Documentation/mainboard/index.md:
https://review.coreboot.org/c/coreboot/+/34603/49/Documentation/mainboard/in... PS49, Line 11: - [H110M-E/M.2](asus/h110m-e_m2.md)
Looks like until this port gets working and approved, the index. […]
Just don't forget to add it. Leaving this comment unresolved as a reminder.
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 3: config BOARD_SPECIFIC_OPTIONS Missing Kconfig select for the LPC TPM on the devicetree
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 19: Enable Nit: Disable
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 55: register "PchHdaVcType" = "Vc1"
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 107: 0x0 1520
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 120: 0x0 1520
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 133: 0x0 1520
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 146: 0x0 1520
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 187: [4] = 1, \ : [5] = 1, \ : [6] = 1, \ : [7] = 1, \ These are 0 for H110
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 203: # Enable CLKREQ# : register "PcieRpClkReqSupport[7]" = "1" : # Use SRCCLKREQ1# : register "PcieRpClkReqNumber[7]" = "1" Should not be needed and can be disabled
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 256: end These lone `end` words can go into the previous line
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 282: device pci 1c.4 off end # PCI Express Port 5 should be on
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 298: chip superio/nuvoton/nct5539d asrock/h110m now has some more code you might need.
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 301: rq 0x1c = 0x10 : irq 0x27 = 0x03 : irq 0x2a = 0xc0 Remove these writes. They are writing the default values, and coreboot hangs right when doing so.
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 27: /* Enable Virtual Channel 1 */ : params->PchHdaVcType = 0x1; Should be set in the devicetree
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
PS50: asrock/h110m also fills DQ and DQS map data here. Maybe you need that too.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
(1 comment)
ping
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 298: chip superio/nuvoton/nct5539d
asrock/h110m now has some more code you might need.
Please be a little more specific.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 298: chip superio/nuvoton/nct5539d
Please be a little more specific.
https://github.com/coreboot/coreboot/blob/01bfa53f772a1a5cf7caa95abc62e35579...
Lines 327 and 328
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
(1 comment)
Sorry for bringing up issues one at a time but I guess I'll commit after this one :)
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
PS50:
asrock/h110m also fills DQ and DQS map data here. Maybe you need that too.
and How can I get the DQ and DQS map data for my machine or is it identical to the ASROCK board?
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
(1 comment)
And I don't have any TPM header on my board as ASROCK H110M-DVS board.
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 3: config BOARD_SPECIFIC_OPTIONS
Missing Kconfig select for the LPC TPM on the devicetree
don't have TPM header on my board.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
(11 comments)
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 3: config BOARD_SPECIFIC_OPTIONS
don't have TPM header on my board.
Ack
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi_tables.c:
PS50: This blank file shouldn't be needed anymore
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 343: chip drivers/pc80/tpm : device pnp 4e.0 on end # TPM module : end You don't have a TPM
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 34: // CPU This comment should be removed, it says nothing useful
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 50: // Chipset specific sleep states This comment should be removed
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 51: soc/intel/skylake southbridge/intel/common
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 25: 0x0 these 0x0 should be 0
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 44: 0x00000004 just 4
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 45: 0x80860101 You don't need to repeat the value in the comment
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 46: 0x2 should be 2
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
PS50:
and How can I get the DQ and DQS map data for my machine or is it identical to the ASROCK board?
I think it's the same for DDR4, so just use the asrock values
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
PS50:
I think it's the same for DDR4, so just use the asrock values
It's for LPDDR only, likely added by accident to the Asrock board (Intel refuses to document these things). I'll check the other values.
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#51).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,251 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/51
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 50:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 26: {200, 81, 162} These are for ULT processors with soldered-down memory... I just realized that I only have documentation for mobile devices with SO-DIMM, hmmm, in such a case it would be `121, 75, 100`. Schematics could confirm this.
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 33: 100, 40, 40, 23, 40 same here, closest match: 60, 26, 20, 20, 26 (for 2x SO-DIMM)
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#52).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 21 files changed, 1,246 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/52
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 52:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 33: 100, 40, 40, 23, 40
same here, closest match: 60, 26, 20, 20, 26 (for 2x SO-DIMM)
sorry, 2x SO-DIMM was 2x per channel. but I guess your board has only 1 per channel? then it should be 50, 26, 20, 20, 26
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 45: 0x53, If your board has only 2 DIMMs, you can probably scratch 0x51 and 0x53.
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#53).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,219 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/53
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 53:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/53/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/53/src/mainboard/asus/h110m-e... PS53, Line 54: mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; : mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; : mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; : mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; Needs to change as the order changed above. Most likely:
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
i.e. 0x50 => first channel, first/only DIMM; 0x52 => second channel, first/only DIMM. please test
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#55).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,218 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/55
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 55:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
PS50:
It's for LPDDR only, likely added by accident to the Asrock board (Intel […]
So it doesn't need to be filled at all, I guess?
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 26: {200, 81, 162}
These are for ULT processors with soldered-down memory... I just realized […]
No schematics for either asus nor asrock desktop boards.
In any case, looks like SKL-S does not need RCOMP resistors.
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#56).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,220 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/56
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 56: Code-Review+1
(29 comments)
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 36: config DEVICETREE it's the default value
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 19: Enable
Nit: Disable
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 55:
register "PchHdaVcType" = "Vc1"
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 107: 0x0
1520
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 120: 0x0
1520
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 133: 0x0
1520
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 146: 0x0
1520
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 187: [4] = 1, \ : [5] = 1, \ : [6] = 1, \ : [7] = 1, \
These are 0 for H110
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 203: # Enable CLKREQ# : register "PcieRpClkReqSupport[7]" = "1" : # Use SRCCLKREQ1# : register "PcieRpClkReqNumber[7]" = "1"
Should not be needed and can be disabled
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 256: end
These lone `end` words can go into the previous line
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 282: device pci 1c.4 off end # PCI Express Port 5
should be on
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 298: chip superio/nuvoton/nct5539d
https://github. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 301: rq 0x1c = 0x10 : irq 0x27 = 0x03 : irq 0x2a = 0xc0
Remove these writes. They are writing the default values, and coreboot hangs right when doing so.
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 343: chip drivers/pc80/tpm : device pnp 4e.0 on end # TPM module : end
You don't have a TPM
Done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 203: Enable They are not enabled anymore. Might as well drop the comments
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 298: chip superio/nuvoton/nct5539d you need to indent this, though
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 300: # global : # UART A these two comments aren't needed anymore
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 51: soc/intel/skylake
southbridge/intel/common
Done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 17: */ What happened to the space here?
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 22: / And here?
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 25: 0x0
these 0x0 should be 0
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 44: 0x00000004
just 4
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 45: 0x80860101
You don't need to repeat the value in the comment
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 46: 0x2
should be 2
Done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 26: 0x0 these are just 0 as well
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 49: 0x2 these are just 2 as well
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 27: /* Enable Virtual Channel 1 */ : params->PchHdaVcType = 0x1;
Should be set in the devicetree
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 45: 0x53,
If your board has only 2 DIMMs, you can probably scratch 0x51 and 0x53.
It is the case, done.
https://review.coreboot.org/c/coreboot/+/34603/53/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/53/src/mainboard/asus/h110m-e... PS53, Line 54: mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; : mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; : mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; : mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
Needs to change as the order changed above. Most likely: […]
some intel board with two DIMMs does exactly that
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 56:
(1 comment)
Please elaborate a little on that :)
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 36: config DEVICETREE
it's the default value
Sorry?
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#57).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,217 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/57
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 57:
(7 comments)
done.
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 203: Enable
They are not enabled anymore. […]
done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 298: chip superio/nuvoton/nct5539d
you need to indent this, though
done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 300: # global : # UART A
these two comments aren't needed anymore
removed
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 17: */
What happened to the space here?
now it is there
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 22: /
And here?
done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 26: 0x0
these are just 0 as well
done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 49: 0x2
these are just 2 as well
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 57:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 36: config DEVICETREE
Sorry?
No need to re-define the default value, so this config can be removed.
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#58).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,214 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/58
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 58:
The latest result https://pastebin.com/hg83w0t6 on 10-02-2020, was able to select and load the Linux kernel only in debug mode only from an MBR mode bootable USB following the serial output as there was nothing showing on the main display other than just a blinking cursor and after that https://youtu.be/Ur95EbL4KD0, the machine restarts and that is the complete loop.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 58:
And with some tweaking, https://imgur.com/a/QZj6EHJ, though my year old USB drive is not recognized to coreboot but my 4 years old one is, So I can not guess which ones are outdated in the coreboot section and it just recognizes my HDDs and that's it, can't handle them as it appears. And that is the progress so far.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 58:
And with GOP graphics and tianocore_debug_uefi payload, https://imgur.com/VyQ7PrI and the serial output logs https://pastebin.com/BJ6pYvmK, wow and why?
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 58:
And with GOP blob, coreboot type tianocore_release also works and leads to this https://imgur.com/VyQ7PrI screen and got stuck there and the reason is in the tianocore_debug logs in my previous comment.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 58:
And with tianocore uefi payload as payload, the grub menu appears but after selecting the OS, it says, error: no suitable video mode found. -> Booting in blind mode.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 58:
And the fail log of after selecting the OS from the GRUB menu, https://pastebin.com/pTmytxjT
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 58:
And the faillog for coreboot+tcore+uefi_payload+GOP, https://pastebin.com/K05pS9fv with console=ttyS0,115200 earlyprintk=ttyS0,115200
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#59).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 18 files changed, 1,207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/59
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#60).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/60
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 60:
With some little amendments on devicetree.cb according to Nico Huber's suggestion and testing on builtin hdmi display port with coreboot+gop+tcore+uefy_payload https://pastebin.com/8hzTdcuL but it still does not trigger the DISPLAY as the tcore+coreboot_payload does with the coreboot bios logo but that sticks there and does not brings up the GRUB menu as in the former one's case though only manageable through serial output and also the USB keyboard works for the former case. So no big change or no break through so far.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 60:
Patch Set 60:
With some little amendments on devicetree.cb according to Nico Huber's suggestion and testing on builtin hdmi display port with coreboot+gop+tcore+uefy_payload https://pastebin.com/8hzTdcuL but it still does not trigger the DISPLAY as the tcore+coreboot_payload does with the coreboot bios logo but that sticks there and does not brings up the GRUB menu as in the former one's case though only manageable through serial output and also the USB keyboard works for the former case. So no big change or no break through so far.
There is difference between linux and linux-libre kernel booting, a bit minimal log https://pastebin.com/mQG1LeJx
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 60:
Patch Set 60:
Patch Set 60:
With some little amendments on devicetree.cb according to Nico Huber's suggestion and testing on builtin hdmi display port with coreboot+gop+tcore+uefy_payload https://pastebin.com/8hzTdcuL but it still does not trigger the DISPLAY as the tcore+coreboot_payload does with the coreboot bios logo but that sticks there and does not brings up the GRUB menu as in the former one's case though only manageable through serial output and also the USB keyboard works for the former case. So no big change or no break through so far.
There is difference between linux and linux-libre kernel booting, a bit minimal log https://pastebin.com/mQG1LeJx
The current log with initcall_debug and earlyprintk kernel parameters, https://pastebin.com/Aw3J1n62
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#62).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/62
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 62:
Maybe
[ OK ] Started Load/Save Random Seed.
`random.trust_cpu=on` will get you further.
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#63).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/63
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 63:
(1 comment)
Can it be made a variant of the board it is based on?
https://review.coreboot.org/c/coreboot/+/34603/63//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/63//COMMIT_MSG@7 PS63, Line 7: mainboard/asus: Add ASUS H110M-E/M.2 mainboard mb/asus: Add Asus H110M-E/M.2
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#64).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/64
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
(1 comment)
.
https://review.coreboot.org/c/coreboot/+/34603/63//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/63//COMMIT_MSG@7 PS63, Line 7: mainboard/asus: Add ASUS H110M-E/M.2 mainboard
mb/asus: Add Asus H110M-E/M. […]
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
Patch Set 63:
(1 comment)
Can it be made a variant of the board it is based on?
Paul, it is based on a mainboard of a different vendor. I don't think variants cover such usecases very well... Also, it would make it not appear on board_status.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
Patch Set 64:
Patch Set 63:
(1 comment)
Can it be made a variant of the board it is based on?
Paul, it is based on a mainboard of a different vendor. I don't think variants cover such usecases very well... Also, it would make it not appear on board_status.
Oh, I just saw the H110M. Thanks.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 20: ACTIVE_AC Does your system use fan for CPU cooling? If not, these *_ACTIVE_ACx are not required.
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 20: ACTIVE_AC
Does your system use fan for CPU cooling? If not, these *_ACTIVE_ACx are not required.
You mean chassis fan other than that mounted over processor's heat sink cooling?
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
And the log of successful CLI mode boot, https://pastebin.com/1rtasZi8 kernel parameters used: set 1: random.trust_cpu=on initcall_debug console=tty0 console=ttyS0,115200 earlyprintk=ttyS0,115200 (halts) set 2: nomodeset initcall_debug console=tty0 console=ttyS0,115200 earlyprintk=ttyS0,115200 (boots)
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
And git diff, https://pastebin.com/uZwxfjzM
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
Ok, a clean one, https://pastebin.com/BZtnmEZS
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
https://imgur.com/a/6v4ZD6G, coreboot_tcore_debug_coreboot_payload_gop but only boots with nomodeset kernel parameter into CLI mode.
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
Patch Set 64:
https://imgur.com/a/6v4ZD6G, coreboot_tcore_debug_coreboot_payload_gop but only boots with nomodeset kernel parameter into CLI mode.
Only windows booted after resetting all the devices/hardwares(ironic) but in case of Linux, re-installed the kernel in CLI mode but didn't change anything.
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
Patch Set 64:
Patch Set 64:
https://imgur.com/a/6v4ZD6G, coreboot_tcore_debug_coreboot_payload_gop but only boots with nomodeset kernel parameter into CLI mode.
Only windows booted after resetting all the devices/hardwares(ironic) but in case of Linux, re-installed the kernel in CLI mode but didn't change anything.
And only GOP+card combo triggers the Display.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 20: ACTIVE_AC
You mean chassis fan other than that mounted over processor's heat sink cooling?
This is a desktop mainboard, so it has a CPU fan. I'm not sure if DPTF is meant to be used on desktops though.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
(18 comments)
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 36: config DEVICETREE
No need to re-define the default value, so this config can be removed.
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi_tables.c:
PS50:
This blank file shouldn't be needed anymore
Done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 203: Enable
done
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 204: register "PcieRpClkReqNumber[7]" = "0" This isn't needed if Clock Request is disabled
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 34: // CPU
This comment should be removed, it says nothing useful
*poke*
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 50: // Chipset specific sleep states
This comment should be removed
*poke*
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 17: */
now it is there
Done
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 22: /
done
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 34: // CPU This comment should go away.
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 50: // Chipset specific sleep states This one as well
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 26: 0x0
done
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 27: 0x0 Um, these ones should also be updated. All the `AZALIA_PIN_CFG(0x0` should just use `0`
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 52: 0x2 2
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 55: 0x2 2
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
PS50:
So it doesn't need to be filled at all, I guess?
Ack
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 26: {200, 81, 162}
No schematics for either asus nor asrock desktop boards. […]
LGA1151 CPUs have the RCOMP resistors on the underside of the CPU, and their values are indeed 121, 75 and 100.
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 33: 100, 40, 40, 23, 40
sorry, 2x SO-DIMM was 2x per channel. but I guess your board has only 1 per […]
Done, I guess?
https://review.coreboot.org/c/coreboot/+/34603/53/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/53/src/mainboard/asus/h110m-e... PS53, Line 54: mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; : mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; : mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; : mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
some intel board with two DIMMs does exactly that
Done, I guess.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 64:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 298: chip superio/nuvoton/nct5539d
done
Ack
https://review.coreboot.org/c/coreboot/+/34603/56/src/mainboard/asus/h110m-e... PS56, Line 300: # global : # UART A
removed
Ack
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#65).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/65
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 65:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 20: ACTIVE_AC
This is a desktop mainboard, so it has a CPU fan. […]
Ack
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 204: register "PcieRpClkReqNumber[7]" = "0"
This isn't needed if Clock Request is disabled
Ack
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 34: // CPU
This comment should go away.
Ack
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 50: // Chipset specific sleep states
This one as well
Ack
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 27: 0x0
Um, these ones should also be updated. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 52: 0x2
2
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 55: 0x2
2
Done
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 65:
Ok, libgfxinit+Graphics card works for both seabios and tianocore but for seabios MBR/DOS partition GRUB sucks and GPT GRUB works better, installed the whole operating system (archlinux and then also Parabole) over coreboot (with nomodeset kernel parameter booting into CLI) but there's something off about coreboot as it halts during "found /dev/ttyS0" in normal mode and 7 out of 10 times the booting process halts at FspSiliconInit call.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 65:
Patch Set 65:
Ok, libgfxinit+Graphics card works for both seabios and tianocore but for seabios MBR/DOS partition GRUB sucks and GPT GRUB works better, installed the whole operating system (archlinux and then also Parabole) over coreboot (with nomodeset kernel parameter booting into CLI) but there's something off about coreboot as it halts during "found /dev/ttyS0" in normal mode and 7 out of 10 times the booting process halts at FspSiliconInit call.
The serial port stuff is very likely due to broken ACPI code. Patrick Rudolph wants to use a SSDT generator, see CB:38864 as an example.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 65:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 20: ACTIVE_AC
Ack
Um, Sumeet was referring to all the `DPTF_CPU_ACTIVE_ACx` lines, not just the first one...
Also, I would still want to know if desktop boards are meant to use DPTF.
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 34: // CPU
*poke*
Done
https://review.coreboot.org/c/coreboot/+/34603/50/src/mainboard/asus/h110m-e... PS50, Line 50: // Chipset specific sleep states
*poke*
Done
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 66:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 20: ACTIVE_AC
Um, Sumeet was referring to all the `DPTF_CPU_ACTIVE_ACx` lines, not just the first one... […]
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 204: register "PcieRpClkReqNumber[7]" = "0"
Ack
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 34: // CPU
Ack
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 50: // Chipset specific sleep states
Ack
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 27: 0x0
Done
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 52: 0x2
Done
Done
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 55: 0x2
Done
Done
Hello Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#67).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,203 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/67
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 67:
Patch Set 65:
Patch Set 65:
Ok, libgfxinit+Graphics card works for both seabios and tianocore but for seabios MBR/DOS partition GRUB sucks and GPT GRUB works better, installed the whole operating system (archlinux and then also Parabole) over coreboot (with nomodeset kernel parameter booting into CLI) but there's something off about coreboot as it halts during "found /dev/ttyS0" in normal mode and 7 out of 10 times the booting process halts at FspSiliconInit call.
The serial port stuff is very likely due to broken ACPI code. Patrick Rudolph wants to use a SSDT generator, see CB:38864 as an example.
Waiting to test that.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#68).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/68
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#69).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/69
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(5 comments)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 82: # VR Settings Configuration for 5 Domains : #+----------------+-------+-------+-------------+-------------+-------+ : #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | : #+----------------+-------+-------+-------------+-------------+-------+ : #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | : #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | : #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | : #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | : #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | : #| ImonSlope | 0 | 0 | 0 | 0 | 0 | : #| ImonOffset | 0 | 0 | 0 | 0 | 0 | : #| IccMax* | 0 | 0 | 0 | 0 | 0 | : #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | : #+----------------+-------+-------+-------------+-------------+-------+ : #[*] Installed automatically for KBL-S and KBL-DT CPUs in the vr_config.c : #+----------------+-------+-------+-------------+-------------+-------+ : register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(4), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_IA_CORE]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_UNSLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0 ,\ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_SLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : that's all default, right? then this can be dropped completely
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 252: device pci 00.0 on end # Host Bridge : device pci 01.0 on end # PEG : device pci 02.0 on end # Integrated Graphics Device : device pci 14.0 on end # USB xHCI : device pci 14.1 off end # USB xDCI (OTG) : device pci 14.2 on end # Thermal Subsystem : device pci 15.0 off end # I2C #0 : device pci 15.1 off end # I2C #1 : device pci 15.2 off end # I2C #2 : device pci 15.3 off end # I2C #3 : device pci 16.0 on end # Management Engine Interface 1 : device pci 16.1 off end # Management Engine Interface 2 : device pci 16.2 off end # Management Engine IDE-R : device pci 16.3 off end # Management Engine KT Redirection : device pci 16.4 off end # Management Engine Interface 3 : device pci 17.0 on end # SATA : device pci 19.0 off end # UART #2 : device pci 19.1 off end # I2C #5 : device pci 19.2 off end # I2C #4 : device pci 1c.0 on end # PCI Express Port 1 : device pci 1c.1 off end # PCI Express Port 2 : device pci 1c.2 off end # PCI Express Port 3 : device pci 1c.3 off end # PCI Express Port 4 : device pci 1c.4 on end # PCI Express Port 5 : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 on end # PCI Express Port 8 : device pci 1d.0 on end # PCI Express Port 9 : device pci 1d.1 off end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 : device pci 1e.0 off end # UART #0 : device pci 1e.1 off end # UART #1 : device pci 1e.2 off end # GSPI #0 : device pci 1e.3 off end # GSPI #1 : device pci 1e.4 off end # eMMC : device pci 1e.5 off end # SDIO : device pci 1e.6 off end # SDCard : device pci 1f.0 on # LPC bridge tabs are your friend :)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 305: evice pnp 2e.6 off end # CIR : device pnp 2e.7 off end # GPIO7 : device pnp 2e.107 off end # GPIO8 : device pnp 2e.8 off end # WDT : device pnp 2e.108 off end # GPIO0 : device pnp 2e.308 off end # GPIO base : device pnp 2e.408 off end # WDTMEM : device pnp 2e.9 off end # GPIO2 : device pnp 2e.109 off end # GPIO3 : device pnp 2e.209 off end # GPIO4 : device pnp 2e.309 off end # GPIO5 : device pnp 2e.a on end # ACPI : device pnp 2e.b off # HWM, LED nit: this could be formatted to enhance readability like the ones from 322 😊
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 22: #define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ not really needed, just use _PAD_CFG_STRUCT below
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100 this will trigger an error "gpio_pad_reset_config_override: Logical to Chipset mapping not found". due to the reset mapping; replace 0 with 0x0... with 0xc for any GPP_* (but not GPD*!)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 17: subdirs-y += spd what's that?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 17: subdirs-y += spd
what's that?
Garbage!
(it is only necessary when using memory-down)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 252: device pci 00.0 on end # Host Bridge : device pci 01.0 on end # PEG : device pci 02.0 on end # Integrated Graphics Device : device pci 14.0 on end # USB xHCI : device pci 14.1 off end # USB xDCI (OTG) : device pci 14.2 on end # Thermal Subsystem : device pci 15.0 off end # I2C #0 : device pci 15.1 off end # I2C #1 : device pci 15.2 off end # I2C #2 : device pci 15.3 off end # I2C #3 : device pci 16.0 on end # Management Engine Interface 1 : device pci 16.1 off end # Management Engine Interface 2 : device pci 16.2 off end # Management Engine IDE-R : device pci 16.3 off end # Management Engine KT Redirection : device pci 16.4 off end # Management Engine Interface 3 : device pci 17.0 on end # SATA : device pci 19.0 off end # UART #2 : device pci 19.1 off end # I2C #5 : device pci 19.2 off end # I2C #4 : device pci 1c.0 on end # PCI Express Port 1 : device pci 1c.1 off end # PCI Express Port 2 : device pci 1c.2 off end # PCI Express Port 3 : device pci 1c.3 off end # PCI Express Port 4 : device pci 1c.4 on end # PCI Express Port 5 : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 on end # PCI Express Port 8 : device pci 1d.0 on end # PCI Express Port 9 : device pci 1d.1 off end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 : device pci 1e.0 off end # UART #0 : device pci 1e.1 off end # UART #1 : device pci 1e.2 off end # GSPI #0 : device pci 1e.3 off end # GSPI #1 : device pci 1e.4 off end # eMMC : device pci 1e.5 off end # SDIO : device pci 1e.6 off end # SDCard : device pci 1f.0 on # LPC bridge
tabs are your friend :)
What he means: Use tabs to align these things.
device pci 14.2 on end <TAB HERE> # Thermal Subsystem device pci 15.0 off end <TAB HERE> # I2C #0
Note that there are two spaces after an `on` keyword: that way, the `end` keywords are aligned 😄
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 305: evice pnp 2e.6 off end # CIR : device pnp 2e.7 off end # GPIO7 : device pnp 2e.107 off end # GPIO8 : device pnp 2e.8 off end # WDT : device pnp 2e.108 off end # GPIO0 : device pnp 2e.308 off end # GPIO base : device pnp 2e.408 off end # WDTMEM : device pnp 2e.9 off end # GPIO2 : device pnp 2e.109 off end # GPIO3 : device pnp 2e.209 off end # GPIO4 : device pnp 2e.309 off end # GPIO5 : device pnp 2e.a on end # ACPI : device pnp 2e.b off # HWM, LED
nit: this could be formatted to enhance readability like the ones from 322 😊
(clarification: `322` refers to the line number of this file.)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
this will trigger an error "gpio_pad_reset_config_override: Logical […]
Good catch: the log is spammed with those. Can't we use proper macros instead?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
Good catch: the log is spammed with those. […]
We could... but Maxims tool is still lacking some registers
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
We could... […]
Some more specific examples please.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
Some more specific examples please.
Pretty easy here :-)
Example: This H110_PAD_DW0_DW1_CFG(GPP_F22, 0x04000100, 0x0000103b), /* GPIO */ becomes H110_PAD_DW0_DW1_CFG(GPP_F22, 0xc4000100, 0x0000103b), /* GPIO */
Do this for all GPP_* but not for GPD_*
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
Pretty easy here :-) […]
but in line 22, you already said " just use _PAD_CFG_STRUCT below", so H110_PAD_DW0_DW1_CFG supposed to become "_PAD_CFG_STRUCT", isn't it?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
but in line 22, you already said " just use _PAD_CFG_STRUCT below", so H110_PAD_DW0_DW1_CFG supposed […]
woops, was just copy pasta, so yes ;-)
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(6 comments)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 17: subdirs-y += spd
Garbage!
(it is only necessary when using memory-down)
removed.
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 82: # VR Settings Configuration for 5 Domains : #+----------------+-------+-------+-------------+-------------+-------+ : #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | : #+----------------+-------+-------+-------------+-------------+-------+ : #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | : #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | : #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | : #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | : #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | : #| ImonSlope | 0 | 0 | 0 | 0 | 0 | : #| ImonOffset | 0 | 0 | 0 | 0 | 0 | : #| IccMax* | 0 | 0 | 0 | 0 | 0 | : #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | : #+----------------+-------+-------+-------------+-------------+-------+ : #[*] Installed automatically for KBL-S and KBL-DT CPUs in the vr_config.c : #+----------------+-------+-------+-------------+-------------+-------+ : register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(4), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_IA_CORE]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_UNSLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0 ,\ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_SLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" :
that's all default, right? then this can be dropped completely
Done
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 252: device pci 00.0 on end # Host Bridge : device pci 01.0 on end # PEG : device pci 02.0 on end # Integrated Graphics Device : device pci 14.0 on end # USB xHCI : device pci 14.1 off end # USB xDCI (OTG) : device pci 14.2 on end # Thermal Subsystem : device pci 15.0 off end # I2C #0 : device pci 15.1 off end # I2C #1 : device pci 15.2 off end # I2C #2 : device pci 15.3 off end # I2C #3 : device pci 16.0 on end # Management Engine Interface 1 : device pci 16.1 off end # Management Engine Interface 2 : device pci 16.2 off end # Management Engine IDE-R : device pci 16.3 off end # Management Engine KT Redirection : device pci 16.4 off end # Management Engine Interface 3 : device pci 17.0 on end # SATA : device pci 19.0 off end # UART #2 : device pci 19.1 off end # I2C #5 : device pci 19.2 off end # I2C #4 : device pci 1c.0 on end # PCI Express Port 1 : device pci 1c.1 off end # PCI Express Port 2 : device pci 1c.2 off end # PCI Express Port 3 : device pci 1c.3 off end # PCI Express Port 4 : device pci 1c.4 on end # PCI Express Port 5 : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 on end # PCI Express Port 8 : device pci 1d.0 on end # PCI Express Port 9 : device pci 1d.1 off end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 : device pci 1e.0 off end # UART #0 : device pci 1e.1 off end # UART #1 : device pci 1e.2 off end # GSPI #0 : device pci 1e.3 off end # GSPI #1 : device pci 1e.4 off end # eMMC : device pci 1e.5 off end # SDIO : device pci 1e.6 off end # SDCard : device pci 1f.0 on # LPC bridge
What he means: Use tabs to align these things. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 305: evice pnp 2e.6 off end # CIR : device pnp 2e.7 off end # GPIO7 : device pnp 2e.107 off end # GPIO8 : device pnp 2e.8 off end # WDT : device pnp 2e.108 off end # GPIO0 : device pnp 2e.308 off end # GPIO base : device pnp 2e.408 off end # WDTMEM : device pnp 2e.9 off end # GPIO2 : device pnp 2e.109 off end # GPIO3 : device pnp 2e.209 off end # GPIO4 : device pnp 2e.309 off end # GPIO5 : device pnp 2e.a on end # ACPI : device pnp 2e.b off # HWM, LED
(clarification: `322` refers to the line number of this file. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 22: #define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
not really needed, just use _PAD_CFG_STRUCT below
Done
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
woops, was just copy pasta, so yes ;-)
Done
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#70).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,127 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/70
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#71).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,128 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/71
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 22: #define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
Done
oops, renders the code unstable, so had to revert this change but replaced the gpp ones from 0x0 to 0xc, gonna test now, wish me luck.
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/64/src/mainboard/asus/h110m-e... PS64, Line 20: ACTIVE_AC
Done
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/70/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/70/src/mainboard/asus/h110m-e... PS70, Line 22: #define _PAD_CFG_STRUCT(val, config0, config1) lolwhat? :D :P
remove that line, then you can use _PAD_CFG_STRUCT below with breaking your code ;)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 22: #define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
oops, renders the code unstable, so had to revert this change but replaced the gpp ones from 0x0 to […]
see https://review.coreboot.org/c/coreboot/+/34603/70/src/mainboard/asus/h110m-e...
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... PS54, Line 182: \ not needed
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... PS54, Line 183: \ same
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... PS54, Line 184: \ same ... ;)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 125: # Set params for PEG 0:1:0 : register "Peg0MaxLinkWidth" = "Peg0_x16" : # Configure PCIe clockgen in PCH : # PEG0 uses SRCCLKREQ0 and CLKSRC0 : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : register "PcieRpClkSrcNumber[0]" = "0" : : # Enable Root port 8(x1) for LAN. : register "PcieRpEnable[7]" = "1" : register "PcieRpClkReqSupport[7]" = "0" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[7]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[7]" = "1" : # Use CLK SRC 1 : register "PcieRpClkSrcNumber[7]" = "1" : : # Enable Root port 5 (x1) for PCIE slot. : register "PcieRpEnable[4]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[4]" = "1" : # Use SRCCLKREQ2# : register "PcieRpClkReqNumber[4]" = "2" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[4]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[4]" = "1" : # Use CLK SRC 2 : register "PcieRpClkSrcNumber[4]" = "2" : # Use Hot Plug subsystem : register "PcieRpHotPlug[4]" = "1" : : # Enable Root port 9(x1) for PCIE slot. : register "PcieRpEnable[8]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[8]" = "1" : # Use SRCCLKREQ3# : register "PcieRpClkReqNumber[8]" = "3" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[8]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[8]" = "1" : # Use CLK SRC 3 : register "PcieRpClkSrcNumber[8]" = "3" : # Use Hot Plug subsystem : register "PcieRpHotPlug[8]" = "1" pretty hard to read; maybe align this by tabs and put the comments in line?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/cmos.default:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 5: add hyper_threading?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 71: Code-Review+1
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#72).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/72
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 72:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/cmos.default:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 5:
add hyper_threading?
Ack
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 125: # Set params for PEG 0:1:0 : register "Peg0MaxLinkWidth" = "Peg0_x16" : # Configure PCIe clockgen in PCH : # PEG0 uses SRCCLKREQ0 and CLKSRC0 : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : register "PcieRpClkSrcNumber[0]" = "0" : : # Enable Root port 8(x1) for LAN. : register "PcieRpEnable[7]" = "1" : register "PcieRpClkReqSupport[7]" = "0" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[7]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[7]" = "1" : # Use CLK SRC 1 : register "PcieRpClkSrcNumber[7]" = "1" : : # Enable Root port 5 (x1) for PCIE slot. : register "PcieRpEnable[4]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[4]" = "1" : # Use SRCCLKREQ2# : register "PcieRpClkReqNumber[4]" = "2" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[4]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[4]" = "1" : # Use CLK SRC 2 : register "PcieRpClkSrcNumber[4]" = "2" : # Use Hot Plug subsystem : register "PcieRpHotPlug[4]" = "1" : : # Enable Root port 9(x1) for PCIE slot. : register "PcieRpEnable[8]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[8]" = "1" : # Use SRCCLKREQ3# : register "PcieRpClkReqNumber[8]" = "3" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[8]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[8]" = "1" : # Use CLK SRC 3 : register "PcieRpClkSrcNumber[8]" = "3" : # Use Hot Plug subsystem : register "PcieRpHotPlug[8]" = "1"
pretty hard to read; maybe align this by tabs and put the comments in line?
For you, anything.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#73).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/73
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 73: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 125: # Set params for PEG 0:1:0 : register "Peg0MaxLinkWidth" = "Peg0_x16" : # Configure PCIe clockgen in PCH : # PEG0 uses SRCCLKREQ0 and CLKSRC0 : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : register "PcieRpClkSrcNumber[0]" = "0" : : # Enable Root port 8(x1) for LAN. : register "PcieRpEnable[7]" = "1" : register "PcieRpClkReqSupport[7]" = "0" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[7]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[7]" = "1" : # Use CLK SRC 1 : register "PcieRpClkSrcNumber[7]" = "1" : : # Enable Root port 5 (x1) for PCIE slot. : register "PcieRpEnable[4]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[4]" = "1" : # Use SRCCLKREQ2# : register "PcieRpClkReqNumber[4]" = "2" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[4]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[4]" = "1" : # Use CLK SRC 2 : register "PcieRpClkSrcNumber[4]" = "2" : # Use Hot Plug subsystem : register "PcieRpHotPlug[4]" = "1" : : # Enable Root port 9(x1) for PCIE slot. : register "PcieRpEnable[8]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[8]" = "1" : # Use SRCCLKREQ3# : register "PcieRpClkReqNumber[8]" = "3" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[8]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[8]" = "1" : # Use CLK SRC 3 : register "PcieRpClkSrcNumber[8]" = "3" : # Use Hot Plug subsystem : register "PcieRpHotPlug[8]" = "1"
For you, anything.
:-)
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 73:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 249: off on ?
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 29: Analog eDP https://review.coreboot.org/c/coreboot/+/38921
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#74).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/74
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 74:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/cmos.default:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 5:
Ack
Done
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 249: off
on ?
Done
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/34603/71/src/mainboard/asus/h110m-e... PS71, Line 29: Analog
eDP […]
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 74: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/73/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/73/src/mainboard/asus/h110m-e... PS73, Line 203: tab
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#75).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/75
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 75:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/73/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/73/src/mainboard/asus/h110m-e... PS73, Line 203:
tab
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 75: Code-Review+1
+2 as soon as the remaining comments are resolved
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 75:
Patch Set 75: Code-Review+1
+2 as soon as the remaining comments are resolved
Also I have to include the Documentation of the board on the to be accepted patch, So there will be another patch with Documentation if it is to be accepted/merged.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 75: Code-Review+1
Patch Set 75:
Patch Set 75: Code-Review+1
+2 as soon as the remaining comments are resolved
Also I have to include the Documentation of the board on the to be accepted patch, So there will be another patch with Documentation if it is to be accepted/merged.
We can add documentation on a separate change. I would not delay merging this change.
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 75:
Patch Set 75: Code-Review+1
Patch Set 75:
Patch Set 75: Code-Review+1
+2 as soon as the remaining comments are resolved
Also I have to include the Documentation of the board on the to be accepted patch, So there will be another patch with Documentation if it is to be accepted/merged.
We can add documentation on a separate change. I would not delay merging this change.
If you say so.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#76).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,103 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/76
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 76:
(6 comments)
As the Documentation will be on a different commit.
https://review.coreboot.org/c/coreboot/+/34603/49/Documentation/mainboard/in... File Documentation/mainboard/index.md:
https://review.coreboot.org/c/coreboot/+/34603/49/Documentation/mainboard/in... PS49, Line 11: - [H110M-E/M.2](asus/h110m-e_m2.md)
Just don't forget to add it. Leaving this comment unresolved as a reminder.
Done
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... PS54, Line 182: \
not needed
Done
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... PS54, Line 183: \
same
Done
https://review.coreboot.org/c/coreboot/+/34603/54/src/mainboard/asus/h110m-e... PS54, Line 184: \
same ... […]
Done
https://review.coreboot.org/c/coreboot/+/34603/70/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/70/src/mainboard/asus/h110m-e... PS70, Line 22: #define _PAD_CFG_STRUCT(val, config0, config1)
lolwhat? :D :P […]
Done
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 22: #define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
see https://review.coreboot.org/c/coreboot/+/34603/70/src/mainboard/asus/h110m-e.... […]
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 76:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 117: \ well... unneeded.. and all the following lines, too
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 246: still no tab ;)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 76:
(6 comments)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 71: huh? what's that?
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 205: chip superio/nuvoton/nct5539d : device pnp 2e.2 on # UART A : misaligned
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 188: that's not intended, is it?
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 234: DDPB_CTRLDATA why not at EOL?
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 236: DDPC_CTRLCLK same
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 238: DDPC_CTRLDATA same
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 76: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 76:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 234: DDPB_CTRLDATA
why not at EOL?
They fit in 96 characters, maybe your gitconfig is outdated
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 257: /* SUSWARN#/SUSPWRDNACK */ Isn't this the same comment as on the line below?
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#77).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,099 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/77
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#78).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,098 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/78
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#79).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,098 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/79
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#80).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,098 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/80
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#81).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,098 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/81
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 81:
(11 comments)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 205: chip superio/nuvoton/nct5539d : device pnp 2e.2 on # UART A :
misaligned
Um, no...
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 204: device pnp 2e.ff on # passes SIO base addr to SSDT gen Indent with an extra tab
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 205: chip superio/nuvoton/nct5539d Two extra tabs
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 206: device pnp 2e.2 on # UART A Three extra tabs
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 244: end # superio/nuvoton/nct5539d Two tabs
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 245: end # SSDT gen One tab
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 188:
that's not intended, is it?
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 234: DDPB_CTRLDATA
They fit in 96 characters, maybe your gitconfig is outdated
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 236: DDPC_CTRLCLK
same
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 238: DDPC_CTRLDATA
same
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 257: /* SUSWARN#/SUSPWRDNACK */
Isn't this the same comment as on the line below?
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 81:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 205: chip superio/nuvoton/nct5539d : device pnp 2e.2 on # UART A :
Um, no...
chip superio/common
device pnp 2e.ff on # passes SIO base addr to SSDT gen
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 81:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 205: chip superio/nuvoton/nct5539d : device pnp 2e.2 on # UART A :
chip superio/common […]
see what you commented :D https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e...
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 81:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 4: * Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com move to AUTHORS and add SPDX header; same for all other files
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#82).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,136 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/82
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 82:
(6 comments)
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 204: device pnp 2e.ff on # passes SIO base addr to SSDT gen
Indent with an extra tab
Done
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 205: chip superio/nuvoton/nct5539d
Two extra tabs
Done
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 206: device pnp 2e.2 on # UART A
Three extra tabs
Done
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 244: end # superio/nuvoton/nct5539d
Two tabs
Done
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 245: end # SSDT gen
One tab
Done
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/81/src/mainboard/asus/h110m-e... PS81, Line 4: * Copyright (C) 2019 Pavel Sayekat pavelsayekat@gmail.com
move to AUTHORS and add SPDX header; same for all other files
Done
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#83).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 1,140 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/83
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 83:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 71:
huh? what's that?
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 117: \
well... unneeded.. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 205: chip superio/nuvoton/nct5539d : device pnp 2e.2 on # UART A :
see what you commented :D https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 246:
still no tab ;)
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 83:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 15: * Authors: uhm, nope. move to AUTHORS file. same for all other files
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 83:
(12 comments)
Please, don't just copy and paste things around...
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/bootblock.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/cmos.layout:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 27: AZALIA_SUBVENDOR(0, 0x10438445), AZALIA_PIN_CFG(0, 0x11, 0x40000000), What happened here? Why aren't the AZALIA_PIN_CFG statements on a single line?
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: later The original file was never GPL-2.0-or-later, it was GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 4: This file is part of the coreboot project. Only keep this line of the entire comment block.
/* This file is part of the coreboot project. */
Please do this for ALL files
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 19: _GPIO_DVS_H This symbol was from the H110M-DVS. Maybe change it to match your board?
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later GPL-2.0-only
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 83:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 71:
Done
Nope.
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 213: device pnp 2e.5 on # PS/2 KBC : io 0x60 = 0x0060 : io 0x62 = 0x0064 : irq 0x70 = 1 # Keyboard : irq 0x72 = 12 # Mouse : end : device pnp 2e.6 off end # CIR : device pnp 2e.7 off end # GPIO7 : device pnp 2e.107 off end # GPIO8 : device pnp 2e.8 off end # WDT : device pnp 2e.108 off end # GPIO0 : device pnp 2e.308 off end # GPIO base : device pnp 2e.408 off end # WDTMEM : device pnp 2e.9 off end # GPIO2 : device pnp 2e.109 off end # GPIO3 : device pnp 2e.209 off end # GPIO4 : device pnp 2e.309 off end # GPIO5 : device pnp 2e.a on end # ACPI : device pnp 2e.b on # HWM, LED : io 0x60 = 0x0290 : io 0x62 = 0 : irq 0x70 = 0 : end : device pnp 2e.d off end # BCLK, WDT2, WDT_MEM : device pnp 2e.e off end # CIR wake-up : device pnp 2e.f off end # GPIO PP/OD : device pnp 2e.14 off end # SVID, Port 80 UART : device pnp 2e.16 off end # DS5 : device pnp 2e.116 off end # DS3 : device pnp 2e.316 off end # PCHDSW : device pnp 2e.416 off end # DSWWOPT : device pnp 2e.516 off end # DS3OPT : device pnp 2e.616 off end # DSDSS : device pnp 2e.716 off end # DSPU These need to be indented one more tab
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#84).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 937 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/84
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 84:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 71:
Nope.
oops, that was not intended. thx for reopening
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#85).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 944 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/85
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#86).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 929 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/86
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 86:
(15 comments)
I don't know..
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/bootblock.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/cmos.layout:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/76/src/mainboard/asus/h110m-e... PS76, Line 71:
oops, that was not intended. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 213: device pnp 2e.5 on # PS/2 KBC : io 0x60 = 0x0060 : io 0x62 = 0x0064 : irq 0x70 = 1 # Keyboard : irq 0x72 = 12 # Mouse : end : device pnp 2e.6 off end # CIR : device pnp 2e.7 off end # GPIO7 : device pnp 2e.107 off end # GPIO8 : device pnp 2e.8 off end # WDT : device pnp 2e.108 off end # GPIO0 : device pnp 2e.308 off end # GPIO base : device pnp 2e.408 off end # WDTMEM : device pnp 2e.9 off end # GPIO2 : device pnp 2e.109 off end # GPIO3 : device pnp 2e.209 off end # GPIO4 : device pnp 2e.309 off end # GPIO5 : device pnp 2e.a on end # ACPI : device pnp 2e.b on # HWM, LED : io 0x60 = 0x0290 : io 0x62 = 0 : irq 0x70 = 0 : end : device pnp 2e.d off end # BCLK, WDT2, WDT_MEM : device pnp 2e.e off end # CIR wake-up : device pnp 2e.f off end # GPIO PP/OD : device pnp 2e.14 off end # SVID, Port 80 UART : device pnp 2e.16 off end # DS5 : device pnp 2e.116 off end # DS3 : device pnp 2e.316 off end # PCHDSW : device pnp 2e.416 off end # DSWWOPT : device pnp 2e.516 off end # DS3OPT : device pnp 2e.616 off end # DSDSS : device pnp 2e.716 off end # DSPU
These need to be indented one more tab
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 27: AZALIA_SUBVENDOR(0, 0x10438445), AZALIA_PIN_CFG(0, 0x11, 0x40000000),
What happened here? Why aren't the AZALIA_PIN_CFG statements on a single line?
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: later
The original file was never GPL-2.0-or-later, it was GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 4: This file is part of the coreboot project.
Only keep this line of the entire comment block. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 15: * Authors:
uhm, nope. move to AUTHORS file. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 19: _GPIO_DVS_H
This symbol was from the H110M-DVS. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/romstage.c:
https://review.coreboot.org/c/coreboot/+/34603/83/src/mainboard/asus/h110m-e... PS83, Line 1: GPL-2.0-or-later
GPL-2. […]
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 86: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 86:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/86//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/86//COMMIT_MSG@9 PS86, Line 9: This port is based on the Asrock H110M Please add a dot/period at the end of sentences.
https://review.coreboot.org/c/coreboot/+/34603/86//COMMIT_MSG@10 PS86, Line 10: As there is no documentation added, please add a summary of the working and non-working things to the commit message.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#87).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard. ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard.
This port is based on the Asrock H110M.
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 929 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/87
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard. ......................................................................
Patch Set 87:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/86//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/86//COMMIT_MSG@9 PS86, Line 9: This port is based on the Asrock H110M
Please add a dot/period at the end of sentences.
Done
https://review.coreboot.org/c/coreboot/+/34603/86//COMMIT_MSG@10 PS86, Line 10:
As there is no documentation added, please add a summary of the working and non-working things to th […]
Ah, I6c5aad50b513935eab70b502df1d95fb3413fa6b.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard. ......................................................................
Patch Set 87:
(16 comments)
https://review.coreboot.org/c/coreboot/+/34603/87//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/87//COMMIT_MSG@7 PS87, Line 7: . No period here
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 49: MAINBOARD_POWER_ON_AFTER_POWER_FAIL This isn't necessary
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
PS87: I still want to see if this is working at all.
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 9: B0D4 This device is not enabled in your devicetree.cb, I doubt this will work...
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/cmos.layout:
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 8: #0 8 r 0 seconds : #8 8 r 0 alarm_seconds : #16 8 r 0 minutes : #24 8 r 0 alarm_minutes : #32 8 r 0 hours : #40 8 r 0 alarm_hours : #48 8 r 0 day_of_week : #56 8 r 0 day_of_month : #64 8 r 0 month : #72 8 r 0 year : # ----------------------------------------------------------------- : # Status Register A : #80 4 r 0 rate_select : #84 3 r 0 REF_Clock : #87 1 r 0 UIP : # ----------------------------------------------------------------- : # Status Register B : #88 1 r 0 auto_switch_DST : #89 1 r 0 24_hour_mode : #90 1 r 0 binary_values_enable : #91 1 r 0 square-wave_out_enable : #92 1 r 0 update_finished_enable : #93 1 r 0 alarm_interrupt_enable : #94 1 r 0 periodic_interrupt_enable : #95 1 r 0 disable_clock_updates : # ----------------------------------------------------------------- : # Status Register C : #96 4 r 0 status_c_rsvd : #100 1 r 0 uf_flag : #101 1 r 0 af_flag : #102 1 r 0 pf_flag : #103 1 r 0 irqf_flag : # ----------------------------------------------------------------- : # Status Register D : #104 7 r 0 status_d_rsvd : #111 1 r 0 valid_cmos_ram : # ----------------------------------------------------------------- : # Diagnostic Status Register : #112 8 r 0 diag_rsvd1 : : # ----------------------------------------------------------------- Remove these
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 49: reserved_memory KEEP this line!
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 50: #120 264 r 0 unused Remove this one
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 56: #390 2 r 0 unused? Remove
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 60: #392 3 r 0 unused Remove
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 62: #399 1 r 0 unused Remove
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 66: #401 7 r 0 unused Remove
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 69: 408 1 e 1 nmi Remove ("nmi" is unused in skylake)
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 71: #411 5 r 0 unused Remove
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 73: # coreboot config options: bootloader : #Used by ChromeOS: : 416 128 r 0 vbnv : #544 440 r 0 unused : : # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3 Remove
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 84: #1000 24 r 0 amd_reserved Remove
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 91: 1 0 Disable : 1 1 Enable Remove
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#88).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M.
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 20 files changed, 929 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/88
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 88:
(16 comments)
??
https://review.coreboot.org/c/coreboot/+/34603/87//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/87//COMMIT_MSG@7 PS87, Line 7: .
No period here
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 49: MAINBOARD_POWER_ON_AFTER_POWER_FAIL
This isn't necessary
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
PS87:
I still want to see if this is working at all.
??
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 9: B0D4
This device is not enabled in your devicetree.cb, I doubt this will work...
So, what to do? remove the whole DTRT portion?
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/cmos.layout:
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 8: #0 8 r 0 seconds : #8 8 r 0 alarm_seconds : #16 8 r 0 minutes : #24 8 r 0 alarm_minutes : #32 8 r 0 hours : #40 8 r 0 alarm_hours : #48 8 r 0 day_of_week : #56 8 r 0 day_of_month : #64 8 r 0 month : #72 8 r 0 year : # ----------------------------------------------------------------- : # Status Register A : #80 4 r 0 rate_select : #84 3 r 0 REF_Clock : #87 1 r 0 UIP : # ----------------------------------------------------------------- : # Status Register B : #88 1 r 0 auto_switch_DST : #89 1 r 0 24_hour_mode : #90 1 r 0 binary_values_enable : #91 1 r 0 square-wave_out_enable : #92 1 r 0 update_finished_enable : #93 1 r 0 alarm_interrupt_enable : #94 1 r 0 periodic_interrupt_enable : #95 1 r 0 disable_clock_updates : # ----------------------------------------------------------------- : # Status Register C : #96 4 r 0 status_c_rsvd : #100 1 r 0 uf_flag : #101 1 r 0 af_flag : #102 1 r 0 pf_flag : #103 1 r 0 irqf_flag : # ----------------------------------------------------------------- : # Status Register D : #104 7 r 0 status_d_rsvd : #111 1 r 0 valid_cmos_ram : # ----------------------------------------------------------------- : # Diagnostic Status Register : #112 8 r 0 diag_rsvd1 : : # -----------------------------------------------------------------
Remove these
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 49: reserved_memory
KEEP this line!
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 50: #120 264 r 0 unused
Remove this one
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 56: #390 2 r 0 unused?
Remove
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 60: #392 3 r 0 unused
Remove
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 62: #399 1 r 0 unused
Remove
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 66: #401 7 r 0 unused
Remove
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 69: 408 1 e 1 nmi
Remove ("nmi" is unused in skylake)
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 71: #411 5 r 0 unused
Remove
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 73: # coreboot config options: bootloader : #Used by ChromeOS: : 416 128 r 0 vbnv : #544 440 r 0 unused : : # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3
Remove
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 84: #1000 24 r 0 amd_reserved
Remove
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 91: 1 0 Disable : 1 1 Enable
Remove
Done
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#89).
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mainboard/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - serial port - onboard audio - onboard network
Not tested: - PS/2 port - NCT5539D GPIOs - S3 suspend/resume - Wake-on-LAN - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/89
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mainboard/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 89:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/acpi/dptf.asl:
PS87:
??
Done
https://review.coreboot.org/c/coreboot/+/34603/87/src/mainboard/asus/h110m-e... PS87, Line 9: B0D4
So, what to do? remove the whole DTRT portion?
Done
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#90).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - serial port - onboard audio - onboard network
Not tested: - PS/2 port - NCT5539D GPIOs - S3 suspend/resume - Wake-on-LAN - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/90
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#91).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - serial port - onboard audio - onboard network - External Graphics Cards (For MS Windows, the GUI works but installing the graphics driver trips the machine and for GNU/Linux display only works with "nomodeset" kernel parameter)
Not working: - Onboard Graphics
Not tested: - PS/2 port - NCT5539D GPIOs - S3 suspend/resume - Wake-on-LAN - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/91
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#92).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - serial port - onboard audio - onboard network - External Graphics Cards (For MS Windows, the GUI works but installing the graphics driver trips the machine and for GNU/Linux, display only works with "nomodeset" kernel parameter)
Not working: - Onboard Graphics
Not tested: - PS/2 port - NCT5539D GPIOs - S3 suspend/resume - Wake-on-LAN - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/92
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 92: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG@11 PS92, Line 11: Working parts so far: What payload did you use?
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG@20 PS92, Line 20: GNU/Linux Which Linux kernel version?
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG@20 PS92, Line 20: MS Windows Which version?
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Paul Menzel, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#93).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Payload used: -Seabios -Tianocore
Blobs used: -fsp2.0 -GOP -ME -ME(cleaned) no difference observed between use of ME and ME(cleaned).
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - serial port - onboard audio - onboard network - External Graphics Cards works only with GOP, libgfxinit does not jumps to GRUB on main display or on serial output (For MS Windows 8.1, the GUI works but installing the graphics driver trips the machine and for GNU/Linux (Linux 4.18, 5.4, Linux-libre 5.4, 5.5) , display only works with "nomodeset" kernel parameter).
Not working: - Onboard Graphics - S3 suspend/resume - Wake-on-LAN
Not tested: - PS/2 port - NCT5539D GPIOs - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/93
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Paul Menzel, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#94).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Payload used: - Seabios - Tianocore
Blobs used: - Intel fsp2.0 - GOP - Intel ME - Intel ME(cleaned) no difference observed between use of ME and ME(cleaned).
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - serial port - onboard audio - onboard network - External Graphics Cards works only with GOP, libgfxinit does not jumps to GRUB on main display or on serial output (For MS Windows 8.1, the GUI works but installing the graphics driver trips the machine and for GNU/Linux (Linux 4.18, 5.4, Linux-libre 5.4, 5.5) , display only works with "nomodeset" kernel parameter).
Not working: - Intel onboard Graphics - S3 suspend/resume - Wake-on-LAN
Not tested: - PS/2 port - NCT5539D GPIOs - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/94
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Paul Menzel, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#95).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Payload used: - Seabios - Tianocore
Blobs used: - Intel fsp2.0 - GOP - Intel ME - Intel ME(cleaned) no difference observed between use of ME and ME(cleaned).
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - serial port - onboard audio - onboard network - External Graphics Cards works only with GOP, libgfxinit does not jumps to GRUB on main display or on serial output (For MS Windows 8.1, the GUI works but installing the graphics driver trips the machine and for GNU/Linux (Linux 4.18, 5.4, Linux-libre 5.4, 5.5) , display only works with "nomodeset" kernel parameter).
Not working: - Intel onboard Graphics - S3 suspend/resume - Wake-on-LAN
Not tested: - PS/2 port - NCT5539D GPIOs - hardware monitor 3 out of 4 times the machine trips during the coreboot boot process at FspSiliconInit and if not then in the Graphics initialization process, once out of 100 times it miracally booted into GUI only on Ubuntu (Linux 4.18).
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/95
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 95:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG@11 PS92, Line 11: Working parts so far:
What payload did you use?
Seabios, Tianocore
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG@20 PS92, Line 20: MS Windows
Which version?
Windows 8.1
https://review.coreboot.org/c/coreboot/+/34603/92//COMMIT_MSG@20 PS92, Line 20: GNU/Linux
Which Linux kernel version?
Linux 4.18, 5.4, Linux-libre-5.4, 5.5
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Paul Menzel, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#96).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Payload used: - Seabios - Tianocore
Blobs used: - Intel fsp2.0 - GOP - Intel ME - Intel ME(cleaned) no difference observed between use of ME and ME(cleaned).
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - Serial port - Onboard audio - Onboard network - External Graphics Cards works only with GOP, libgfxinit does not jumps to GRUB on main display or on serial output (For MS Windows 8.1, the GUI works but installing the graphics driver trips the machine and for GNU/Linux (Linux 4.18, 5.4, Linux-libre 5.4, 5.5) , display only works with "nomodeset" kernel parameter). 3 out of 4 times the machine trips during the coreboot boot process at FspSiliconInit and if not then in the Graphics initialization process, once out of 100 times it somehow booted into GUI only on Ubuntu (Linux 4.18).
Not working: - Intel onboard Graphics - S3 suspend/resume - Wake-on-LAN
Not tested: - PS/2 port - NCT5539D GPIOs - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/96
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 96: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/96/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/96/src/mainboard/asus/h110m-e... PS96, Line 13: 18 the Interrupt Select (INTSEL) field is read-only and should be set to 00h in all DW1 registers. An exception is when we set host owership (bit 4 - https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/...) to driver mode
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Maxim Polyakov, Paul Menzel, Sumeet R Pawnikar, Angel Pons, Michael Niewöhner, Maxim Polyakov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34603
to look at the new patch set (#97).
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
mb/asus: Add ASUS H110M-E/M.2 mainboard
This port is based on the Asrock H110M-DVS.
Payload used: - Seabios - Tianocore
Blobs used: - Intel fsp2.0 - GOP - Intel ME - Intel ME(cleaned) no difference observed between use of ME and ME(cleaned).
Working parts so far: - PCIe x1 - PEG x16 Gen3 - SATA - M.2 - USB 2.0 and USB 3.0 ports - Serial port - Onboard audio - Onboard network - External Graphics Cards works only with GOP, libgfxinit just wakes the main display with a blinking cursor even if I log into the system (when nomodeset kernel parameter enabled) through serial port (For MS Windows 8.1, the GUI works but installing the graphics driver trips the machine and for GNU/Linux (Linux 4.18, 5.4, Linux-libre 5.4, 5.5) , display only works with "nomodeset" kernel parameter). 3 out of 4 times the machine trips during the coreboot boot process at FspSiliconInit and if not then in the Graphics initialization process, once out of 100 times it somehow booted into GUI only on Ubuntu (Linux 4.18).
Not working: - Intel onboard Graphics - S3 suspend/resume - Wake-on-LAN
Not tested: - PS/2 port - NCT5539D GPIOs - hardware monitor
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Signed-off-by: Pavel Sayekat pavelsayekat@gmail.com --- A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 19 files changed, 827 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/97
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97: Code-Review+1
(8 comments)
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 101: register "SataPortsEnable" = "{ Do all SATA ports work?
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 149: subsystemid 0x1043 0x8694 inherit indent this
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 189: blank line can be removed
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 25: #include <soc/intel/skylake/acpi/ipu.asl> I think you can remove this
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 32: you can remove this blank line
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 15: eDP nope? your board doesn't have eDP
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 14: 0x0 Replace all these 0x0 with 0
All of them, please.
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 29: 4, Put this on the next line
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 26: Enable Lies! You are actually disabling DPTF, so this comment should be changed
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 26: Enable
Lies! You are actually disabling DPTF, so this comment should be changed
um, forgot to put an emoji, I'm not angry about this 😄
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97:
(5 comments)
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG@12 PS97, Line 12: Seabios SeaBIOS
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG@19 PS97, Line 19: - Intel ME(cleaned) Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG@20 PS97, Line 20: no difference observed between use of ME and ME(cleaned). Ditto.
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG@31 PS97, Line 31: , Remove the first space.
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG@31 PS97, Line 31: - External Graphics Cards works only with GOP, libgfxinit just wakes the main display with a blinking cursor even if I log into the system (when nomodeset kernel parameter enabled) through serial port (For MS Windows 8.1, the GUI works but installing the graphics driver trips the machine and for GNU/Linux (Linux 4.18, 5.4, Linux-libre 5.4, 5.5) , display only works with "nomodeset" kernel parameter). 3 out of 4 times the machine trips during the coreboot boot process at FspSiliconInit and if not then in the Graphics initialization process, once out of 100 times it somehow booted into GUI only on Ubuntu (Linux 4.18). Please wrap the lines after 75 characters.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97:
(12 comments)
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Kconfig:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 42: DDR4 nit: space after #
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 6: ramstage-y += mainboard.c not needed, included in src/arch/x86/Makefile.inc
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 8: ramstage-y += hda_verb.c not needed, included in src/device/Makefile.inc
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 2: ## This file is part of the coreboot project. this line can be dropped in all files (see CB:41194)
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 6: # Disable deep Sx states : register "deep_s3_enable_ac" = "0" : register "deep_s3_enable_dc" = "0" : register "deep_s5_enable_ac" = "0" : register "deep_s5_enable_dc" = "0" : register "deep_sx_config" = "DSX_EN_WAKE_PIN" can be dropped when disabled
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 26: Enable
um, forgot to put an emoji, I'm not angry about this 😄
well, this can be completely dropped, assuming dptf shall be disabled
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 31: register "ScsEmmcEnabled" = "0" : register "ScsEmmcHs400Enabled" = "0" : register "ScsSdCardEnabled" = "0" : register "HeciEnabled" = "0" : register "SkipExtGfxScan" = "0" can be dropped
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 39: register "PmTimerDisabled" = "0" duplicate; =0 can be dropped anyways
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 41: register "DspEnable" = "0" can be dropped
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 70: register "PmTimerDisabled" = "0" duplicate; =0 can be dropped anyways
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 106: 0, : [5] = 0, : [6] = 0, : [7] = 0, can be dropped
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 13: CdClock not sure if that is still needed; default is "Auto"; Maybe test and drop
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 101: register "SataPortsEnable" = "{
Do all SATA ports work?
Just saw an H110 board, ports 4 and 5 are the ones not present in SPT (on previous generations, they were ports 2 and 3)
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 13: CdClock
not sure if that is still needed; default is "Auto"; Maybe test and drop
How to test it or should I set it to Auto from 3?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 97:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG@31 PS97, Line 31: - External Graphics Cards works only with GOP, libgfxinit just wakes the main display with a blinking cursor even if I log into the system (when nomodeset kernel parameter enabled) through serial port (For MS Windows 8.1, the GUI works but installing the graphics driver trips the machine and for GNU/Linux (Linux 4.18, 5.4, Linux-libre 5.4, 5.5) , display only works with "nomodeset" kernel parameter). 3 out of 4 times the machine trips during the coreboot boot process at FspSiliconInit and if not then in the Graphics initialization process, once out of 100 times it somehow booted into GUI only on Ubuntu (Linux 4.18).
Please wrap the lines after 75 characters.
The libgfxinit things are not about external graphics cards
https://review.coreboot.org/c/coreboot/+/34603/97//COMMIT_MSG@35 PS97, Line 35: S3 suspend/resume It would be good to describe what happens instead of the expected outcome.
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34603/97/src/mainboard/asus/h110m-e... PS97, Line 13: CdClock
How to test it or should I set it to Auto from 3?
AFAIK, remove the line then check if video outputs still work
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34603?usp=email )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Martin L Roth (Code Review)
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Maxim Polyakov (Code Review)
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Michael Niewöhner (Code Review)
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Nico Huber (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)
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Pavel Sayekat (Code Review)
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Pavlushka (Code Review)
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Sumeet R Pawnikar (Code Review)