Patch Set 50:
So far the serial output of coreboot which leads to a blank display with a blinking cursor, https://pastebin.com/S9tLjhwb
Well well well... It seems to hang when writing the SIO global registers. As I commented on the devtree, just remove these writes. Hope this helps.
Patch set 50:Code-Review +1
19 comments:
Patch Set #47, Line 9: a variant of
Please undo the commit message change
Done
File Documentation/mainboard/asus/h110m-e_m2.md:
Patch Set #46, Line 44: output is not required:
to speed up the boot.
Done
Should fit on the line above.
Done
File Documentation/mainboard/index.md:
Patch Set #49, Line 11: - [H110M-E/M.2](asus/h110m-e_m2.md)
Looks like until this port gets working and approved, the index. […]
Just don't forget to add it. Leaving this comment unresolved as a reminder.
File src/mainboard/asus/h110m-e_m2/Kconfig:
Patch Set #50, Line 3: config BOARD_SPECIFIC_OPTIONS
Missing Kconfig select for the LPC TPM on the devicetree
File src/mainboard/asus/h110m-e_m2/devicetree.cb:
Patch Set #50, Line 19: Enable
Nit: Disable
register "PchHdaVcType" = "Vc1"
1520
1520
1520
1520
[4] = 1, \
[5] = 1, \
[6] = 1, \
[7] = 1, \
These are 0 for H110
# Enable CLKREQ#
register "PcieRpClkReqSupport[7]" = "1"
# Use SRCCLKREQ1#
register "PcieRpClkReqNumber[7]" = "1"
Should not be needed and can be disabled
These lone `end` words can go into the previous line
Patch Set #50, Line 282: device pci 1c.4 off end # PCI Express Port 5
should be on
Patch Set #50, Line 298: chip superio/nuvoton/nct5539d
asrock/h110m now has some more code you might need.
rq 0x1c = 0x10
irq 0x27 = 0x03
irq 0x2a = 0xc0
Remove these writes. They are writing the default values, and coreboot hangs right when doing so.
File src/mainboard/asus/h110m-e_m2/ramstage.c:
/* Enable Virtual Channel 1 */
params->PchHdaVcType = 0x1;
Should be set in the devicetree
File src/mainboard/asus/h110m-e_m2/romstage.c:
asrock/h110m also fills DQ and DQS map data here. Maybe you need that too.
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