Patch set 56:Code-Review +1
29 comments:
File src/mainboard/asus/h110m-e_m2/Kconfig:
Patch Set #56, Line 36: config DEVICETREE
it's the default value
File src/mainboard/asus/h110m-e_m2/devicetree.cb:
Patch Set #50, Line 19: Enable
Nit: Disable
Done
register "PchHdaVcType" = "Vc1"
Done
1520
Done
1520
Done
1520
Done
1520
Done
[4] = 1, \
[5] = 1, \
[6] = 1, \
[7] = 1, \
These are 0 for H110
Done
# Enable CLKREQ#
register "PcieRpClkReqSupport[7]" = "1"
# Use SRCCLKREQ1#
register "PcieRpClkReqNumber[7]" = "1"
Should not be needed and can be disabled
Done
These lone `end` words can go into the previous line
Done
Patch Set #50, Line 282: device pci 1c.4 off end # PCI Express Port 5
should be on
Done
Patch Set #50, Line 298: chip superio/nuvoton/nct5539d
https://github. […]
Done
rq 0x1c = 0x10
irq 0x27 = 0x03
irq 0x2a = 0xc0
Remove these writes. They are writing the default values, and coreboot hangs right when doing so.
Done
chip drivers/pc80/tpm
device pnp 4e.0 on end # TPM module
end
You don't have a TPM
Done
File src/mainboard/asus/h110m-e_m2/devicetree.cb:
Patch Set #56, Line 203: Enable
They are not enabled anymore. Might as well drop the comments
Patch Set #56, Line 298: chip superio/nuvoton/nct5539d
you need to indent this, though
# global
# UART A
these two comments aren't needed anymore
File src/mainboard/asus/h110m-e_m2/dsdt.asl:
Patch Set #50, Line 51: soc/intel/skylake
southbridge/intel/common
Done
File src/mainboard/asus/h110m-e_m2/dsdt.asl:
What happened to the space here?
And here?
File src/mainboard/asus/h110m-e_m2/hda_verb.c:
these 0x0 should be 0
Done
Patch Set #50, Line 44: 0x00000004
just 4
Done
Patch Set #50, Line 45: 0x80860101
You don't need to repeat the value in the comment
Done
should be 2
Done
File src/mainboard/asus/h110m-e_m2/hda_verb.c:
these are just 0 as well
these are just 2 as well
File src/mainboard/asus/h110m-e_m2/ramstage.c:
/* Enable Virtual Channel 1 */
params->PchHdaVcType = 0x1;
Should be set in the devicetree
Done
File src/mainboard/asus/h110m-e_m2/romstage.c:
Patch Set #50, Line 45: 0x53,
If your board has only 2 DIMMs, you can probably scratch 0x51 and 0x53.
It is the case, done.
File src/mainboard/asus/h110m-e_m2/romstage.c:
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
Needs to change as the order changed above. Most likely: […]
some intel board with two DIMMs does exactly that
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