Patch set 73:Code-Review +1
1 comment:
File src/mainboard/asus/h110m-e_m2/devicetree.cb:
# Set params for PEG 0:1:0
register "Peg0MaxLinkWidth" = "Peg0_x16"
# Configure PCIe clockgen in PCH
# PEG0 uses SRCCLKREQ0 and CLKSRC0
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "0"
register "PcieRpClkSrcNumber[0]" = "0"
# Enable Root port 8(x1) for LAN.
register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "0"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[7]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[7]" = "1"
# Use CLK SRC 1
register "PcieRpClkSrcNumber[7]" = "1"
# Enable Root port 5 (x1) for PCIE slot.
register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[4]" = "1"
# Use SRCCLKREQ2#
register "PcieRpClkReqNumber[4]" = "2"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[4]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[4]" = "1"
# Use CLK SRC 2
register "PcieRpClkSrcNumber[4]" = "2"
# Use Hot Plug subsystem
register "PcieRpHotPlug[4]" = "1"
# Enable Root port 9(x1) for PCIE slot.
register "PcieRpEnable[8]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[8]" = "1"
# Use SRCCLKREQ3#
register "PcieRpClkReqNumber[8]" = "3"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[8]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[8]" = "1"
# Use CLK SRC 3
register "PcieRpClkSrcNumber[8]" = "3"
# Use Hot Plug subsystem
register "PcieRpHotPlug[8]" = "1"
For you, anything.
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