Chapter bazillionth: The devicetree :)
Adding Maxim Polyakov as reviewer, as he ported asrock/h110m and probably knows Skylake stuff better than I do
16 comments:
File src/mainboard/asus/h110m-e_m2/devicetree.cb:
Patch Set #18, Line 78: # VR Settings Configuration for 5 Domains
All the VR (Voltage Regulator) settings, if taken from asrock/h110m, should work.
Patch Set #18, Line 145: register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
I think you don't need this
Patch Set #18, Line 190: register "SerialIoDevMode" = "{ \
I don't think these should be enabled either
In your case, this is root port 8
register "PcieRpEnable[5]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[5]" = "1"
# Use SRCCLKREQ1#
register "PcieRpClkReqNumber[5]" = "1"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[5]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[5]" = "1"
# Use CLK SRC 1
register "PcieRpClkSrcNumber[5]" = "1"
s/[5]/[7]
(replace '[5]' with '[7]' on this section)
Patch Set #18, Line 225: # Enable Root port 5 (x1) for PCIE slot.
This one is correct
In your case, this is root port 9
register "PcieRpEnable[6]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[6]" = "1"
# Use SRCCLKREQ3#
register "PcieRpClkReqNumber[6]" = "3"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[6]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[6]" = "1"
# Use CLK SRC 3
register "PcieRpClkSrcNumber[6]" = "3"
# Use Hot Plug subsystem
register "PcieRpHotPlug[6]" = "1"
s/[6]/[8]
(replace '[6]' with '[8]' on this section)
device pci 14.2 on # Thermal Subsystem
subsystemid 0x1849 0xa131
end
Disable this device:
device pci 14.2 off end # Thermal Subsystem
device pci 16.0 on # Management Engine Interface 1
subsystemid 0x1849 0xa131
end
Looks disabled on your board, but it might just be hidden
Patch Set #18, Line 302: 1c.4 on
1c.4 off
Patch Set #18, Line 303: 1c.5 on
1c.5 off
Patch Set #18, Line 304: 1c.6 on
1c.6 off
Patch Set #18, Line 305: 1c.7 off
1c.7 on
Patch Set #18, Line 306: 1d.0 off
1d.0 on
The values you should write here are the ones superiotool says. Make sure the LDNs (device pnp 2e.X) are correct.
If in doubt, send a log of 'superiotool -d'
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