Pavel Sayekat has uploaded this change for review.
src/mainboard/asus: Add h110m-e_m2 mainboard support
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c
---
A src/mainboard/asus/h110m-e_m2/6776.txt
A src/mainboard/asus/h110m-e_m2/Kconfig
A src/mainboard/asus/h110m-e_m2/Kconfig.name
A src/mainboard/asus/h110m-e_m2/Makefile.inc
A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl
A src/mainboard/asus/h110m-e_m2/acpi/ec.asl
A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl
A src/mainboard/asus/h110m-e_m2/acpi/superio.asl
A src/mainboard/asus/h110m-e_m2/acpi_tables.c
A src/mainboard/asus/h110m-e_m2/board_info.txt
A src/mainboard/asus/h110m-e_m2/bootblock.c
A src/mainboard/asus/h110m-e_m2/cmos.default
A src/mainboard/asus/h110m-e_m2/cmos.layout
A src/mainboard/asus/h110m-e_m2/data.vbt
A src/mainboard/asus/h110m-e_m2/devicetree.cb
A src/mainboard/asus/h110m-e_m2/dsdt.asl
A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads
A src/mainboard/asus/h110m-e_m2/gpio.txt
A src/mainboard/asus/h110m-e_m2/hda_verb.c
A src/mainboard/asus/h110m-e_m2/include/gpio.h
A src/mainboard/asus/h110m-e_m2/mainboard.c
A src/mainboard/asus/h110m-e_m2/ramstage.c
A src/mainboard/asus/h110m-e_m2/romstage.c
23 files changed, 1,875 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/1
diff --git a/src/mainboard/asus/h110m-e_m2/6776.txt b/src/mainboard/asus/h110m-e_m2/6776.txt
new file mode 100644
index 0000000..9969ca7
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/6776.txt
@@ -0,0 +1,10 @@
+acpi/superio.asl:#define NCT6776_SHOW_PP
+acpi/superio.asl:#define NCT6776_SHOW_SP1
+acpi/superio.asl:#define NCT6776_SHOW_KBC
+acpi/superio.asl:#define NCT6776_SHOW_HWM
+acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+acpi/superio.asl:#include <superio/nuvoton/nct6776/acpi/superio.asl>
+gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO
diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig b/src/mainboard/asus/h110m-e_m2/Kconfig
new file mode 100644
index 0000000..55a21cf
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/Kconfig
@@ -0,0 +1,53 @@
+if BOARD_ASUS-H110M_E-M2
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select SOC_INTEL_KABYLAKE
+ select SKYLAKE_SOC_PCH_H
+ select GENERIC_SPD_BIN
+ select SUPERIO_NUVOTON_NCT5539D
+ select SUPERIO_NUVOTON_NCT5539D_COM_A
+ select REALTEK_8168_RESET
+ select RT8168_SET_LED_MODE
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_DIR
+ string
+ default "asus/h110m"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H110M"
+
+config MAX_CPUS
+ int
+ default 8
+
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config PRERAM_CBMEM_CONSOLE_SIZE
+ hex
+ default 0xd00
+
+config DIMM_SPD_SIZE
+ int
+ default 512 #DDR4
+
+# This is overridden if CMOS is used for configuration values.
+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+ bool
+ default n
+
+endif
diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig.name b/src/mainboard/asus/h110m-e_m2/Kconfig.name
new file mode 100644
index 0000000..788594c
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_H110M_E-M.2
+ bool "H110M_E-M.2"
diff --git a/src/mainboard/asus/h110m-e_m2/Makefile.inc b/src/mainboard/asus/h110m-e_m2/Makefile.inc
new file mode 100644
index 0000000..ce6cf80
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2016 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+bootblock-y += bootblock.c
+
+ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl
new file mode 100644
index 0000000..4453f3b
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 98
+#define DPTF_CPU_CRITICAL 125
+#define DPTF_CPU_ACTIVE_AC0 91
+#define DPTF_CPU_ACTIVE_AC1 85
+#define DPTF_CPU_ACTIVE_AC2 83
+#define DPTF_CPU_ACTIVE_AC3 80
+#define DPTF_CPU_ACTIVE_AC4 75
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 10000, /* PowerLimitMinimum */
+ 31000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 28000, /* TimeWindowMaximum */
+ 100 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 65000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 28000, /* TimeWindowMaximum */
+ 100 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/asus/h110m-e_m2/acpi/ec.asl b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl
diff --git a/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl
diff --git a/src/mainboard/asus/h110m-e_m2/acpi/superio.asl b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl
new file mode 100644
index 0000000..b671e3c
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define NCT6776_SHOW_PP
+#define NCT6776_SHOW_SP1
+#define NCT6776_SHOW_KBC
+#define NCT6776_SHOW_HWM
+
+#undef NCT6776_SHOW_GPIO
+
+#include <superio/nuvoton/nct6776/acpi/superio.asl>
diff --git a/src/mainboard/asus/h110m-e_m2/acpi_tables.c b/src/mainboard/asus/h110m-e_m2/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/acpi_tables.c
diff --git a/src/mainboard/asus/h110m-e_m2/board_info.txt b/src/mainboard/asus/h110m-e_m2/board_info.txt
new file mode 100644
index 0000000..23fd8e6
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/H110M-E-M-2/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2017
diff --git a/src/mainboard/asus/h110m-e_m2/bootblock.c b/src/mainboard/asus/h110m-e_m2/bootblock.c
new file mode 100644
index 0000000..eb019c2
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/bootblock.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ * Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5539d/nct5539d.h>
+#include "include/gpio.h"
+
+static void early_config_superio(void)
+{
+ const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1);
+ nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}
+
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't do. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
+
+void bootblock_mainboard_early_init(void)
+{
+ early_config_superio();
+}
diff --git a/src/mainboard/asus/h110m-e_m2/cmos.default b/src/mainboard/asus/h110m-e_m2/cmos.default
new file mode 100644
index 0000000..3296093
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/cmos.default
@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
diff --git a/src/mainboard/asus/h110m-e_m2/cmos.layout b/src/mainboard/asus/h110m-e_m2/cmos.layout
new file mode 100644
index 0000000..916db62
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/cmos.layout
@@ -0,0 +1,125 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2016 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/asus/h110m-e_m2/data.vbt b/src/mainboard/asus/h110m-e_m2/data.vbt
new file mode 100644
index 0000000..fb03cca
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/h110m-e_m2/devicetree.cb b/src/mainboard/asus/h110m-e_m2/devicetree.cb
new file mode 100644
index 0000000..cdc6c2d
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/devicetree.cb
@@ -0,0 +1,388 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Intel Corporation.
+## Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # FSP Configuration
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "HeciEnabled" = "0"
+ register "SkipExtGfxScan" = "0"
+ register "PrimaryDisplay" = "Display_PEG"
+ register "Device4Enable" = "1"
+ register "SaGv" = "SaGv_Enabled"
+ register "PmTimerDisabled" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "0"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x10, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x0, \
+ .voltage_limit = 0x0 \
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x0, \
+ .voltage_limit = 0x0 \
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x0 ,\
+ .voltage_limit = 0x0 \
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x0, \
+ .voltage_limit = 0x0 \
+ }"
+
+ register "EnableLan" = "0"
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+
+ register "PmTimerDisabled" = "0"
+
+ # USB
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+
+ # SATA
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{ \
+ [0] = 1, \
+ [1] = 1, \
+ [2] = 1, \
+ [3] = 1, \
+ [4] = 1, \
+ [5] = 1, \
+ [6] = 1, \
+ [7] = 1, \
+ }"
+
+ # PCH UART, SPI, I2C
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
+ }"
+
+ # Set params for PEG 0:1:0
+ register "Peg0MaxLinkWidth" = "Peg0_x16"
+ # Configure PCIe clockgen in PCH
+ # PEG0 uses SRCCLKREQ0 and CLKSRC0
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[0]" = "0"
+
+ # Enable Root port 6(x1) for LAN.
+ register "PcieRpEnable[5]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[5]" = "1"
+ # Use SRCCLKREQ1#
+ register "PcieRpClkReqNumber[5]" = "1"
+ # Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[5]" = "1"
+ # Use CLK SRC 1
+ register "PcieRpClkSrcNumber[5]" = "1"
+
+ # Enable Root port 5 (x1) for PCIE slot.
+ register "PcieRpEnable[4]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[4]" = "1"
+ # Use SRCCLKREQ2#
+ register "PcieRpClkReqNumber[4]" = "2"
+ # Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[4]" = "1"
+ # Use CLK SRC 2
+ register "PcieRpClkSrcNumber[4]" = "2"
+ # Use Hot Plug subsystem
+ register "PcieRpHotPlug[4]" = "1"
+
+ # Enable Root port 7(x1) for PCIE slot.
+ register "PcieRpEnable[6]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[6]" = "1"
+ # Use SRCCLKREQ3#
+ register "PcieRpClkReqNumber[6]" = "3"
+ # Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[6]" = "1"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[6]" = "1"
+ # Use CLK SRC 3
+ register "PcieRpClkSrcNumber[6]" = "3"
+ # Use Hot Plug subsystem
+ register "PcieRpHotPlug[6]" = "1"
+
+ # PL2 override 91W
+ register "tdp_pl2_override" = "91"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on # Host Bridge
+ subsystemid 0x1849 0x191f
+ end
+ device pci 01.0 on # PEG
+ subsystemid 0x1849 0x1901
+ end
+ device pci 02.0 on # Integrated Graphics Device
+ subsystemid 0x1849 0x1912
+ end
+ device pci 14.0 on # USB xHCI
+ subsystemid 0x1849 0xa131
+ end
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on # Thermal Subsystem
+ subsystemid 0x1849 0xa131
+ end
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x1849 0xa131
+ end
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on # SATA
+ subsystemid 0x1849 0xa102
+ end
+ device pci 19.0 off end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.5 on end # PCI Express Port 6
+ device pci 1c.6 on end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on # LPC bridge
+ subsystemid 0x1849 0x1a43
+ chip superio/nuvoton/nct5539d
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # Parallel
+ # global
+ irq 0x1c = 0x10
+ irq 0x27 = 0x10
+ irq 0x2a = 0x64
+ # parallel port
+ io 0x60 = 0x0378
+ irq 0x70 = 7
+ drq 0x74 = 4 # No DMA
+ irq 0xf0 = 0x3c # Printer mode
+ end
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x03f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # IR
+ io 0x60 = 0x02f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # PS/2 KBC
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 1 # Keyboard
+ irq 0x72 = 12 # Mouse
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO6
+ device pnp 2e.107 off end # GPIO7
+ device pnp 2e.207 off end # GPIO8
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.108 off end # GPIO0
+ device pnp 2e.308 off end # GPIO base
+ device pnp 2e.408 off end # WDTMEM
+ device pnp 2e.708 off end # GPIO1
+ device pnp 2e.9 off end # GPIO2
+ device pnp 2e.109 off end # GPIO3
+ device pnp 2e.209 off end # GPIO4
+ device pnp 2e.309 off end # GPIO5
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HWM, LED
+ io 0x60 = 0x0290
+ io 0x62 = 0
+ irq 0x70 = 0
+ end
+ device pnp 2e.d off end # BCLK, WDT2, WDT_MEM
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f off end # GPIO PP/OD
+ device pnp 2e.14 off end # SVID, Port 80 UART
+ device pnp 2e.16 off end # DS5
+ device pnp 2e.116 off end # DS3
+ device pnp 2e.316 off end # PCHDSW
+ device pnp 2e.416 off end # DSWWOPT
+ device pnp 2e.516 off end # DS3OPT
+ device pnp 2e.616 off end # DSDSS
+ device pnp 2e.716 off end # DSPU
+ end # superio/nuvoton/nct5539d
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM module
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/asus/h110m-e_m2/dsdt.asl b/src/mainboard/asus/h110m-e_m2/dsdt.asl
new file mode 100644
index 0000000..f3e216d
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/dsdt.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ /* Image processing unit */
+ #include <soc/intel/skylake/acpi/ipu.asl>
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ // Dynamic Platform Thermal Framework
+ #include "acpi/dptf.asl"
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads
new file mode 100644
index 0000000..86a3a62
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads
@@ -0,0 +1,32 @@
+--
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1, -- mainboard DVI port
+ HDMI3, -- mainboard HDMI port
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/h110m-e_m2/gpio.txt b/src/mainboard/asus/h110m-e_m2/gpio.txt
new file mode 100644
index 0000000..3416eee
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/gpio.txt
@@ -0,0 +1,580 @@
+acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+include/gpio.h:#ifndef _GPIO_DVS_H
+include/gpio.h:#define _GPIO_DVS_H
+include/gpio.h: /* GPIO Group GPP_A */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_B */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_C */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_D */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_E */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_F */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_G */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_H */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */
+include/gpio.h: /* GPIO Group GPD */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_I */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_A */
+devicetree.cb: device pnp 2e.7 off end # GPIO6
+devicetree.cb: device pnp 2e.107 off end # GPIO7
+devicetree.cb: device pnp 2e.207 off end # GPIO8
+devicetree.cb: device pnp 2e.108 off end # GPIO0
+devicetree.cb: device pnp 2e.308 off end # GPIO base
+devicetree.cb: device pnp 2e.708 off end # GPIO1
+devicetree.cb: device pnp 2e.9 off end # GPIO2
+devicetree.cb: device pnp 2e.109 off end # GPIO3
+devicetree.cb: device pnp 2e.209 off end # GPIO4
+devicetree.cb: device pnp 2e.309 off end # GPIO5
+devicetree.cb: device pnp 2e.f off end # GPIO PP/OD
+acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+include/gpio.h:#ifndef _GPIO_DVS_H
+include/gpio.h:#define _GPIO_DVS_H
+include/gpio.h: /* GPIO Group GPP_A */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_B */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_C */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_D */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_E */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_F */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_G */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_H */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */
+include/gpio.h: /* GPIO Group GPD */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_I */
+include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */
+include/gpio.h: /* GPIO Group GPP_A */
+devicetree.cb: device pnp 2e.7 off end # GPIO6
+devicetree.cb: device pnp 2e.107 off end # GPIO7
+devicetree.cb: device pnp 2e.207 off end # GPIO8
+devicetree.cb: device pnp 2e.108 off end # GPIO0
+devicetree.cb: device pnp 2e.308 off end # GPIO base
+devicetree.cb: device pnp 2e.708 off end # GPIO1
+devicetree.cb: device pnp 2e.9 off end # GPIO2
+devicetree.cb: device pnp 2e.109 off end # GPIO3
+devicetree.cb: device pnp 2e.209 off end # GPIO4
+devicetree.cb: device pnp 2e.309 off end # GPIO5
+devicetree.cb: device pnp 2e.f off end # GPIO PP/OD
+gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H
+gpio.txt:include/gpio.h:#define _GPIO_DVS_H
+gpio.txt:include/gpio.h: /* GPIO Group GPP_A */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_B */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_C */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_D */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_E */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_F */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_G */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_H */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPD */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_I */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_A */
+gpio.txt:devicetree.cb: device pnp 2e.7 off end # GPIO6
+gpio.txt:devicetree.cb: device pnp 2e.107 off end # GPIO7
+gpio.txt:devicetree.cb: device pnp 2e.207 off end # GPIO8
+gpio.txt:devicetree.cb: device pnp 2e.108 off end # GPIO0
+gpio.txt:devicetree.cb: device pnp 2e.308 off end # GPIO base
+gpio.txt:devicetree.cb: device pnp 2e.708 off end # GPIO1
+gpio.txt:devicetree.cb: device pnp 2e.9 off end # GPIO2
+gpio.txt:devicetree.cb: device pnp 2e.109 off end # GPIO3
+gpio.txt:devicetree.cb: device pnp 2e.209 off end # GPIO4
+gpio.txt:devicetree.cb: device pnp 2e.309 off end # GPIO5
+gpio.txt:devicetree.cb: device pnp 2e.f off end # GPIO PP/OD
+gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO
+gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H
+gpio.txt:include/gpio.h:#define _GPIO_DVS_H
+gpio.txt:include/gpio.h: /* GPIO Group GPP_A */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_B */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_C */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_D */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_E */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_F */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */
+gpio.txt:include/gpio.h: /* GPIO Group GPP_G */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */
+gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */
diff --git a/src/mainboard/asus/h110m-e_m2/hda_verb.c b/src/mainboard/asus/h110m-e_m2/hda_verb.c
new file mode 100644
index 0000000..1d1627b
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/hda_verb.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ * (Written by Naresh G Solanki <naresh.solanki@intel.com> for Intel Corp.)
+ * Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header ALC887 */
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+ 0x10438445, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x0, 0x10438445),
+ AZALIA_PIN_CFG(0x0, 0x11, 0x40000000),
+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x14, 0x01014020),
+ AZALIA_PIN_CFG(0x0, 0x15, 0x90170110),
+ AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040),
+ AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050),
+ AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030),
+ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629),
+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
+
+ /* coreboot specific header */
+ 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */
+ 0x80860101,
+ 0x00000004,
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(0x2, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x2, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x2, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x2, 0x07, 0x18560030)
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h110m-e_m2/include/gpio.h b/src/mainboard/asus/h110m-e_m2/include/gpio.h
new file mode 100644
index 0000000..a8a4d19
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/include/gpio.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _GPIO_DVS_H
+#define _GPIO_DVS_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
+ _PAD_CFG_STRUCT(val, config0, config1)
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+ /* GPIO Group GPP_A */
+ H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
+ H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */
+ H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */
+ H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */
+ H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */
+ H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
+ H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
+ H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
+ H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
+ H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
+ H110_PAD_DW0_DW1_CFG(GPP_A11, 0x44000502, 0x00003023), /* PME# */
+ H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */
+ H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */
+ H110_PAD_DW0_DW1_CFG(GPP_A16, 0x04000100, 0x00001028), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A17, 0x04000100, 0x00001029), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A18, 0x04000100, 0x0000102a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A19, 0x04000100, 0x0000102b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A20, 0x04000100, 0x0000102c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A21, 0x04000100, 0x0000102d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A22, 0x04000100, 0x0000102e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A23, 0x04000100, 0x0000102f), /* GPIO */
+ /* GPIO Group GPP_B */
+ H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B1, 0x04000100, 0x00001031), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B3, 0x04000100, 0x00001033), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B4, 0x04000100, 0x00001034), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B5, 0x44000702, 0x00000035), /* SRCCLKREQ0# */
+ H110_PAD_DW0_DW1_CFG(GPP_B6, 0x04000100, 0x00001036), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B7, 0x04000500, 0x00001037), /* SRCCLKREQ2# */
+ H110_PAD_DW0_DW1_CFG(GPP_B8, 0x04000100, 0x00001038), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B9, 0x04000500, 0x00001039), /* SRCCLKREQ4# */
+ H110_PAD_DW0_DW1_CFG(GPP_B10, 0x04000500, 0x0000103a), /* SRCCLKREQ5# */
+ H110_PAD_DW0_DW1_CFG(GPP_B11, 0x84000100, 0x0000003b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B12, 0x84000100, 0x0000103c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B13, 0x84000600, 0x0000003d), /* PLTRST# */
+ H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000003e), /* SPKR */
+ H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000200, 0x00000040), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B17, 0x04000100, 0x00001041), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000100, 0x00000045), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000100, 0x00001047), /* GPIO */
+ /* GPIO Group GPP_C */
+ H110_PAD_DW0_DW1_CFG(GPP_C0, 0x84000502, 0x00000048), /* SMBCLK */
+ H110_PAD_DW0_DW1_CFG(GPP_C1, 0x84000502, 0x00000049), /* SMBDATA */
+ H110_PAD_DW0_DW1_CFG(GPP_C2, 0x84000100, 0x0000004a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C3, 0x84000502, 0x0000004b), /* SML0CLK */
+ H110_PAD_DW0_DW1_CFG(GPP_C4, 0x84000502, 0x0000004c), /* SML0DATA */
+ H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C6, 0x04000102, 0x0000104e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C7, 0x04000102, 0x0000104f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C8, 0x04000100, 0x00001050), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C9, 0x04000100, 0x00001051), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C10, 0x04000100, 0x00001052), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C11, 0x04000100, 0x00001053), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C12, 0x04000100, 0x00000054), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C13, 0x04000100, 0x00001055), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C15, 0x04000100, 0x00001057), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C16, 0x04000100, 0x00001058), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C17, 0x04000100, 0x00001059), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C18, 0x04000100, 0x0000105a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C19, 0x04000100, 0x0000105b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000100, 0x0000005c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000100, 0x0000005d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000100, 0x0000005e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_C23, 0x84000100, 0x0000005f), /* GPIO */
+ /* GPIO Group GPP_D */
+ H110_PAD_DW0_DW1_CFG(GPP_D0, 0x04000100, 0x00001060), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D1, 0x04000100, 0x00001061), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D3, 0x04000100, 0x00001063), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000100, 0x00000064), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D5, 0x04000100, 0x00001065), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D6, 0x04000100, 0x00001066), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D7, 0x04000100, 0x00001067), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D8, 0x04000100, 0x00001068), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000100, 0x00000069), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000100, 0x0000006a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D11, 0x04000100, 0x0000106b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D12, 0x04000102, 0x0000106c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000100, 0x0000006d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000102, 0x0000006e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D16, 0x04000100, 0x00001070), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D17, 0x04000100, 0x00001071), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D18, 0x04000100, 0x00001072), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D19, 0x04000100, 0x00001073), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D20, 0x04000100, 0x00001074), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_D23, 0x04000100, 0x00001077), /* GPIO */
+ /* GPIO Group GPP_E */
+ H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000102, 0x00000018), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000102, 0x00000019), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000100, 0x0000001a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E3, 0x04000100, 0x0000101b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E4, 0x44000100, 0x0000001c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E5, 0x04000100, 0x0000101d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E6, 0x04000100, 0x0000101e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E7, 0x04000100, 0x0000101f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */
+ H110_PAD_DW0_DW1_CFG(GPP_E9, 0x84000502, 0x00000021), /* USB_OC0# */
+ H110_PAD_DW0_DW1_CFG(GPP_E10, 0x84000502, 0x00000022), /* USB_OC1# */
+ H110_PAD_DW0_DW1_CFG(GPP_E11, 0x84000502, 0x00000023), /* USB_OC2# */
+ H110_PAD_DW0_DW1_CFG(GPP_E12, 0x84000502, 0x00000024), /* USB_OC3# */
+ /* GPIO Group GPP_F */
+ H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000100, 0x00000025), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F1, 0x04000100, 0x00001026), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F2, 0x04000100, 0x00001027), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F3, 0x04000100, 0x00001028), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000100, 0x00000029), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000100, 0x0000002a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000100, 0x0000002b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000100, 0x0000002c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000100, 0x0000002d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000100, 0x0000002e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F10, 0x84000100, 0x0000002f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F11, 0x04000100, 0x00001030), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F12, 0x04000100, 0x00001031), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F13, 0x04000100, 0x00001032), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F14, 0x04000100, 0x00001033), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F15, 0x84000502, 0x00000034), /* USB_OC4# */
+ H110_PAD_DW0_DW1_CFG(GPP_F16, 0x84000102, 0x00000035), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F17, 0x84000102, 0x00000036), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000102, 0x00000037), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F19, 0x04000100, 0x00001038), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F20, 0x04000100, 0x00001039), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F21, 0x04000100, 0x0000103a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F22, 0x04000100, 0x0000103b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_F23, 0x04000100, 0x0000103c), /* GPIO */
+ /* GPIO Group GPP_G */
+ H110_PAD_DW0_DW1_CFG(GPP_G0, 0x04000100, 0x0000103d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G1, 0x04000100, 0x0000103e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G2, 0x04000100, 0x0000103f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G3, 0x04000100, 0x00001040), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G4, 0x04000100, 0x00001041), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G5, 0x84000100, 0x00000042), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G6, 0x84000100, 0x00000043), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G7, 0x84000100, 0x00000044), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G8, 0x04000100, 0x00001045), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G9, 0x04000100, 0x00001046), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G10, 0x04000100, 0x00001047), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G11, 0x04000100, 0x00001048), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G12, 0x04000100, 0x00001049), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G13, 0x04000100, 0x0000104a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G14, 0x84000100, 0x0000004b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000100, 0x0000004c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G16, 0x04000100, 0x0000104d), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G17, 0x04000100, 0x0000104e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G18, 0x84000100, 0x0000104f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000100, 0x00001050), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G20, 0x04000100, 0x00001051), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G21, 0x04000100, 0x00001052), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G22, 0x04000100, 0x00001053), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_G23, 0x04000100, 0x00001054), /* GPIO */
+ /* GPIO Group GPP_H */
+ H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000100, 0x00000055), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000702, 0x00000056), /* SRCCLKREQ7# */
+ H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000100, 0x00000057), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000100, 0x00000058), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H4, 0x04000100, 0x00001059), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000100, 0x0000005a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H6, 0x04000100, 0x0000105b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H7, 0x04000100, 0x0000105c), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H8, 0x44000702, 0x0000005d), /* SRCCLKREQ14# */
+ H110_PAD_DW0_DW1_CFG(GPP_H9, 0x04000100, 0x0000105e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H10, 0x04000100, 0x0000105f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H11, 0x04000100, 0x00001060), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H13, 0x44000100, 0x00000062), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H14, 0x84000100, 0x00000063), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H15, 0x04000100, 0x00001064), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H16, 0x84000100, 0x00000065), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H17, 0x04000100, 0x00001066), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000100, 0x00000067), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000100, 0x00000068), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000100, 0x0000006b), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_H23, 0x84000102, 0x0000006c), /* GPIO */
+ /* GPIO Group GPD */
+ H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPD1, 0x84000102, 0x00000019), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPD2, 0x84000502, 0x0000001a), /* LAN_WAKE# */
+ H110_PAD_DW0_DW1_CFG(GPD3, 0x84000502, 0x0000001b), /* PWRBTN# */
+ H110_PAD_DW0_DW1_CFG(GPD4, 0x84000600, 0x0000001c), /* SLP_S3# */
+ H110_PAD_DW0_DW1_CFG(GPD5, 0x84000600, 0x0000001d), /* SLP_S4# */
+ H110_PAD_DW0_DW1_CFG(GPD6, 0x84000100, 0x0000001e), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPD8, 0x84000500, 0x00000020), /* SUSCLK */
+ H110_PAD_DW0_DW1_CFG(GPD9, 0x04000100, 0x00000021), /* SLP_WLAN# */
+ H110_PAD_DW0_DW1_CFG(GPD10, 0x84000100, 0x00000022), /* SLP_S5# */
+ H110_PAD_DW0_DW1_CFG(GPD11, 0x04000102, 0x00000023), /* GPIO */
+ /* GPIO Group GPP_I */
+ H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000500, 0x0000006d), /* DDPB_HPD0 */
+ H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000500, 0x0000006e), /* DDPC_HPD1 */
+ H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000100, 0x0000006f), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */
+ H110_PAD_DW0_DW1_CFG(GPP_I4, 0x04000100, 0x00001071), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */
+ H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00000073),
+ /* DDPB_CTRLDATA */
+ H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000502, 0x00000074),
+ /* DDPC_CTRLCLK */
+ H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000502, 0x00000075),
+ /* DDPC_CTRLDATA */
+ H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000102, 0x00000076), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000100, 0x00000077), /* GPIO */
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+ /* GPIO Group GPP_A */
+ H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
+ H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */
+ H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */
+ H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */
+ H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */
+ H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
+ H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
+ H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
+ H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
+ H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
+ /* ---- */
+ /* SUSWARN#/SUSPWRDNACK */
+ H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */
+ H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */
+ H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */
+};
+
+#endif
diff --git a/src/mainboard/asus/h110m-e_m2/mainboard.c b/src/mainboard/asus/h110m-e_m2/mainboard.c
new file mode 100644
index 0000000..4c1c6cd
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/mainboard.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+ * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/h110m-e_m2/ramstage.c b/src/mainboard/asus/h110m-e_m2/ramstage.c
new file mode 100644
index 0000000..c93e84c
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/ramstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation
+ * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "include/gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+ params->CdClock = 3;
+ /* Enable Virtual Channel 1 */
+ params->PchHdaVcType = 0x1;
+}
diff --git a/src/mainboard/asus/h110m-e_m2/romstage.c b/src/mainboard/asus/h110m-e_m2/romstage.c
new file mode 100644
index 0000000..ae5e297
--- /dev/null
+++ b/src/mainboard/asus/h110m-e_m2/romstage.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+#include <string.h>
+#include <spd_bin.h>
+
+#define RCOMP_TARGET_PARAMS 0x5
+
+static void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+static void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 200, 81, 162 };
+ memcpy(rcomp_ptr, RcompResistor,
+ sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
+ 100, 40, 40, 23, 40 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x51, 0x52, 0x53, },
+ };
+
+ mem_cfg = &mupd->FspmConfig;
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = 1;
+ get_spd_smbus(&blk);
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
+ mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
+ mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
+ dump_spd_info(&blk);
+
+ /* use virtual channel 1 for the dmi interface of the PCH */
+ mupd->FspmTestConfig.DmiVc1 = 1;
+
+ /* desktop type */
+ mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
+}
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