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Change in coreboot[master]: mb/google/drallion: Enable dynamic sar
by EricR Lai (Code Review) 14 Jan '20

14 Jan '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38386 ) Change subject: mb/google/drallion: Enable dynamic sar ...................................................................... mb/google/drallion: Enable dynamic sar Drallion will use two sar table for tablet and clam shell mode. BUG=b:140469407 TEST=Build and check the config has enable BRANCH=none Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I0367741e795a3b00c490ecb1972d22b9f454134f --- M src/mainboard/google/drallion/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38386/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index e9e26a3..a006858 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -24,6 +24,7 @@ select MAINBOARD_USES_IFD_EC_REGION select USE_SAR select SAR_ENABLE + select DSAR_ENABLE if BOARD_GOOGLE_BASEBOARD_DRALLION -- To view, visit https://review.coreboot.org/c/coreboot/+/38386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0367741e795a3b00c490ecb1972d22b9f454134f Gerrit-Change-Number: 38386 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Declare common smbus_base() and enable_smbus()
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38232 ) Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ...................................................................... sb/intel/common: Declare common smbus_base() and enable_smbus() This avoids including platform-specific headers with different filenames from common code. Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/smbus_host.h M src/northbridge/intel/gm45/raminit.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 20 files changed, 84 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/1 diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 2a02fb7..def6bbb 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -15,6 +15,7 @@ #define __DEVICE_SMBUS_HOST_H__ #include <stdint.h> +#include <console/console.h> /* Low-level SMBUS host controller. */ @@ -34,7 +35,17 @@ /* Upstream API */ +uintptr_t smbus_base(void); +int smbus_enable_iobar(uintptr_t base); void smbus_host_reset(uintptr_t base); void smbus_set_slave_addr(uintptr_t base, u8 slave_address); +static inline void enable_smbus(void) +{ + uintptr_t base = smbus_base(); + smbus_enable_iobar(base); + smbus_host_reset(base); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); +} + #endif diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b1da177..5de87cf 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -21,6 +21,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/device.h> +#include <device/smbus_host.h> #include <spd.h> #include <console/console.h> #include <lib.h> diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 62f8e42..8a6cdd4 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <mrc_cache.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -32,13 +33,18 @@ #include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h> -static void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_BASE_ADDRESS; +} + +int smbus_enable_iobar(uintptr_t base) { uint32_t reg; const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); /* SMBus I/O BAR */ - reg = SMBUS_BASE_ADDRESS | 2; + reg = base | 2; pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); /* Enable decode of I/O space. */ reg = pci_read_config16(smbus_dev, PCI_COMMAND); diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 4631652..114de95 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -42,6 +42,5 @@ void pch_uart_init(void); void intel_early_me_status(void); -void enable_smbus(void); #endif diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 5ecce28..3467720 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "pch.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; @@ -34,7 +39,7 @@ /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +47,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 5f353af..5348478 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -62,7 +62,6 @@ int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void enable_smbus(void); void enable_usb_bar(void); #if ENV_ROMSTAGE diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 917a3b4..78e4ecf 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -23,7 +23,12 @@ #include <device/smbus_host.h> #include "i82371eb.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; u8 reg8; @@ -34,7 +39,7 @@ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); /* Set the SMBus I/O base. */ - pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); + pci_write_config32(dev, SMBBA, base | 1); /* Enable the SMBus controller host interface. */ reg8 = pci_read_config8(dev, SMBHSTCFG); @@ -46,9 +51,7 @@ reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; } int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 55242ef..ea7efef 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,7 +19,6 @@ #if !defined(__ACPI__) -void enable_smbus(void); void enable_pm(void); #if ENV_ROMSTAGE diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 77b0aa0..163e8d2 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -16,25 +16,27 @@ #include <device/pci_ops.h> #include <device/pci_def.h> -#include <console/console.h> #include <device/smbus_host.h> #include "i82801dx.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* set smbus iobase */ - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config32(dev, 0x20, base | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 50122d8..9895de1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -35,7 +35,6 @@ #include "chip.h" void i82801dx_enable(struct device *dev); -void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 60fcceb..fdc98ab 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "i82801gx.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; @@ -33,7 +38,7 @@ /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -41,9 +46,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 0516a7a..688f1c3 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -37,7 +37,6 @@ #include <device/device.h> void i82801gx_enable(struct device *dev); -void enable_smbus(void); void i82801gx_lpc_setup(void); void i82801gx_setup_bars(void); void i82801gx_early_init(void); diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 4286760..678c653 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -22,7 +22,12 @@ #include <device/smbus_host.h> #include "i82801ix.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; @@ -35,7 +40,7 @@ /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -43,9 +48,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 906d24e..f60aad3 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -208,7 +208,6 @@ void aseg_smm_lock(void); -void enable_smbus(void); void i82801ix_early_init(void); void i82801ix_lpc_decode(void); void i82801ix_dmi_setup(void); diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 594400f..de48038 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -21,7 +21,12 @@ #include <device/smbus_host.h> #include "i82801jx.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; @@ -30,7 +35,7 @@ /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -38,9 +43,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 26a99f4..abf6187 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -226,7 +226,6 @@ #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) #if ENV_ROMSTAGE -void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index fdf0c32..4aefb0b 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "pch.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; @@ -34,7 +39,7 @@ /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +47,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 529b7a2..424bf42 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -52,7 +52,6 @@ #define DEBUG_PERIODIC_SMIS 0 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void enable_smbus(void); void enable_usb_bar(void); #if ENV_ROMSTAGE diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 5ecce28..3467720 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "pch.h" -void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; @@ -34,7 +39,7 @@ /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +47,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 71f42ea..9622c67 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -174,7 +174,6 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void enable_smbus(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); -- To view, visit https://review.coreboot.org/c/coreboot/+/38232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Gerrit-Change-Number: 38232 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail: Add SOUTHBRIDGE_INTEL_COMMON_SMBUS
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38236 ) Change subject: soc/intel/baytrail: Add SOUTHBRIDGE_INTEL_COMMON_SMBUS ...................................................................... soc/intel/baytrail: Add SOUTHBRIDGE_INTEL_COMMON_SMBUS Change-Id: Ie026b8c57046d951752158fd28277e338ed1421c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38236/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4e92237..1fd9c40 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,6 +18,7 @@ select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP -- To view, visit https://review.coreboot.org/c/coreboot/+/38236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie026b8c57046d951752158fd28277e338ed1421c Gerrit-Change-Number: 38236 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: intel/nehalem,ibexpeak: Move enable_smbus() call
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38297 ) Change subject: intel/nehalem,ibexpeak: Move enable_smbus() call ...................................................................... intel/nehalem,ibexpeak: Move enable_smbus() call Change-Id: I6e43f7696b289ce9e0319afdcc73889ddabd4db1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/early_pch.c 2 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/38297/1 diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 69383e6..eceb8c2 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -57,9 +57,6 @@ } } - /* Enable SMBUS. */ - enable_smbus(); - early_thermal_init(); timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index b76115b..e462dd8 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -44,6 +44,7 @@ void early_pch_init(void) { early_gpio_init(); + enable_smbus(); /* TODO, make this configurable */ pch_setup_cir(NEHALEM_MOBILE); southbridge_configure_default_intmap(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e43f7696b289ce9e0319afdcc73889ddabd4db1 Gerrit-Change-Number: 38297 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: crossgcc: Upgrade cmake to version 3.16.2
by HAOUAS Elyes (Code Review) 14 Jan '20

14 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38162 ) Change subject: crossgcc: Upgrade cmake to version 3.16.2 ...................................................................... crossgcc: Upgrade cmake to version 3.16.2 Aslo add comment on IASL conflicting use of _ADR and _HID. Change-Id: I2012f0adcb348a3ea6c50c361a49a0a600d3db3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum A util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/38162/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6150011..b862b9a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,13 +54,17 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 + +# Conflicting use of _ADR and _HID in coreboot tree needs +# to be properly # addressed before we can upgrade IASL version. +# Use IASL version 20190703 For now. IASL_VERSION=20190703 PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=9.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.16.0 +CMAKE_VERSION=3.16.2 NASM_VERSION=2.14.02 # GCC toolchain archive locations diff --git a/util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum deleted file mode 100644 index 0adcc1a..0000000 --- a/util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -9943ebbbf076bbe1b54c7dadcd6df28ad0d241ed tarballs/cmake-3.16.0.tar.gz diff --git a/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum new file mode 100644 index 0000000..c5190b2 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum @@ -0,0 +1 @@ +f514dbd9aa8332a28ba62dd8ce97b0aa0b099491 tarballs/cmake-3.16.2.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/38162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2012f0adcb348a3ea6c50c361a49a0a600d3db3d Gerrit-Change-Number: 38162 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: intel/sandybridge,bd82x6x: Move enable_smbus() call
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38298 ) Change subject: intel/sandybridge,bd82x6x: Move enable_smbus() call ...................................................................... intel/sandybridge,bd82x6x: Move enable_smbus() call Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_pch.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38298/1 diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 079e1b1..7d1c019 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -82,9 +82,6 @@ mainboard_early_init(s3resume); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - post_code(0x39); perform_raminit(s3resume); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index b19216b..6f06a57 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -327,4 +327,7 @@ pch_enable_gbe(); setup_pch_gpios(&mainboard_gpio_map); + + if (ENV_ROMSTAGE) + enable_smbus(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Gerrit-Change-Number: 38298 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: intel/x4x,i82801{ix|jx}: Move enable_smbus() call
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38268 ) Change subject: intel/x4x,i82801{ix|jx}: Move enable_smbus() call ...................................................................... intel/x4x,i82801{ix|jx}: Move enable_smbus() call Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/x4x/romstage.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/early_init.c 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/38268/1 diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index eae87f3..26d336b 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -34,8 +34,6 @@ u8 boot_path = 0; u8 s3_resume; - enable_smbus(); - #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) i82801jx_early_init(); #elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 92db7d8..4ce4fbe 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -23,6 +23,9 @@ { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + if (ENV_ROMSTAGE) + enable_smbus(); + /* Set up RCBA. */ pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 1afc6b3..87831bb 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -81,6 +81,9 @@ { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + if (ENV_ROMSTAGE) + enable_smbus(); + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); i82801jx_setup_bars(); printk(BIOS_DEBUG, " done.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/38268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e Gerrit-Change-Number: 38268 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: drivers/pc80/rtc: Clean up some POST_CODE_EXTRA use
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38188 ) Change subject: drivers/pc80/rtc: Clean up some POST_CODE_EXTRA use ...................................................................... drivers/pc80/rtc: Clean up some POST_CODE_EXTRA use Change-Id: I5ecfa0860a28547f76a72592a8d07bca67822217 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/post.c M src/include/console/console.h 2 files changed, 43 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38188/1 diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index e559edf..0d5d0e1 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -24,9 +24,7 @@ void cmos_post_log(void) { u8 code = 0; -#if CONFIG(CMOS_POST_EXTRA) u32 extra = 0; -#endif spin_lock(&cmos_post_lock); @@ -34,15 +32,13 @@ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: code = cmos_read(CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); -#endif + if (CONFIG(CMOS_POST_EXTRA)) + extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: code = cmos_read(CMOS_POST_BANK_0_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); -#endif + if (CONFIG(CMOS_POST_EXTRA)) + extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; } @@ -60,11 +56,9 @@ "in previous boot: 0x%02x\n", code); #if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); -#if CONFIG(CMOS_POST_EXTRA) - if (extra) + if (CONFIG(CMOS_POST_EXTRA) && extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); #endif -#endif } } @@ -83,49 +77,15 @@ /* Initialize to zero */ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); -#endif + if (CONFIG(CMOS_POST_EXTRA)) { + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); + } } cmos_write(magic, CMOS_POST_BANK_OFFSET); } -#if CONFIG(CMOS_POST_EXTRA) -void post_log_extra(u32 value) -{ - spin_lock(&cmos_post_lock); - - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - cmos_write32(value, CMOS_POST_BANK_0_EXTRA); - break; - case CMOS_POST_BANK_1_MAGIC: - cmos_write32(value, CMOS_POST_BANK_1_EXTRA); - break; - } - - spin_unlock(&cmos_post_lock); -} - -void post_log_path(const struct device *dev) -{ - if (dev) { - /* Encode path into lower 3 bytes */ - u32 path = dev_path_encode(dev); - /* Upper byte contains the log type */ - path |= CMOS_POST_EXTRA_DEV_PATH << 24; - post_log_extra(path); - } -} - -void post_log_clear(void) -{ - post_log_extra(0); -} -#endif /* CONFIG_CMOS_POST_EXTRA */ - void cmos_post_code(u8 value) { spin_lock(&cmos_post_lock); @@ -141,3 +101,37 @@ spin_unlock(&cmos_post_lock); } + +static void __unused cmos_post_extra(u32 value) +{ + spin_lock(&cmos_post_lock); + + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write32(value, CMOS_POST_BANK_0_EXTRA); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write32(value, CMOS_POST_BANK_1_EXTRA); + break; + } + + spin_unlock(&cmos_post_lock); +} + +#if CONFIG(CMOS_POST_EXTRA) +void post_log_path(const struct device *dev) +{ + if (dev) { + /* Encode path into lower 3 bytes */ + u32 path = dev_path_encode(dev); + /* Upper byte contains the log type */ + path |= CMOS_POST_EXTRA_DEV_PATH << 24; + cmos_post_extra(path); + } +} + +void post_log_clear(void) +{ + cmos_post_extra(0); +} +#endif /* CONFIG_CMOS_POST_EXTRA */ diff --git a/src/include/console/console.h b/src/include/console/console.h index c573123..9983cef 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -32,12 +32,10 @@ void arch_post_code(u8 value); void cmos_post_code(u8 value); #if CONFIG(CMOS_POST_EXTRA) -void post_log_extra(u32 value); struct device; void post_log_path(const struct device *dev); void post_log_clear(void); #else -#define post_log_extra(x) do {} while (0) #define post_log_path(x) do {} while (0) #define post_log_clear() do {} while (0) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ecfa0860a28547f76a72592a8d07bca67822217 Gerrit-Change-Number: 38188 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: console/post: Split parts to arch/
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38187 ) Change subject: console/post: Split parts to arch/ ...................................................................... console/post: Split parts to arch/ Both IO port and cmos are currently arch/x86 only features. Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc A src/arch/x86/post.c M src/console/post.c M src/include/console/console.h 4 files changed, 37 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38187/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6ed93e5..534f2ce 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -99,6 +99,7 @@ all-y += memcpy.c all-y += memset.c all-y += cpu_common.c +all-y += post.c endif diff --git a/src/arch/x86/post.c b/src/arch/x86/post.c new file mode 100644 index 0000000..0a20bab --- /dev/null +++ b/src/arch/x86/post.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <console/console.h> +#include <arch/io.h> + +void arch_post_code(uint8_t value) +{ + if (CONFIG(POST_IO)) + outb(value, CONFIG_POST_IO_PORT); + + if (CONFIG(CMOS_POST)) + cmos_post_code(value); +} diff --git a/src/console/post.c b/src/console/post.c index b9a7557..33d85e7 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -14,11 +14,9 @@ #include <stdint.h> #include <console/console.h> -#if CONFIG(POST_IO) -#include <arch/io.h> -#endif /* Write POST information */ +void __weak arch_post_code(uint8_t value) { } /* Some mainboards have very nice features beyond just a simple display. * They can override this function. @@ -27,16 +25,13 @@ void post_code(uint8_t value) { -#if !CONFIG(NO_POST) -#if CONFIG(CONSOLE_POST) - printk(BIOS_EMERG, "POST: 0x%02x\n", value); -#endif -#if CONFIG(CMOS_POST) - cmos_post_code(value); -#endif -#if CONFIG(POST_IO) - outb(value, CONFIG_POST_IO_PORT); -#endif -#endif + if (!CONFIG(NO_POST)) { + /* Assume this to be the most reliable and simplest type + for displaying POST so keep it first. */ + arch_post_code(value); + + if (CONFIG(CONSOLE_POST)) + printk(BIOS_EMERG, "POST: 0x%02x\n", value); + } mainboard_post(value); } diff --git a/src/include/console/console.h b/src/include/console/console.h index d3c1d54..c573123 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -29,6 +29,7 @@ #include <console/vtxprintf.h> void post_code(u8 value); +void arch_post_code(u8 value); void cmos_post_code(u8 value); #if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value); -- To view, visit https://review.coreboot.org/c/coreboot/+/38187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2 Gerrit-Change-Number: 38187 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: util/crossgcc: Add comment on IASL version
by HAOUAS Elyes (Code Review) 14 Jan '20

14 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38164 ) Change subject: util/crossgcc: Add comment on IASL version ...................................................................... util/crossgcc: Add comment on IASL version Change-Id: I81c6f4134610bcd35e173cdb002ef821788b0538 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/38164/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6150011..b3b92d4 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,6 +54,10 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 + +# Conflicting use of _ADR and _HID in coreboot tree needs +# to be properly addressed before we can upgrade IASL version. +# Use IASL version 20190703 for now. IASL_VERSION=20190703 PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 -- To view, visit https://review.coreboot.org/c/coreboot/+/38164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81c6f4134610bcd35e173cdb002ef821788b0538 Gerrit-Change-Number: 38164 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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