coreboot-gerrit January 2020

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Change in coreboot[master]: soc/intel/common/systemagent: add Kconfig guard
by Andrey Petrov (Code Review) 15 Jan '20

15 Jan '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38013 ) Change subject: soc/intel/common/systemagent: add Kconfig guard ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/38013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b9e18f6169d91732a1db7e8eabf137b66072dd Gerrit-Change-Number: 38013 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 Jan 2020 23:30:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: /mb/google/hatch/variants/helios: Remove MAX98357A devicetree entry
by Tim Wawrzynczak (Code Review) 15 Jan '20

15 Jan '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38398 ) Change subject: /mb/google/hatch/variants/helios: Remove MAX98357A devicetree entry ...................................................................... Patch Set 1: Good catch, thanks! Can we add BRANCH=firmware-hatch-12672.B for reference? -- To view, visit https://review.coreboot.org/c/coreboot/+/38398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id02410553f018385d407086b2f9bc3ee1e7a5f40 Gerrit-Change-Number: 38398 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Jan 2020 23:26:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Nick Vaccaro (Code Review) 14 Jan '20

14 Jan '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 17: (3 comments) https://review.coreboot.org/c/coreboot/+/37427/17//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37427/17//COMMIT_MSG@13 PS17, Line 13: .G nit - space needed https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… PS17, Line 4: 2019 2020 https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… PS17, Line 4: 2019 2020 -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 17 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 14 Jan 2020 21:13:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: document non-Docker sphinx installation and usage
by Felix Held (Code Review) 14 Jan '20

14 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37952 ) Change subject: Documentation: document non-Docker sphinx installation and usage ...................................................................... Documentation: document non-Docker sphinx installation and usage Change-Id: I0f63860beb0a8a00360752318236e302c7170977 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37952/1 diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index dc3cd34..51c248f 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -45,6 +45,22 @@ The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and recommonmark 0.4.0. +Since some Linux distributions don't package every needed sphinx extension, +the installation via pip in a venv is recommended. You'll need these python3 +modules: + +* sphinx +* recommonmark +* sphinx_rtd_theme +* sphinxcontrib-ditaa + +Now cd into the Documentation folder and run + + make sphinx + +If no error occurs, you can find the generated HTML documentation in +Documentation/_build now. + ### Optional Install [sphinx-autobuild] for rebuilding markdown/rst sources on the fly! -- To view, visit https://review.coreboot.org/c/coreboot/+/37952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f63860beb0a8a00360752318236e302c7170977 Gerrit-Change-Number: 37952 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/{i945,pineview},i82801gx: Move enable_smbus() call
by Kyösti Mälkki (Code Review) 14 Jan '20

14 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38296 ) Change subject: intel/{i945,pineview},i82801gx: Move enable_smbus() call ...................................................................... intel/{i945,pineview},i82801gx: Move enable_smbus() call Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/early_init.c 3 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/38296/1 diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 4795881..ff4ccc1 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -61,9 +61,6 @@ s3resume = southbridge_detect_s3_resume(); - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - mainboard_pre_raminit_config(s3resume); if (CONFIG(DEBUG_RAM_SETUP)) diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index e324c05..ce4cd55 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -51,8 +51,6 @@ enable_lapic(); - enable_smbus(); - /* Perform some early chipset initialization required * before RAM initialization can work */ diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index f91a5dc..29c4550 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -73,6 +73,9 @@ { uint8_t reg8; uint32_t reg32; + + enable_smbus(); + /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); i82801gx_setup_bars(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5 Gerrit-Change-Number: 38296 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: dedede: Add dedede mainboard
by Karthik Ramasubramanian (Code Review) 14 Jan '20

14 Jan '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38277 ) Change subject: dedede: Add dedede mainboard ...................................................................... dedede: Add dedede mainboard Add mainboard stubs for Dedede. More functionalities will be added later. BUG=b:144768001 TEST=Build test. Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- A src/mainboard/google/dedede/Kconfig A src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/Makefile.inc A src/mainboard/google/dedede/board_info.txt A src/mainboard/google/dedede/bootblock.c A src/mainboard/google/dedede/mainboard.c A src/mainboard/google/dedede/romstage.c A src/mainboard/google/dedede/variants/baseboard/devicetree.cb 8 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38277/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig new file mode 100644 index 0000000..02e4e51 --- /dev/null +++ b/src/mainboard/google/dedede/Kconfig @@ -0,0 +1,35 @@ +config BOARD_GOOGLE_BASEBOARD_DEDEDE + def_bool n + select SOC_INTEL_JASPERLAKE + +if BOARD_GOOGLE_BASEBOARD_DEDEDE + +config BASEBOARD_DEDEDE_LAPTOP + def_bool n + select SYSTEM_TYPE_LAPTOP + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "google/dedede" + +config MAINBOARD_FAMILY + string + default "Google_Dedede" if BOARD_GOOGLE_DEDEDE + +config MAINBOARD_PART_NUMBER + string + default "dedede" if BOARD_GOOGLE_DEDEDE + +config MAX_CPUS + int + default 4 + +config UART_FOR_CONSOLE + int + default 2 + +endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name new file mode 100644 index 0000000..ff5411b --- /dev/null +++ b/src/mainboard/google/dedede/Kconfig.name @@ -0,0 +1,4 @@ +config BOARD_GOOGLE_DEDEDE + bool "Dedede" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc new file mode 100644 index 0000000..be05b6b --- /dev/null +++ b/src/mainboard/google/dedede/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += bootblock.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard diff --git a/src/mainboard/google/dedede/board_info.txt b/src/mainboard/google/dedede/board_info.txt new file mode 100644 index 0000000..db769af --- /dev/null +++ b/src/mainboard/google/dedede/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Dedede +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/dedede/bootblock.c b/src/mainboard/google/dedede/bootblock.c new file mode 100644 index 0000000..11186f7 --- /dev/null +++ b/src/mainboard/google/dedede/bootblock.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ + /* TODO: Perform mainboard initialization */ +} diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c new file mode 100644 index 0000000..51b1aa4 --- /dev/null +++ b/src/mainboard/google/dedede/mainboard.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + /* TODO: Perform mainboard initialization */ +} + +static void mainboard_enable(struct device *dev) +{ + /* TODO: Enable mainboard */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c new file mode 100644 index 0000000..bba6e1a --- /dev/null +++ b/src/mainboard/google/dedede/romstage.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <fsp/api.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* ToDo : Fill FSP-M memory params */ +} diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..eb9dc1c --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/tigerlake + device cpu_cluster 0 on + device lapic 0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/38277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc Gerrit-Change-Number: 38277 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Update Kconfig
by Wonkyu Kim (Code Review) 14 Jan '20

14 Jan '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38148 ) Change subject: mb/intel/tglrvp: Update Kconfig ...................................................................... mb/intel/tglrvp: Update Kconfig Update Kconfig to add Tigerlake RVP board specific configs. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ia63c06e3b4b4effcace7a8458b1066a615de2008 --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 36 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38148/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index bee72cf..45093f0 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -3,19 +3,24 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 - select EC_ACPI - select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_MAX98373 select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select GENERATE_SMBIOS_TABLES select SOC_INTEL_TIGERLAKE - select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + config MAINBOARD_DIR string default "intel/tglrvp" @@ -24,6 +29,11 @@ string default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3 +config GBB_HWID + string + depends on CHROMEOS + default "TGLRVP" if BOARD_INTEL_TGLRVP_UP3 + config MAINBOARD_PART_NUMBER string default "tglrvp" @@ -44,9 +54,31 @@ int default 512 +choice TGL_EC + prompt "ON BOARD EC" + default TGL_CHROME_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config TGL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + +config TGL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config UART_FOR_CONSOLE int -- To view, visit https://review.coreboot.org/c/coreboot/+/38148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia63c06e3b4b4effcace7a8458b1066a615de2008 Gerrit-Change-Number: 38148 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Add initial mainboard code
by Patrick Georgi (Code Review) 14 Jan '20

14 Jan '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37868 ) Change subject: mb/intel/tglrvp: Add initial mainboard code ...................................................................... mb/intel/tglrvp: Add initial mainboard code This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Tigerlake". 2. Replace "icelake_rvp" with "tglrvp". 3. Rename "icl" with "tgl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake". 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add board support namely BOARD_INTEL_TGLRVP_UP3 10. Replace icl_u and icl_y variant with tglrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per tigerlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 32MB BIOS region. 5. clean up and make empty devicetree setting TEST=Build tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- A src/mainboard/intel/tglrvp/Kconfig A src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/acpi/mainboard.asl A src/mainboard/intel/tglrvp/board_id.c A src/mainboard/intel/tglrvp/board_id.h A src/mainboard/intel/tglrvp/board_info.txt A src/mainboard/intel/tglrvp/bootblock.c A src/mainboard/intel/tglrvp/chromeos.c A src/mainboard/intel/tglrvp/chromeos.fmd A src/mainboard/intel/tglrvp/dsdt.asl A src/mainboard/intel/tglrvp/mainboard.c A src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/empty.spd.hex A src/mainboard/intel/tglrvp/spd/spd.h A src/mainboard/intel/tglrvp/spd/spd_util.c A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb A src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 23 files changed, 961 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig new file mode 100644 index 0000000..bee72cf --- /dev/null +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -0,0 +1,54 @@ +if BOARD_INTEL_TGLRVP_UP3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select EC_ACPI + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select GENERIC_SPD_BIN + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_USB_ACPI + select SOC_INTEL_TIGERLAKE + select MAINBOARD_USES_IFD_EC_REGION + select INTEL_LPSS_UART_FOR_CONSOLE + +config MAINBOARD_DIR + string + default "intel/tglrvp" + +config VARIANT_DIR + string + default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3 + +config MAINBOARD_PART_NUMBER + string + default "tglrvp" + +config MAINBOARD_FAMILY + string + default "Intel_tglrvp" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + +config UART_FOR_CONSOLE + int + default 2 +endif diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name new file mode 100644 index 0000000..a2271f3 --- /dev/null +++ b/src/mainboard/intel/tglrvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_TGLRVP_UP3 + bool "Tigerlake UP3 DDR4/LPDDR4 RVP" diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc new file mode 100644 index 0000000..81cbc6e --- /dev/null +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -0,0 +1,35 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += mainboard.c +ramstage-y += board_id.c + +subdirs-y += ../common +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl new file mode 100644 index 0000000..6647ac1 --- /dev/null +++ b/src/mainboard/intel/tglrvp/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(EC_GOOGLE_CHROMEEC) +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif diff --git a/src/mainboard/intel/tglrvp/board_id.c b/src/mainboard/intel/tglrvp/board_id.c new file mode 100644 index 0000000..2331256 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_id.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <ec/google/chromeec/ec.h> +#include <stdint.h> + +#include "board_id.h" + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + id = get_board_id_via_ext_ec(); + } else { + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + return id; +} diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h new file mode 100644 index 0000000..9aac527 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +#include <stdint.h> + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/tglrvp/board_info.txt b/src/mainboard/intel/tglrvp/board_info.txt new file mode 100644 index 0000000..cecc5b4 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Tigerlake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c new file mode 100644 index 0000000..01b257c --- /dev/null +++ b/src/mainboard/intel/tglrvp/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c new file mode 100644 index 0000000..372f6ce --- /dev/null +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd new file mode 100644 index 0000000..bfbd304 --- /dev/null +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1081000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x1000000 + } + SI_BIOS@0x1400000 0xC00000 { + RW_SECTION_A@0x0 0x2d0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bffc0 + RW_FWID_A@0x2cffc0 0x40 + } + RW_SECTION_B@0x2d0000 0x2d0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bffc0 + RW_FWID_B@0x2cffc0 0x40 + } + RW_MISC@0x5a0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + SMMSTORE@0x5d0000 0x40000 + RW_LEGACY(CBFS)@0x610000 0x1c0000 + WP_RO@0x7d0000 0x430000 { + RO_VPD@0x0 0x4000 + RO_SECTION@0x4000 0x42c000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x33c000 + } + } + } +} diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl new file mode 100644 index 0000000..559e1e3 --- /dev/null +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/tigerlake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + } + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Mainboard specific */ + #include "acpi/mainboard.asl" + +} diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c new file mode 100644 index 0000000..d74c11c --- /dev/null +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c new file mode 100644 index 0000000..0ab1f48 --- /dev/null +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* ToDo : Fill FSP-M memory params */ +} diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc new file mode 100644 index 0000000..b8b059a --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b000 diff --git a/src/mainboard/intel/tglrvp/spd/empty.spd.hex b/src/mainboard/intel/tglrvp/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h new file mode 100644 index 0000000..ed8b8b6 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <stdint.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); +void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/intel/tglrvp/spd/spd_util.c b/src/mainboard/intel/tglrvp/spd/spd_util.c new file mode 100644 index 0000000..4bfd964 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/spd_util.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <stdint.h> +#include <string.h> + +#include "../board_id.h" +#include "spd.h" + +enum tgl_dimm_type { + tgl_u_ddr4 = 0, + tgl_u_lpddr4 = 1, + tgl_u_lpddr4_type_3 = 4, + tgl_y_lpddr4 = 6 +}; + +static uint8_t get_spd_index(void) +{ + uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; + + return spd_index; +} + +void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr) +{ + /* DQ byte map Ch0 */ + const u8 dq_map[12] = { + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr) +{ + const u8 dq_map[12] = { + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map Ch0 */ + const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; + const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; + const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + + switch (get_spd_index()) { + case tgl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case tgl_u_lpddr4: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case tgl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, + sizeof(dqs_map_u_lpddr_type_3)); + break; + case tgl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } +} + +void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map Ch1 */ + const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; + const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; + + switch (get_spd_index()) { + case tgl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case tgl_u_lpddr4: + case tgl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case tgl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } +} + +void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 100, 100, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { + 100, 33, 32, 33, 28 }; + static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { + 80, 40, 40, 40, 30 }; + + switch (get_spd_index()) { + case tgl_u_ddr4: + memcpy(rcomp_strength_ptr, RcompTarget_DDR4, + sizeof(RcompTarget_DDR4)); + break; + case tgl_y_lpddr4: + case tgl_u_lpddr4: + case tgl_u_lpddr4_type_3: + memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, + sizeof(RcompTarget_LPDDR4_Ax)); + break; + default: + break; + } +} diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..a8a147a --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..227ec75 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..9220b11 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc new file mode 100644 index 0000000..23bf160 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb new file mode 100644 index 0000000..6a4bae8 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -0,0 +1,78 @@ +chip soc/intel/tigerlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 08.0 off end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 off end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 on end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + device pci 13.0 off end # GSPI3 0xA0FD + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 on end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 15.0 on end # I2C0 0xA0E8 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + device pci 17.0 off end # SATA 0xA0D3 + device pci 19.0 off end # I2C4 0xA0C5 + device pci 19.1 on end # I2C5 0xA0C6 + device pci 19.2 on end # UART2 0xA0C7 + device pci 1c.0 off end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 on end # RP3 0xA0BA + device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 off end # RP6 0xA0BD + device pci 1c.6 off end # RP7 0xA0BE + device pci 1c.7 off end # RP8 0xA0BF + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 on end # RP10 0xA0B1 + device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1e.0 off end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 off end # GSPI0 0xA0AA + device pci 1e.3 off end # GSPI1 0xA0AB + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 on end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 on end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 + end +end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c new file mode 100644 index 0000000..48ad36e --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ToDo: Fill gpio configuration */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* ToDo: Fill early gpio configurations for TPM and WWAN */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Gerrit-Change-Number: 37868 Gerrit-PatchSet: 19 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload: cbgfx: Support drawing a box with rounded corners
by Yu-Ping Wu (Code Review) 14 Jan '20

14 Jan '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37757 ) Change subject: libpayload: cbgfx: Support drawing a box with rounded corners ...................................................................... libpayload: cbgfx: Support drawing a box with rounded corners A function draw_rounded_box() is added to draw a box with rounded corners. In addition, this function is different from draw_box() in 2 ways: - The position and size arguments are relative to the canvas - This function supports drawing only the border of a box (linear time complexity when the thickness is fixed) BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie480410d2fd8316462d5ff874999ae2317de04f9 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M payloads/libpayload/drivers/video/graphics.c M payloads/libpayload/include/cbgfx.h 2 files changed, 167 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/37757/1 diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 6b5664b..cf206a7 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -243,6 +243,154 @@ return CBGFX_SUCCESS; } +int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, + const struct rgb_color *rgb, + const struct fraction *thickness, + const struct fraction *radius) +{ + struct vector top_left; + struct vector size; + struct vector p, t; + + if (cbgfx_init()) + return CBGFX_ERROR_INIT; + + const uint32_t color = calculate_color(rgb, 0); + + transform_vector(&top_left, &canvas.size, pos_rel, &canvas.offset); + transform_vector(&size, &canvas.size, dim_rel, &vzero); + add_vectors(&t, &top_left, &size); + if (within_box(&t, &canvas) < 0) { + LOG("Box exceeds canvas boundary\n"); + return CBGFX_ERROR_BOUNDARY; + } + + if (!is_valid_fraction(thickness) || !is_valid_fraction(radius)) + return CBGFX_ERROR_INVALID_PARAMETER; + + struct scale thickness_scale = { + .x = { .n = thickness->n, .d = thickness->d }, + .y = { .n = thickness->n, .d = thickness->d }, + }; + struct scale radius_scale = { + .x = { .n = radius->n, .d = radius->d }, + .y = { .n = radius->n, .d = radius->d }, + }; + struct vector d, r, s; + transform_vector(&d, &canvas.size, &thickness_scale, &vzero); + transform_vector(&r, &canvas.size, &radius_scale, &vzero); + const uint8_t has_thickness = d.x > 0 && d.y > 0; + const uint8_t has_radius = r.x > 0 && r.y > 0; + if (has_radius) { + if (d.x > r.x || d.y > r.y) { + LOG("Thickness cannot be greater than radius\n"); + return CBGFX_ERROR_INVALID_PARAMETER; + } + if (r.x * 2 > t.x - top_left.x || r.y * 2 > t.y - top_left.y) { + LOG("Radius cannot be greater than half of the box\n"); + return CBGFX_ERROR_INVALID_PARAMETER; + } + } + + /* Step 1: Draw edges */ + uint32_t x_begin, x_end; + if (has_thickness) { + /* top */ + for (p.y = top_left.y; p.y < top_left.y + d.y; p.y++) + for (p.x = top_left.x + r.x; p.x < t.x - r.x; p.x++) + set_pixel(&p, color); + /* bottom */ + for (p.y = t.y - d.y; p.y < t.y; p.y++) + for (p.x = top_left.x + r.x; p.x < t.x - r.x; p.x++) + set_pixel(&p, color); + for (p.y = top_left.y + r.y; p.y < t.y - r.y; p.y++) { + /* left */ + for (p.x = top_left.x; p.x < top_left.x + d.x; p.x++) + set_pixel(&p, color); + /* right */ + for (p.x = t.x - d.x; p.x < t.x; p.x++) + set_pixel(&p, color); + } + } else { + /* Fill the regions except circular sectors */ + for (p.y = top_left.y; p.y < t.y; p.y++) { + if (p.y >= top_left.y + r.y && p.y < t.y - r.y) { + x_begin = top_left.x; + x_end = t.x; + } else { + x_begin = top_left.x + r.x; + x_end = t.x - r.x; + } + for (p.x = x_begin; p.x < x_end; p.x++) + set_pixel(&p, color); + } + } + + if (!has_radius) + return CBGFX_SUCCESS; + + /* Step 2: Draw rounded corners + * When has_thickness, only the border is drawn. With fixed thickness, + * the time complexity is linear to the size of the box. + */ + if (has_thickness) { + s.x = r.x - d.x; + s.y = r.y - d.y; + } else { + s.x = r.x; + s.y = r.y; + } + + /* Use 64 bits to avoid overflow */ + uint64_t x, y, yy; + const uint64_t rrx = r.x * r.x, rry = r.y * r.y; + const uint64_t ssx = s.x * s.x, ssy = s.y * s.y; + x_begin = 0; + x_end = 0; + for (y = r.y; y-- > 0;) { + /* The inequality is valid in the beginning of each iteration: + * y^2 + x_end^2 < r^2 + */ + yy = y * y; + /* Check yy/ssy + xx/ssx < 1 */ + while (yy * ssx + x_begin * x_begin * ssy < ssx * ssy) + x_begin++; + /* The inequality must be valid now: y^2 + x_begin >= s^2 */ + x = x_begin; + /* Check yy/rry + xx/rrx < 1 */ + while (x < x_end || yy * rrx + x * x * rry < rrx * rry) { + /* Example sequence of (y, x) when s = (4, 4) and + * r = (5, 5): + * [(4, 0), (4, 1), (4, 2), (3, 3), (2, 4), + * (1, 4), (0, 4)]. + * If s.x==s.y r.x==r.y, then the sequence will be + * symmetric, and x and y will range from 0 to (r-1). + */ + /* top left */ + p.y = top_left.y + r.y - 1 - y; + p.x = top_left.x + r.x - 1 - x; + set_pixel(&p, color); + /* top right */ + p.y = top_left.y + r.y - 1 - y; + p.x = t.x - r.x + x; + set_pixel(&p, color); + /* bottom left */ + p.y = t.y - r.y + y; + p.x = top_left.x + r.x - 1 - x; + set_pixel(&p, color); + /* bottom right */ + p.y = t.y - r.y + y; + p.x = t.x - r.x + x; + set_pixel(&p, color); + x++; + } + x_end = x; + /* (x_begin <= x_end) must hold now */ + } + + return CBGFX_SUCCESS; +} + int clear_canvas(const struct rgb_color *rgb) { const struct rect box = { diff --git a/payloads/libpayload/include/cbgfx.h b/payloads/libpayload/include/cbgfx.h index cffc7fd..ed2d10e 100644 --- a/payloads/libpayload/include/cbgfx.h +++ b/payloads/libpayload/include/cbgfx.h @@ -115,6 +115,25 @@ int draw_box(const struct rect *box, const struct rgb_color *rgb); /** + * Draw a box with rounded corners on screen. + * + * @param[in] pos_rel Coordinate of the top left corner of the box relative to + * the canvas. + * @param[in] dim_rel Width and height of the image relative to the canvas. + * @param[in] rgb Color of the border of the box. + * @param[in] thickness Thickness of the border relative to the canvas. If zero + * is given, the box will be filled with the rgb color. + * @param[in] radius Radius of the rounded corners relative to the canvas. A + * zero value indicates sharps corner will be drawn. + * + * @return CBGFX_* error codes + */ +int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, + const struct rgb_color *rgb, + const struct fraction *thickness, + const struct fraction *radius); + +/** * Clear the canvas */ int clear_canvas(const struct rgb_color *rgb); -- To view, visit https://review.coreboot.org/c/coreboot/+/37757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie480410d2fd8316462d5ff874999ae2317de04f9 Gerrit-Change-Number: 37757 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: Support panels using ANX7625
by Hung-Te Lin (Code Review) 14 Jan '20

14 Jan '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36767 ) Change subject: mb/google/kukui: Support panels using ANX7625 ...................................................................... mb/google/kukui: Support panels using ANX7625 For Kukui followers using ANX7625 eDP bridge to access panel. BUG=b:140132295 TEST=make # board = kukui Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/panel_anx7625.c 3 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/36767/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index e6d604e..3b53478 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -42,6 +42,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_JUNIPER || BOARD_GOOGLE_DAMU || BOARD_GOOGLE_KAPPA select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE config MAINBOARD_DIR diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 2e8a79a..7839422 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -30,4 +30,6 @@ ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c + ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c new file mode 100644 index 0000000..10cbf5c --- /dev/null +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> +#include <string.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_PP1200_MIPIBRDG_EN, 1); //1.0 + gpio_output(GPIO_VDDIO_MIPIBRDG_EN, 1); //3.3 + gpio_output(GPIO_PP1800_LCM_EN, 1); //1.8 + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 4; + mtk_i2c_bus_init(i2c_bus); + + anx7625_init(i2c_bus); + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid\n"); + return NULL; + } + anx7625_dp_start(i2c_bus, edid); + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Gerrit-Change-Number: 36767 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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