coreboot-gerrit January 2020

coreboot-gerrit@coreboot.org

1 participants
1869 discussions

Change in coreboot[master]: soc/intel/tigerlake: Add asl support for USBC
by Shaunak Saha (Code Review) 15 Jan '20

15 Jan '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38439 ) Change subject: soc/intel/tigerlake: Add asl support for USBC ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/38439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44fd726c14f96bd3c963f17ec8e0abc956a76ebd Gerrit-Change-Number: 38439 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Jan 2020 19:37:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset
by Michał Żygowski (Code Review) 15 Jan '20

15 Jan '20

Hello Piotr Kleinschmidt, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38274 to review the following change. Change subject: mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset ...................................................................... mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset LDN 0xf keeps registers with open-drain configuration of the GPIO. Enabling the LDN is required for proper GPIO soft reset operation by the SuperIO driver. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6 --- M src/mainboard/pcengines/apu1/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38274/1 diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 2e8b8f4..d7c7952 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -63,12 +63,12 @@ irq 0x70 = 3 end device pnp 2e.8 off end - device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end device pnp 2e.e off end + device pnp 2e.f on end end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 6728228..b888ae7 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -65,12 +65,12 @@ irq 0x70 = 3 end device pnp 2e.8 off end - device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.e off end + device pnp 2e.f on end end # SIO NCT5104D chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 0c0c21e..ad29965 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -65,12 +65,12 @@ irq 0x70 = 3 end device pnp 2e.8 off end - device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.e off end + device pnp 2e.f on end end # SIO NCT5104D end # LPC 0x439d diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index c93c04f..c5b20c9 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -65,12 +65,12 @@ irq 0x70 = 3 end device pnp 2e.8 off end - device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.e off end + device pnp 2e.f on end end # SIO NCT5104D end # LPC 0x439d -- To view, visit https://review.coreboot.org/c/coreboot/+/38274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6 Gerrit-Change-Number: 38274 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: src/superio/nuvoton/nct5104d: soft reset GPIO
by Piotr Kleinschmidt (Code Review) 15 Jan '20

15 Jan '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35482 ) Change subject: src/superio/nuvoton/nct5104d: soft reset GPIO ...................................................................... src/superio/nuvoton/nct5104d: soft reset GPIO So far, only hard power off could reset GPIOs state to defaults: IN, Open-drain. Now, defaults are set with every boot to ensure that GPIOS are not in uknown/unwanted state. Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/superio/nuvoton/nct5104d/nct5104d.h M src/superio/nuvoton/nct5104d/superio.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35482/1 diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index 707e94a..6826bb6 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -21,15 +21,25 @@ #include <device/pnp_type.h> /* SIO global configuration */ +#define LDN_SELECT_CR07 0x07 #define IRQ_TYPE_SEL_CR10 0x10 /* UARTA,UARTB */ #define IRQ_TYPE_SEL_CR11 0x11 /* SMI,UARTC,UARTD,WDTO */ #define GLOBAL_OPTION_CR26 0x26 #define CR26_LOCK_REG (1 << 4) /* required to access CR10/CR11 */ +/* LDN 0x07 specific registers */ +#define NCT5104D_GPIO0_IO 0xE0 +#define NCT5104D_GPIO1_IO 0xE4 + +/* LDN 0x0F specific registers */ +#define NCT5104D_GPIO0_PP_OD 0xE0 +#define NCT5104D_GPIO1_PP_OD 0xE1 + /* Logical Device Numbers (LDN). */ #define NCT5104D_FDC 0x00 /* FDC - not pinned out */ #define NCT5104D_SP1 0x02 /* UARTA */ #define NCT5104D_SP2 0x03 /* UARTB */ +#define NCT5104D_GPIO 0x07 /* GPIO In-Out configuration */ #define NCT5104D_GPIO_WDT 0x08 /* GPIO WDT Interface */ #define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */ #define NCT5104D_SP3 0x10 /* UARTC */ diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 40d1200..53eb99d 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -106,6 +106,19 @@ pnp_write_config(dev, 0x1c, reg); } +static void reset_gpio(struct device *dev) +{ + /* Soft reset GPIOs to default state: IN, Open-drain */ + + pnp_write_config(dev, LDN_SELECT_CR07, NCT5104D_GPIO); + pnp_write_config(dev, NCT5104D_GPIO0_IO, 0xFF); + pnp_write_config(dev, NCT5104D_GPIO1_IO, 0xFF); + + pnp_write_config(dev, LDN_SELECT_CR07, NCT5104D_GPIO_PP_OD); + pnp_write_config(dev, NCT5104D_GPIO0_PP_OD, 0xFF); + pnp_write_config(dev, NCT5104D_GPIO1_PP_OD, 0xFF); +} + static void nct5104d_init(struct device *dev) { struct superio_nuvoton_nct5104d_config *conf = dev->chip_info; @@ -127,6 +140,7 @@ break; case NCT5104D_GPIO0: case NCT5104D_GPIO1: + reset_gpio(dev); route_pins_to_uart(dev, false); break; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/35482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Gerrit-Change-Number: 35482 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by build bot (Jenkins) (Code Review) 15 Jan '20

15 Jan '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 55: (10 comments) https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 101: if (!cse_update_boot_partition_info()) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 260: (bp_status == BP_STATUS_GENERAL_FAILURE || bp_status == BP_STATUS_CORRUPTED)) { line over 96 characters https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 216: /* trailing whitespace https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 217: * The status is return when BIOS requests CSE for boot switch. trailing whitespace https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 218: * This value isn't applicable to chrome platforms trailing whitespace https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 230: /* trailing whitespace https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 279: * then this command be used. Inorder to set CSE to boot from RW/RO, coreboot/BIOS must issue trailing whitespace https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 281: * NOTE: During CSE FW update, coreboot can notify CSE to boot from RO(BP1), and shall issue trailing whitespace https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 311: bool cse_get_bp_entry_status(enum boot_partition_id boot_partition, uint8_t *boot_partition_status); line over 96 characters https://review.coreboot.org/c/coreboot/+/35402/55/src/soc/intel/common/bloc… PS55, Line 317: bool cse_get_bp_entry_version(enum boot_partition_id boot_partition, struct partition_fw_version *fw_version); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 55 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 18:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 15 Jan '20

15 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, V Sowmya, Andrey Petrov, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#49). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 4.1MB. * FMAP changes to accommodate ME update binary in RW CBFSes & larger CSE binary. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update - Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. - Send global reset command to reset only the CSME - Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) - Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command - Erase and Copy the CBFS ME RW to ME RW partition - Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command - Trigger global reset The system should boot with the Updated ME Verified basic update flows on Cometlake RVP and hatch. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A Documentation/soc/intel/cse_fw_update/Layout_after.svg A Documentation/soc/intel/cse_fw_update/Layout_before.svg A Documentation/soc/intel/cse_fw_update/cse_fw_update.md M Documentation/soc/intel/index.md A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 8 files changed, 861 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/49 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 49 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 15 Jan '20

15 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#55). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse.c A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 518 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/55 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 55 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC ...
by Sridhar Siricilla (Code Review) 15 Jan '20

15 Jan '20

Sridhar Siricilla has uploaded a new patch set (#25) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific ...................................................................... soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific Move me_hfsts1 structure from common code to SoC specific. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c A src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/include/soc/me.h A src/soc/intel/icelake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/me.h A src/soc/intel/tigerlake/me.c 14 files changed, 567 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 25 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/fast_spi: don't include all spi flash drivers
by Aaron Durbin (Code Review) 15 Jan '20

15 Jan '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38363 ) Change subject: soc/intel/common/block/fast_spi: don't include all spi flash drivers ...................................................................... soc/intel/common/block/fast_spi: don't include all spi flash drivers The fast spi driver implements hardware sequencing which abstracts away the underlying spi flash commands in the hardware block. It also has its own spi flash probe function to intercept the spi flash ops. As such it's not necessary to include all spi flash drivers. On a hatch Chrome OS build this saves 9.5KiB of text in each of verstage, romstage, and ramstage. Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/block/fast_spi/Kconfig M src/soc/intel/skylake/Kconfig 3 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38363/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c2d2eae..0d69da2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -106,7 +106,6 @@ select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI - select SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index 4bd1f59..9369272 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_FAST_SPI bool + select SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS help Intel Processor common FAST_SPI support diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a2fbdff..9674024 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -77,7 +77,6 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING - select SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS config FSP_HYPERTHREADING bool "Enable Hyper-Threading" -- To view, visit https://review.coreboot.org/c/coreboot/+/38363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa Gerrit-Change-Number: 38363 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: drives/spi/spi_flash: add option to not select all drivers
by Aaron Durbin (Code Review) 15 Jan '20

15 Jan '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38362 ) Change subject: drives/spi/spi_flash: add option to not select all drivers ...................................................................... drives/spi/spi_flash: add option to not select all drivers Add a new Kconfig option, SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS, to make it easier for other parts of the code base to indicate that all spi flash drivers should not be included. Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/drivers/spi/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/skylake/Kconfig 3 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/38362/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index a4be84d..c9d94d9 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -61,9 +61,14 @@ Include the common implementation in all stages, including the early ones. +config SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS + bool + default y if COMMON_CBFS_SPI_WRAPPER + default n + config SPI_FLASH_INCLUDE_ALL_DRIVERS bool - default n if COMMON_CBFS_SPI_WRAPPER + default n if SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS default y config SPI_FLASH_SMM diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2f4ebb0..c2d2eae 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -106,6 +106,7 @@ select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -341,10 +342,6 @@ default 0x400000 if SOC_INTEL_GLK default 0x100000 -config SPI_FLASH_INCLUDE_ALL_DRIVERS - bool - default n - config SMM_RESERVED_SIZE hex default 0x100000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d90fb6b..a2fbdff 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -77,6 +77,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS config FSP_HYPERTHREADING bool "Enable Hyper-Threading" @@ -232,10 +233,6 @@ depends on FSP_USE_REPO default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" -config SPI_FLASH_INCLUDE_ALL_DRIVERS - bool - default n - config MAX_ROOT_PORTS int default 24 -- To view, visit https://review.coreboot.org/c/coreboot/+/38362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea Gerrit-Change-Number: 38362 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/tigerlake: Update header files
by Ravishankar Sarawadi (Code Review) 15 Jan '20

15 Jan '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37782 ) Change subject: soc/intel/tigerlake: Update header files ...................................................................... soc/intel/tigerlake: Update header files Modify header files to update/include tigerlake: - IOMAP BARs - PCI devices - Serial IO devices - IRQ mapping BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80 --- M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/serialio.h 4 files changed, 171 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37782/1 diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index b3797c1..e87956d 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -34,11 +34,19 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define EARLY_I2C_BASE_ADDRESS 0xfe040000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) +#define UART_BASE_SIZE 0x1000 -#define MCH_BASE_ADDRESS 0xfed10000 -#define MCH_BASE_SIZE 0x8000 +#define UART_BASE_0_ADDRESS 0xFE03E000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define EARLY_I2C_BASE_ADDRESS 0xFE020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 #define DMI_BASE_ADDRESS 0xfeda0000 #define DMI_BASE_SIZE 0x1000 @@ -49,7 +57,7 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 -#define REG_BASE_ADDRESS 0xfc000000 +#define REG_BASE_ADDRESS 0xfb000000 #define REG_BASE_SIZE 0x1000 #define HPET_BASE_ADDRESS 0xfed00000 @@ -58,7 +66,7 @@ #define PCH_PWRM_BASE_SIZE 0x10000 #define SPI_BASE_ADDRESS 0xfe010000 -#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 +#define EARLY_GSPI_BASE_ADDRESS 0xFE030000 #define GPIO_BASE_SIZE 0x10000 diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 2f980ff..ccd358d 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,91 +16,107 @@ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 -#define SCI_IRQ9 9 -#define SCI_IRQ10 10 -#define SCI_IRQ11 11 -#define SCI_IRQ20 20 -#define SCI_IRQ21 21 -#define SCI_IRQ22 22 -#define SCI_IRQ23 23 +#define SCI_IRQ9 9 +#define SCI_IRQ10 10 +#define SCI_IRQ11 11 +#define SCI_IRQ20 20 +#define SCI_IRQ21 21 +#define SCI_IRQ22 22 +#define SCI_IRQ23 23 -#define TCO_IRQ9 9 -#define TCO_IRQ10 10 -#define TCO_IRQ11 11 -#define TCO_IRQ20 20 -#define TCO_IRQ21 21 -#define TCO_IRQ22 22 -#define TCO_IRQ23 23 +#define TCO_IRQ9 9 +#define TCO_IRQ10 10 +#define TCO_IRQ11 11 +#define TCO_IRQ20 20 +#define TCO_IRQ21 21 +#define TCO_IRQ22 22 +#define TCO_IRQ23 23 -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 -#define SDIO_IRQ 22 +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_I2C6_IRQ 16 +#define LPSS_I2C7_IRQ 17 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 24 +#define LPSS_SPI3_IRQ 23 +#define LPSS_SPI4_IRQ 24 +#define LPSS_SPI5_IRQ 25 +#define LPSS_SPI6_IRQ 38 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 +#define LPSS_UART3_IRQ 19 +#define LPSS_UART4_IRQ 20 +#define LPSS_UART5_IRQ 21 +#define LPSS_UART6_IRQ 22 -#define cAVS_INTA_IRQ 16 -#define SMBUS_INTA_IRQ 16 -#define SMBUS_INTB_IRQ 17 -#define GbE_INTA_IRQ 16 -#define GbE_INTC_IRQ 18 -#define TRACE_HUB_INTA_IRQ 16 -#define TRACE_HUB_INTD_IRQ 19 +#define SDIO_IRQ 22 -#define eMMC_IRQ 16 -#define SD_IRQ 19 +#define eSPI_IRQ 16 +#define P2SB_IRQ 17 +#define PMC_IRQ 18 +#define HDA_IRQ 19 -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 +#define eMMC_IRQ 16 +#define SD_IRQ 19 -#define SATA_IRQ 16 +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define IDER_IRQ 18 -#define KT_IRQ 19 -#define HECI_3_IRQ 16 +#define SATA_IRQ 16 -#define XHCI_IRQ 16 -#define OTG_IRQ 17 -#define PMC_SRAM_IRQ 18 -#define THERMAL_IRQ 16 -#define CNViWIFI_IRQ 19 -#define UFS_IRQ 16 -#define CIO_INTA_IRQ 16 -#define CIO_INTD_IRQ 19 -#define ISH_IRQ 20 +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define IDER_IRQ 18 +#define KT_IRQ 19 +#define HECI_3_IRQ 16 -#define PEG_RP_INTA_IRQ 16 -#define PEG_RP_INTB_IRQ 17 -#define PEG_RP_INTC_IRQ 18 -#define PEG_RP_INTD_IRQ 19 +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define USB2_xHCI_IRQ 16 +#define USB2_xDCI_IRQ 17 +#define PMC_SRAM_IRQ 18 +#define THERMAL_IRQ 16 +#define CNViBT_IRQ 18 +#define CNViWIFI_IRQ 19 +#define UFS_IRQ 16 +#define CIO_INTA_IRQ 16 +#define CIO_INTD_IRQ 19 +#define ISH_IRQ 16 -#define IGFX_IRQ 16 -#define SA_THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define PEG_RP_INTA_IRQ 16 +#define PEG_RP_INTB_IRQ 17 +#define PEG_RP_INTC_IRQ 18 +#define PEG_RP_INTD_IRQ 19 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f54ab4b..5b7695c 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -39,32 +39,70 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) -#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) -#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) /* PCH Devices */ -#define PCH_DEV_SLOT_THERMAL 0x12 -#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) -#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6) -#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0) -#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5) -#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6) +#define PCH_DEV_SLOT_TBT 0x07 +#define PCH_DEVFN_TBT0 _PCH_DEVFN(TBT, 0) +#define PCH_DEVFN_TBT1 _PCH_DEVFN(TBT, 1) +#define PCH_DEVFN_TBT2 _PCH_DEVFN(TBT, 2) +#define PCH_DEVFN_TBT3 _PCH_DEVFN(TBT, 3) +#define PCH_DEV_TBT0 _PCH_DEV(TBT, 0) +#define PCH_DEV_TBT1 _PCH_DEV(TBT, 1) +#define PCH_DEV_TBT2 _PCH_DEV(TBT, 2) +#define PCH_DEV_TBT3 _PCH_DEV(TBT, 3) -#define PCH_DEV_SLOT_ISH 0x13 +#define PCH_DEV_SLOT_SIO4 0x10 +#define PCH_DEVFN_I2C6 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO4, 2) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO4, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO4, 7) +#define PCH_DEV_I2C6 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C7 _PCH_DEV(SIO4, 1) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO4, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO4, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO4, 7) + +#define PCH_DEV_SLOT_SIO5 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART4 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_UART5 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_UART6 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART3 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART4 _PCH_DEV(SIO5, 1) +#define PCH_DEV_UART5 _PCH_DEV(SIO5, 2) +#define PCH_DEV_UART6 _PCH_DEV(SIO5, 3) + +#define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_THERMAL _PCH_DEVFN(ISH, 1) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) #define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_THERMAL _PCH_DEV(ISH, 1) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO6 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO6, 0) +#define PCH_DEVFN_GSPI4 _PCH_DEVFN(SIO6, 1) +#define PCH_DEVFN_GSPI5 _PCH_DEVFN(SIO6, 2) +#define PCH_DEVFN_GSPI6 _PCH_DEVFN(SIO6, 3) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO6, 0) +#define PCH_DEV_GSPI4 _PCH_DEV(SIO6, 1) +#define PCH_DEV_GSPI5 _PCH_DEV(SIO6, 2) +#define PCH_DEV_GSPI6 _PCH_DEV(SIO6, 3) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) #define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) #define PCH_DEV_SLOT_SIO1 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) diff --git a/src/soc/intel/tigerlake/include/soc/serialio.h b/src/soc/intel/tigerlake/include/soc/serialio.h index cdf5515..0bf795cf 100644 --- a/src/soc/intel/tigerlake/include/soc/serialio.h +++ b/src/soc/intel/tigerlake/include/soc/serialio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,19 +30,29 @@ PchSerialIoIndexI2C2, PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, - PchSerialIoIndexI2C5 + PchSerialIoIndexI2C5, + PchSerialIoIndexI2C6, + PchSerialIoIndexI2C7 }; enum { PchSerialIoIndexGSPI0, PchSerialIoIndexGSPI1, - PchSerialIoIndexGSPI2 + PchSerialIoIndexGSPI2, + PchSerialIoIndexGSPI3, + PchSerialIoIndexGSPI4, + PchSerialIoIndexGSPI5, + PchSerialIoIndexGSPI6, }; enum { PchSerialIoIndexUART0, PchSerialIoIndexUART1, - PchSerialIoIndexUART2 + PchSerialIoIndexUART2, + PchSerialIoIndexUART3, + PchSerialIoIndexUART4, + PchSerialIoIndexUART5, + PchSerialIoIndexUART6, }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80 Gerrit-Change-Number: 37782 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

6 24

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2020