coreboot-gerrit January 2020

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Change in coreboot[master]: autoport: Use HTTPS URLs
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38435 ) Change subject: autoport: Use HTTPS URLs ...................................................................... autoport: Use HTTPS URLs Update the two flashrom URLs to use HTTPS. All other URLs are already using HTTPS. Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/autoport/readme.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38435/1 diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 6d1c64c..b73b441 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -63,7 +63,7 @@ Disassemble your computer and find the flash chip(s). Since there could be more than one, this guide will refer to "flash chips" as one or more chips. -Refer to <http://flashrom.org/Technology> as a reference. The flash chip is +Refer to <https://flashrom.org/Technology> as a reference. The flash chip is usually in a `SOIC-8` (2x4 pins, 200mil) or `SOIC-16` (2x8 pins) package. As it can be seen on flashrom's wiki, the former package is like any other 8-pin chip on the mainboard, but it is slightly larger. The latter package is much @@ -282,7 +282,7 @@ * `ROM package`, `ROM protocol` and `ROM socketed`: These refer to the flash chips you found earlier. You can visit - <http://flashrom.org/Technology> for more information. + <https://flashrom.org/Technology> for more information. * `Release year`: Use the power of Internet to find that information. * `Category`: This describes the type of mainboard you have. -- To view, visit https://review.coreboot.org/c/coreboot/+/38435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3 Gerrit-Change-Number: 38435 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Subrata Banik (Code Review) 15 Jan '20

15 Jan '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 3: Code-Review+2 i believe this is good candidate for common code of TCSS. Thoughts ? -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 3 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 14:31:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Get Type-C Mux info from EC
by Subrata Banik (Code Review) 15 Jan '20

15 Jan '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 ) Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.c File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.… PS2, Line 1420: /** : * : */ this is not good practice, either prefer to use comment section else don't keep this at all -- To view, visit https://review.coreboot.org/c/coreboot/+/37867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96bfb6036f4340ba42a078cfd7ecaae777a3ed00 Gerrit-Change-Number: 37867 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 15 Jan 2020 14:28:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/systemagent: add Kconfig guard
by Nico Huber (Code Review) 15 Jan '20

15 Jan '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38013 ) Change subject: soc/intel/common/systemagent: add Kconfig guard ...................................................................... Patch Set 2: I don't mind such guards. But the reason seems spurious as it seems to work fine everywhere. There are some pitfalls, maybe something is wrong with the way your platform is hooked up? If you look at `soc/intel/Kconfig` all plat- forms precede the `source` for `common/Kconfig`, so they can set a different default (and the first default takes precedence in Kconfig). -- To view, visit https://review.coreboot.org/c/coreboot/+/38013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b9e18f6169d91732a1db7e8eabf137b66072dd Gerrit-Change-Number: 38013 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 14:28:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/i2c: add i2c driver for Realtek 1308
by Subrata Banik (Code Review) 15 Jan '20

15 Jan '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37882 ) Change subject: src/drivers/i2c: add i2c driver for Realtek 1308 ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/37882/2/src/drivers/i2c/rt1308/chi… File src/drivers/i2c/rt1308/chip.h: https://review.coreboot.org/c/coreboot/+/37882/2/src/drivers/i2c/rt1308/chi… PS2, Line 26: uint32_t if intention is only 0 or 1 then i believe Paul is right about the usage of variable. but definition and variable name doesn't look same. uid could be any thing not only 0 or 1 https://review.coreboot.org/c/coreboot/+/37882/2/src/drivers/i2c/rt1308/rt1… File src/drivers/i2c/rt1308/rt1308.c: https://review.coreboot.org/c/coreboot/+/37882/2/src/drivers/i2c/rt1308/rt1… PS2, Line 23: #include <stdint.h> redundant i believe already part of header https://review.coreboot.org/c/coreboot/+/37882/2/src/drivers/i2c/rt1308/rt1… PS2, Line 25: #include "chip.h" can u use this one rather being direct #include <soc/soc_chip.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44fc8199f2153e18537023dfd92e0ce6a3ecb9c Gerrit-Change-Number: 37882 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 15 Jan 2020 14:26:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 59: (3 comments) https://review.coreboot.org/c/coreboot/+/21774/59//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/21774/59//COMMIT_MSG@14 PS59, Line 14: - MT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 *three* is before the list, and the list has four items. Make it clear, that the first two boards are identical? https://review.coreboot.org/c/coreboot/+/21774/59//COMMIT_MSG@42 PS59, Line 42: - VBT is missing Are VBT’s needed for desktop systems? https://review.coreboot.org/c/coreboot/+/21774/59/src/mainboard/dell/optipl… File src/mainboard/dell/optiplex_790/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/21774/59/src/mainboard/dell/optipl… PS59, Line 18: */ This is not added in the latest autoport version. -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 59 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Wed, 15 Jan 2020 14:20:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: refactor lane_registers[]
by Felix Held (Code Review) 15 Jan '20

15 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38405 ) Change subject: nb/intel/sandybridge: refactor lane_registers[] ...................................................................... nb/intel/sandybridge: refactor lane_registers[] Rename array and use defines for the values. The patch doesn't change the resulting binary when using BUILD_TIMELESS=1 Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 23 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38405/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4c36600..e7d5ac5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1040,10 +1040,10 @@ } } -static const u32 lane_registers[] = { - 0x0000, 0x0200, 0x0400, 0x0600, - 0x1000, 0x1200, 0x1400, 0x1600, - 0x0800 +static const u32 lane_base[] = { + LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, + LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, + LANEBASE_ECC }; void program_timings(ramctr_timing *ctrl, int channel) @@ -1155,9 +1155,7 @@ shift_402x) << (8 * slotrank); FOR_ALL_LANES { - MCHBAR32(lane_registers[lane] + 0x10 + channel * 0x100 + - 4 * slotrank) - = + MCHBAR32(lane_base[lane] + 0x10 + channel * 0x100 + 4 * slotrank) = (((ctrl->timings[channel][slotrank].lanes[lane]. timA + shift) & 0x3f) | @@ -1170,9 +1168,7 @@ | ((ctrl->timings[channel][slotrank].lanes[lane]. falling + shift) << 20)); - MCHBAR32(lane_registers[lane] + 0x20 + channel * 0x100 + - 4 * slotrank) - = + MCHBAR32(lane_base[lane] + 0x20 + channel * 0x100 + 4 * slotrank) = (((ctrl->timings[channel][slotrank].lanes[lane]. timC + shift) & 0x3f) | @@ -1232,7 +1228,7 @@ int lane) { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; - return ((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 + + return ((MCHBAR32(lane_base[lane] + channel * 0x100 + 4 + ((timA / 32) & 1) * 4) >> (timA % 32)) & 1); } @@ -1894,7 +1890,7 @@ FOR_ALL_LANES { statistics[lane][timB] = - !((MCHBAR32(lane_registers[lane] + + !((MCHBAR32(lane_base[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); } @@ -2017,9 +2013,8 @@ wait_for_iosav(channel); FOR_ALL_LANES { - u64 res = MCHBAR32(lane_registers[lane] + channel * 0x100 + 4); - res |= ((u64) MCHBAR32(lane_registers[lane] + - channel * 0x100 + 8)) << 32; + u64 res = MCHBAR32(lane_base[lane] + channel * 0x100 + 4); + res |= ((u64) MCHBAR32(lane_base[lane] + channel * 0x100 + 8)) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; @@ -3025,9 +3020,9 @@ int channel, slotrank; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(0x0004 + channel * 0x100 + lane_registers[slotrank]) = + MCHBAR32(0x0004 + channel * 0x100 + lane_base[slotrank]) = make_mr0(ctrl, slotrank); - MCHBAR32(0x0008 + channel * 0x100 + lane_registers[slotrank]) = + MCHBAR32(0x0008 + channel * 0x100 + lane_base[slotrank]) = make_mr1(ctrl, slotrank, channel); } } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index f12feaa..53fb3eb 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -133,6 +133,17 @@ #define Cx(r, x) ((r) + ((x) * 0x400)) #define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4)) +/* byte lane training register base addresses */ +#define LANEBASE_B0 0x0000 +#define LANEBASE_B1 0x0200 +#define LANEBASE_B2 0x0400 +#define LANEBASE_B3 0x0600 +#define LANEBASE_B4 0x1000 +#define LANEBASE_B5 0x1200 +#define LANEBASE_B6 0x1400 +#define LANEBASE_B7 0x1600 +#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ + /* Register definitions */ #define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ #define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678 Gerrit-Change-Number: 38405 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add ECC detection support
by Felix Held (Code Review) 15 Jan '20

15 Jan '20

Felix Held has uploaded a new patch set (#6) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/22214 ) Change subject: nb/intel/sandybridge/raminit: Add ECC detection support ...................................................................... nb/intel/sandybridge/raminit: Add ECC detection support Add support for detection ECC capability and forced ECC mode. Print the ECC mode in verbose debugging mode. Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/22214/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/22214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a Gerrit-Change-Number: 22214 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb: Add Dell OptiPlex 990
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38406 ) Change subject: mb: Add Dell OptiPlex 990 ...................................................................... mb: Add Dell OptiPlex 990 Old firmware was running. DMI: Dell Inc. OptiPlex 990/06D7TR, BIOS A03 04/11/2011 The system does not boot. Fan are spinning. Nothing on serial. Change-Id: I765911caa921b3dde0e35c628818a108e49714e0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> dell/optiplex_990: Re-run current autoport Change-Id: Ibf30d058f321affe40633c38df30e8d89868c1c2 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/optiplex_990/Kconfig A src/mainboard/dell/optiplex_990/Kconfig.name A src/mainboard/dell/optiplex_990/Makefile.inc A src/mainboard/dell/optiplex_990/acpi/ec.asl A src/mainboard/dell/optiplex_990/acpi/platform.asl A src/mainboard/dell/optiplex_990/acpi/superio.asl A src/mainboard/dell/optiplex_990/acpi_tables.c A src/mainboard/dell/optiplex_990/board_info.txt A src/mainboard/dell/optiplex_990/devicetree.cb A src/mainboard/dell/optiplex_990/dsdt.asl A src/mainboard/dell/optiplex_990/early_init.c A src/mainboard/dell/optiplex_990/gpio.c A src/mainboard/dell/optiplex_990/hda_verb.c A src/mainboard/dell/optiplex_990/mainboard.c 16 files changed, 562 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38406/1 diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000..298c62b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000..3d2fefd --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/optiplex_990/Kconfig b/src/mainboard/dell/optiplex_990/Kconfig new file mode 100644 index 0000000..4e45cb9 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/Kconfig @@ -0,0 +1,33 @@ +if BOARD_DELL_OPTIPLEX_990 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_10240 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default dell/optiplex_990 + +config MAINBOARD_PART_NUMBER + string + default "OptiPlex 990" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/optiplex_990/Kconfig.name b/src/mainboard/dell/optiplex_990/Kconfig.name new file mode 100644 index 0000000..873a6c5 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_OPTIPLEX_990 + bool "OptiPlex 990" diff --git a/src/mainboard/dell/optiplex_990/Makefile.inc b/src/mainboard/dell/optiplex_990/Makefile.inc new file mode 100644 index 0000000..3465dfe --- /dev/null +++ b/src/mainboard/dell/optiplex_990/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c diff --git a/src/mainboard/dell/optiplex_990/acpi/ec.asl b/src/mainboard/dell/optiplex_990/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/acpi/ec.asl diff --git a/src/mainboard/dell/optiplex_990/acpi/platform.asl b/src/mainboard/dell/optiplex_990/acpi/platform.asl new file mode 100644 index 0000000..0222986 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/dell/optiplex_990/acpi/superio.asl b/src/mainboard/dell/optiplex_990/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/acpi/superio.asl diff --git a/src/mainboard/dell/optiplex_990/acpi_tables.c b/src/mainboard/dell/optiplex_990/acpi_tables.c new file mode 100644 index 0000000..cfc2061 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/optiplex_990/board_info.txt b/src/mainboard/dell/optiplex_990/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/optiplex_990/devicetree.cb b/src/mainboard/dell/optiplex_990/devicetree.cb new file mode 100644 index 0000000..999c190 --- /dev/null +++ b/src/mainboard/dell/optiplex_990/devicetree.cb @@ -0,0 +1,107 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000400e1" + register "gen4_dec" = "0x001c02d1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1028 0x047e + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x047e + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1028 0x047e + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x047e + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x1028 0x047e + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x047e + end + device pci 1e.0 on # PCI bridge + subsystemid 0x1028 0x047e + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1028 0x047e + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1028 0x047e + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x047e + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1028 0x047e + end + device pci 01.0 on # PEG + subsystemid 0x1028 0x047e + end + device pci 02.0 off # iGPU + end + end +end diff --git a/src/mainboard/dell/optiplex_990/dsdt.asl b/src/mainboard/dell/optiplex_990/dsdt.asl new file mode 100644 index 0000000..b00a7ff --- /dev/null +++ b/src/mainboard/dell/optiplex_990/dsdt.asl @@ -0,0 +1,29 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/optiplex_990/early_init.c b/src/mainboard/dell/optiplex_990/early_init.c new file mode 100644 index 0000000..9e30fdd --- /dev/null +++ b/src/mainboard/dell/optiplex_990/early_init.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 7 }, + { 1, 0, 6 }, + { 1, 0, 6 }, + { 1, 0, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/optiplex_990/gpio.c b/src/mainboard/dell/optiplex_990/gpio.c new file mode 100644 index 0000000..da88c2b --- /dev/null +++ b/src/mainboard/dell/optiplex_990/gpio.c @@ -0,0 +1,217 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio11 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio49 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio74 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/optiplex_990/hda_verb.c b/src/mainboard/dell/optiplex_990/hda_verb.c new file mode 100644 index 0000000..ac509bf --- /dev/null +++ b/src/mainboard/dell/optiplex_990/hda_verb.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_990/mainboard.c b/src/mainboard/dell/optiplex_990/mainboard.c new file mode 100644 index 0000000..e5cfebf --- /dev/null +++ b/src/mainboard/dell/optiplex_990/mainboard.c @@ -0,0 +1,15 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf30d058f321affe40633c38df30e8d89868c1c2 Gerrit-Change-Number: 38406 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

1 5

Change in coreboot[master]: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro
by Angel Pons (Code Review) 15 Jan '20

15 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38338 ) Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ...................................................................... nb/intel/sandybridge: Repurpose HOST_BRIDGE macro There are more instances of PCI_DEV(0, 0, 0), so use the macro for them. Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38338/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3e17328..fc4e6f9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -497,7 +497,7 @@ } } -#define HOST_BRIDGE PCI_DEVFN(0, 0) +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define DEFAULT_TCK TCK_800MHZ unsigned int get_mem_min_tck(void) @@ -507,7 +507,7 @@ const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg = NULL; - dev = pcidev_path_on_root(HOST_BRIDGE); + dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); if (dev) cfg = dev->chip_info; @@ -516,11 +516,11 @@ if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) return TCK_1333MHZ; - rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { /* read Capabilities A Register DMFC bits */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); reg32 &= 0x7; switch (reg32) { @@ -533,7 +533,7 @@ } } else { /* read Capabilities B Register DMFC bits */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); reg32 = (reg32 >> 4) & 0x7; switch (reg32) { @@ -573,7 +573,7 @@ const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg = NULL; - dev = pcidev_path_on_root(HOST_BRIDGE); + dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); if (dev) cfg = dev->chip_info; @@ -643,97 +643,97 @@ printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); // TOM (top of memory) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM); + reg = pci_read_config32(HOST_BRIDGE, TOM); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOM, reg); + pci_write_config32(HOST_BRIDGE, TOM, reg); - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM + 4); + reg = pci_read_config32(HOST_BRIDGE, TOM + 4); val = tom & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOM + 4, reg); + pci_write_config32(HOST_BRIDGE, TOM + 4, reg); // TOLUD (top of low used dram) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOLUD); + reg = pci_read_config32(HOST_BRIDGE, TOLUD); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOLUD, reg); + pci_write_config32(HOST_BRIDGE, TOLUD, reg); // TOUUD LSB (top of upper usable dram) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD); + reg = pci_read_config32(HOST_BRIDGE, TOUUD); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOUUD, reg); + pci_write_config32(HOST_BRIDGE, TOUUD, reg); // TOUUD MSB - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD + 4); + reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOUUD + 4, reg); + pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); if (reclaim) { // REMAP BASE - pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE, remapbase << 20); - pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE + 4, remapbase >> 12); + pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); + pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); // REMAP LIMIT - pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT, remaplimit << 20); - pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT + 4, remaplimit >> 12); + pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); + pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); } // TSEG - reg = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB); + reg = pci_read_config32(HOST_BRIDGE, TSEGMB); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TSEGMB, reg); + pci_write_config32(HOST_BRIDGE, TSEGMB, reg); // GFX stolen memory - reg = pci_read_config32(PCI_DEV(0, 0, 0), BDSM); + reg = pci_read_config32(HOST_BRIDGE, BDSM); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), BDSM, reg); + pci_write_config32(HOST_BRIDGE, BDSM, reg); // GTT stolen memory - reg = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); + reg = pci_read_config32(HOST_BRIDGE, BGSM); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg); + pci_write_config32(HOST_BRIDGE, BGSM, reg); if (me_uma_size) { - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4); + reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4, reg); + pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); // ME base - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE); + reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE, reg); + pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4); + reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4, reg); + pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); // ME mask - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); + reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = reg | ME_STLEN_EN; // set ME memory enable reg = reg | MELCK; // set lockbit on ME mem printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); + pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Gerrit-Change-Number: 38338 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020