Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
nb/intel/sandybridge: Repurpose HOST_BRIDGE macro
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them.
Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38338/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3e17328..fc4e6f9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -497,7 +497,7 @@ } }
-#define HOST_BRIDGE PCI_DEVFN(0, 0) +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define DEFAULT_TCK TCK_800MHZ
unsigned int get_mem_min_tck(void) @@ -507,7 +507,7 @@ const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg = NULL;
- dev = pcidev_path_on_root(HOST_BRIDGE); + dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); if (dev) cfg = dev->chip_info;
@@ -516,11 +516,11 @@ if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) return TCK_1333MHZ;
- rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID);
if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { /* read Capabilities A Register DMFC bits */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); reg32 &= 0x7;
switch (reg32) { @@ -533,7 +533,7 @@ } } else { /* read Capabilities B Register DMFC bits */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); reg32 = (reg32 >> 4) & 0x7;
switch (reg32) { @@ -573,7 +573,7 @@ const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg = NULL;
- dev = pcidev_path_on_root(HOST_BRIDGE); + dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); if (dev) cfg = dev->chip_info;
@@ -643,97 +643,97 @@ printk(BIOS_DEBUG, "Update PCI-E configuration space:\n");
// TOM (top of memory) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM); + reg = pci_read_config32(HOST_BRIDGE, TOM); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOM, reg); + pci_write_config32(HOST_BRIDGE, TOM, reg);
- reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM + 4); + reg = pci_read_config32(HOST_BRIDGE, TOM + 4); val = tom & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOM + 4, reg); + pci_write_config32(HOST_BRIDGE, TOM + 4, reg);
// TOLUD (top of low used dram) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOLUD); + reg = pci_read_config32(HOST_BRIDGE, TOLUD); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOLUD, reg); + pci_write_config32(HOST_BRIDGE, TOLUD, reg);
// TOUUD LSB (top of upper usable dram) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD); + reg = pci_read_config32(HOST_BRIDGE, TOUUD); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOUUD, reg); + pci_write_config32(HOST_BRIDGE, TOUUD, reg);
// TOUUD MSB - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD + 4); + reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOUUD + 4, reg); + pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg);
if (reclaim) { // REMAP BASE - pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE, remapbase << 20); - pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE + 4, remapbase >> 12); + pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); + pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12);
// REMAP LIMIT - pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT, remaplimit << 20); - pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT + 4, remaplimit >> 12); + pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); + pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); } // TSEG - reg = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB); + reg = pci_read_config32(HOST_BRIDGE, TSEGMB); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TSEGMB, reg); + pci_write_config32(HOST_BRIDGE, TSEGMB, reg);
// GFX stolen memory - reg = pci_read_config32(PCI_DEV(0, 0, 0), BDSM); + reg = pci_read_config32(HOST_BRIDGE, BDSM); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), BDSM, reg); + pci_write_config32(HOST_BRIDGE, BDSM, reg);
// GTT stolen memory - reg = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); + reg = pci_read_config32(HOST_BRIDGE, BGSM); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg); + pci_write_config32(HOST_BRIDGE, BGSM, reg);
if (me_uma_size) { - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4); + reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4, reg); + pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg);
// ME base - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE); + reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE, reg); + pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg);
- reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4); + reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4, reg); + pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg);
// ME mask - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); + reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = reg | ME_STLEN_EN; // set ME memory enable reg = reg | MELCK; // set lockbit on ME mem printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); + pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); } }
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 510: dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); pcidev_on_root(0, 0)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 576: dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); ditto
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 512: cfg = dev->chip_info; or even `cfg = config_of_soc();` (returns non-NULL or dies)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 510: dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
pcidev_on_root(0, 0)
Would it change the binary? If so, I shall do it in a follow-up
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 512: cfg = dev->chip_info;
or even `cfg = config_of_soc();` (returns non-NULL or dies)
That would change the binary, I guess
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 510: dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
Would it change the binary? If so, I shall do it in a follow-up
It would. If if's the intention to keep it unchanged, please mention that in the commit message.
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 512: cfg = dev->chip_info;
That would change the binary, I guess
Ack
Hello Patrick Rudolph, Felix Held, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38338
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
nb/intel/sandybridge: Repurpose HOST_BRIDGE macro
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them.
Tested with BUILD_TIMELESS=1, resulting binary is identical.
Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38338/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 3:
(1 comment)
Let's hope Jenkins likes this.
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 510: dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
It would. If if's the intention to keep it unchanged, please mention that […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 510: dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
Done
Not really, you have written that it was tested this way, not that you wrote weird code to achieve that.
Hello Patrick Rudolph, Felix Held, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38338
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
nb/intel/sandybridge: Repurpose HOST_BRIDGE macro
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them. Note that the resulting code with PCI_DEVFN(0, 0) is weird. It shall be replaced with config_of_soc() in a follow-up.
Tested with BUILD_TIMELESS=1, resulting binary is identical.
Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38338/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 510: dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
Not really, you have written that it was tested this way, not that you […]
Done (try #2)
https://review.coreboot.org/c/coreboot/+/38338/1/src/northbridge/intel/sandy... PS1, Line 576: dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
ditto
Ack
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 4: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
nb/intel/sandybridge: Repurpose HOST_BRIDGE macro
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them. Note that the resulting code with PCI_DEVFN(0, 0) is weird. It shall be replaced with config_of_soc() in a follow-up.
Tested with BUILD_TIMELESS=1, resulting binary is identical.
Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38338 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4c36600..795775c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -497,7 +497,7 @@ } }
-#define HOST_BRIDGE PCI_DEVFN(0, 0) +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define DEFAULT_TCK TCK_800MHZ
unsigned int get_mem_min_tck(void) @@ -507,7 +507,7 @@ const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg = NULL;
- dev = pcidev_path_on_root(HOST_BRIDGE); + dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); if (dev) cfg = dev->chip_info;
@@ -516,11 +516,11 @@ if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) return TCK_1333MHZ;
- rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID);
if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { /* read Capabilities A Register DMFC bits */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); reg32 &= 0x7;
switch (reg32) { @@ -533,7 +533,7 @@ } } else { /* read Capabilities B Register DMFC bits */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); reg32 = (reg32 >> 4) & 0x7;
switch (reg32) { @@ -573,7 +573,7 @@ const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg = NULL;
- dev = pcidev_path_on_root(HOST_BRIDGE); + dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); if (dev) cfg = dev->chip_info;
@@ -643,97 +643,97 @@ printk(BIOS_DEBUG, "Update PCI-E configuration space:\n");
// TOM (top of memory) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM); + reg = pci_read_config32(HOST_BRIDGE, TOM); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOM, reg); + pci_write_config32(HOST_BRIDGE, TOM, reg);
- reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM + 4); + reg = pci_read_config32(HOST_BRIDGE, TOM + 4); val = tom & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOM + 4, reg); + pci_write_config32(HOST_BRIDGE, TOM + 4, reg);
// TOLUD (top of low used dram) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOLUD); + reg = pci_read_config32(HOST_BRIDGE, TOLUD); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOLUD, reg); + pci_write_config32(HOST_BRIDGE, TOLUD, reg);
// TOUUD LSB (top of upper usable dram) - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD); + reg = pci_read_config32(HOST_BRIDGE, TOUUD); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOUUD, reg); + pci_write_config32(HOST_BRIDGE, TOUUD, reg);
// TOUUD MSB - reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD + 4); + reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TOUUD + 4, reg); + pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg);
if (reclaim) { // REMAP BASE - pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE, remapbase << 20); - pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE + 4, remapbase >> 12); + pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); + pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12);
// REMAP LIMIT - pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT, remaplimit << 20); - pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT + 4, remaplimit >> 12); + pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); + pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); } // TSEG - reg = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB); + reg = pci_read_config32(HOST_BRIDGE, TSEGMB); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); - pci_write_config32(PCI_DEV(0, 0, 0), TSEGMB, reg); + pci_write_config32(HOST_BRIDGE, TSEGMB, reg);
// GFX stolen memory - reg = pci_read_config32(PCI_DEV(0, 0, 0), BDSM); + reg = pci_read_config32(HOST_BRIDGE, BDSM); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), BDSM, reg); + pci_write_config32(HOST_BRIDGE, BDSM, reg);
// GTT stolen memory - reg = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); + reg = pci_read_config32(HOST_BRIDGE, BGSM); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); - pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg); + pci_write_config32(HOST_BRIDGE, BGSM, reg);
if (me_uma_size) { - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4); + reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4, reg); + pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg);
// ME base - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE); + reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE, reg); + pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg);
- reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4); + reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4, reg); + pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg);
// ME mask - reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); + reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = reg | ME_STLEN_EN; // set ME memory enable reg = reg | MELCK; // set lockbit on ME mem printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); + pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); } }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38338 )
Change subject: nb/intel/sandybridge: Repurpose HOST_BRIDGE macro ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : No test failed. EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : No test failed. EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : No test failed.
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Nico Huber (Code Review)