coreboot-gerrit January 2020

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Change in coreboot[master]: nb/intel/sandybridge: drop LyCx(r, x, y) macro
by Felix Held (Code Review) 15 Jan '20

15 Jan '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38402 ) Change subject: nb/intel/sandybridge: drop LyCx(r, x, y) macro ...................................................................... nb/intel/sandybridge: drop LyCx(r, x, y) macro LyCx(r, x, y) was a duplicate of the CxLy(r, x, y) with different order of computation, so that the big refactoring doesn't change the output binary of a timeless build. Now this woraround can be dropped. Tested on lenovo/x230: still boots Change-Id: I251b4dd383f954b27f392190092e06a9a06668e2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38402/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d2f76e0..f12feaa 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -131,10 +131,7 @@ #define Gz(r, z) ((r) + ((z) * 0x100)) #define Ly(r, y) ((r) + ((y) * 4)) #define Cx(r, x) ((r) + ((x) * 0x400)) - -/* FIXME: These two are equivalent, but had to be split for reproducibility reasons. */ #define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4)) -#define LyCx(r, x, y) ((r) + ((y) * 4) + ((x) * 0x400)) /* Register definitions */ #define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ @@ -196,11 +193,11 @@ #define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ /* IOSAV sub-sequence control registers */ -#define IOSAV_n_SP_CMD_ADDR_ch(ch, y) LyCx(0x4200, ch, y) /* Special command address. */ -#define IOSAV_n_ADDR_UPD_ch(ch, y) LyCx(0x4210, ch, y) /* Address update control */ -#define IOSAV_n_SP_CMD_CTL_ch(ch, y) LyCx(0x4220, ch, y) /* Control of command signals */ -#define IOSAV_n_SUBSEQ_CTL_ch(ch, y) LyCx(0x4230, ch, y) /* Sub-sequence controls */ -#define IOSAV_n_ADDRESS_LFSR_ch(ch, y) LyCx(0x4240, ch, y) /* 23-bit LFSR state value */ +#define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ +#define IOSAV_n_ADDR_UPD_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ +#define IOSAV_n_SP_CMD_CTL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ +#define IOSAV_n_SUBSEQ_CTL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ +#define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ #define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ #define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I251b4dd383f954b27f392190092e06a9a06668e2 Gerrit-Change-Number: 38402 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/slippy: update VBT
by Matt DeVillier (Code Review) 15 Jan '20

15 Jan '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38397 ) Change subject: mb/google/slippy: update VBT ...................................................................... mb/google/slippy: update VBT The current BIOS-extracted VBT breaks backlight control with Tianocore, so replace it with one that does. Settings were exported using Intel BMP tool and the overlayed onto a GOP-format (vs BIOS format) VBT file. Test: boot google/wolf with both SeaBIOS and Tianocore payloads, verify backlight control functional under both Linux and Windows. Change-Id: Id6281c8dfb6e0001be8c4d9be1013f2d4bbb5880 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/slippy/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/38397/1 diff --git a/src/mainboard/google/slippy/data.vbt b/src/mainboard/google/slippy/data.vbt index e765e99..a7be44c 100644 --- a/src/mainboard/google/slippy/data.vbt +++ b/src/mainboard/google/slippy/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/38397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6281c8dfb6e0001be8c4d9be1013f2d4bbb5880 Gerrit-Change-Number: 38397 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Add support for Intel Sandybridge CPU (northbridge part)
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/854 ) Change subject: Add support for Intel Sandybridge CPU (northbridge part) ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/854/2/src/northbridge/intel/sandyb… File src/northbridge/intel/sandybridge/early_init.c: https://review.coreboot.org/c/coreboot/+/854/2/src/northbridge/intel/sandyb… PS2, Line 126: /* VLW */ Stefan, do you remember what this means? -- To view, visit https://review.coreboot.org/c/coreboot/+/854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Gerrit-Change-Number: 854 Gerrit-PatchSet: 2 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 12:56:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: /mb/google/hatch/variants/helios: Remove MAX98357A devicetree entry
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38398 ) Change subject: /mb/google/hatch/variants/helios: Remove MAX98357A devicetree entry ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/38398/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38398/1//COMMIT_MSG@10 PS1, Line 10: to indicate the same. … amplifier, so remove the devicetree entry. -- To view, visit https://review.coreboot.org/c/coreboot/+/38398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id02410553f018385d407086b2f9bc3ee1e7a5f40 Gerrit-Change-Number: 38398 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Jan 2020 12:51:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/systemagent: add Kconfig guard
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38013 ) Change subject: soc/intel/common/systemagent: add Kconfig guard ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/38013/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38013/2//COMMIT_MSG@15 PS2, Line 15: Missing Signed-off-by line. -- To view, visit https://review.coreboot.org/c/coreboot/+/38013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b9e18f6169d91732a1db7e8eabf137b66072dd Gerrit-Change-Number: 38013 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 12:50:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Furquan Shaikh (Code Review) 15 Jan '20

15 Jan '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 17: > Patch Set 17: > > > Patch Set 17: > > > > > Patch Set 17: > > > > > > Do you have an updated EDS where the updates you mentioned are captured? > > > > > > Also, I don't see the rest of the CLs uploaded here? Are those still WIP? > > > > Not Yet. Eds team is in the process of releasing the new one.For the next patch which have the chnages in the asl and gpio_soc_defs its WIP and I have one question: > > in the gpio.h file the chnage should be like this right? > > #define CROS_GPIO_DEVICE0_NAME "INT34C5:00" > > #define CROS_GPIO_DEVICE1_NAME "INT34C5:01" > > #define CROS_GPIO_DEVICE4_NAME "INT34C5:02" > > #define CROS_GPIO_DEVICE5_NAME "INT34C5:03" > > > > And in the mainboard for the cros_gpio we have to use the same? > > My board had some problem today. Was not able to test the changes. Fixed it finally. Will push the rest patches tomorrow. I think it would be better to name these CROS_GPIO_COMM0_NAME and so on. But the string looks fine i.e. INT34C5:xx -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 17 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 11:21:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]: add superio driver for sch5545
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20238 ) Change subject: [WIP]: add superio driver for sch5545 ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > The header information seems outdated. > > It doesnt build when configured into the Optiplex 790 because of unknown type names. > > Update: > the include of <device/pnp_ops.h> is missing in either pnp.h or the sch5545_early_init.h, I dont know where it would be better to be added in. Felix, any preference/suggestion where to add that? -- To view, visit https://review.coreboot.org/c/coreboot/+/20238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic258630b02e6ae86b1ee7ce663d9d026bf1c04e9 Gerrit-Change-Number: 20238 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Stuge <peter(a)stuge.se> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Comment-Date: Wed, 15 Jan 2020 11:17:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by Paul Menzel (Code Review) 15 Jan '20

15 Jan '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 59: Code-Review+1 As it’s able to start a payload and boot a GNU/Linux operating system, it’d be great if this could be added to the tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 59 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Wed, 15 Jan 2020 11:10:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Shaunak Saha (Code Review) 15 Jan '20

15 Jan '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 17: > Patch Set 17: > > > Patch Set 17: > > > > Do you have an updated EDS where the updates you mentioned are captured? > > > > Also, I don't see the rest of the CLs uploaded here? Are those still WIP? > > Not Yet. Eds team is in the process of releasing the new one.For the next patch which have the chnages in the asl and gpio_soc_defs its WIP and I have one question: > in the gpio.h file the chnage should be like this right? > #define CROS_GPIO_DEVICE0_NAME "INT34C5:00" > #define CROS_GPIO_DEVICE1_NAME "INT34C5:01" > #define CROS_GPIO_DEVICE4_NAME "INT34C5:02" > #define CROS_GPIO_DEVICE5_NAME "INT34C5:03" > > And in the mainboard for the cros_gpio we have to use the same? My board had some problem today. Was not able to test the changes. Fixed it finally. Will push the rest patches tomorrow. -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 17 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 08:07:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Shaunak Saha (Code Review) 15 Jan '20

15 Jan '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 17: (3 comments) https://review.coreboot.org/c/coreboot/+/37427/17//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37427/17//COMMIT_MSG@13 PS17, Line 13: .G > nit - space needed Ack https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… PS17, Line 4: 2019 > 2020 Ack https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/37427/17/src/soc/intel/tigerlake/i… PS17, Line 4: 2019 > 2020 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 17 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 Jan 2020 08:06:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2020