Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38439 )
Change subject: [WIP]soc/intel/tigerlake: Add asl support for USBC
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Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38439/2/src/soc/intel/tigerlake/ac…
File src/soc/intel/tigerlake/acpi/usbc.asl:
PS2:
Did you write all the code from scratch?
https://review.coreboot.org/c/coreboot/+/38439/2/src/soc/intel/tigerlake/ac…
PS2, Line 23: // Replaces \_SB.PCI0.IPC1
Use tabs.
https://review.coreboot.org/c/coreboot/+/38439/2/src/soc/intel/tigerlake/ac…
PS2, Line 192:
Remove blank lines at end of file.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 )
Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC
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Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37867/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/37867/2//COMMIT_MSG@8
PS2, Line 8:
Please add more details, what the problem and the solution is.
https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec_…
File src/ec/google/chromeec/ec_commands.h:
https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec_…
PS2, Line 4993: } __ec_align1;
Why can’t this struct not be extended?
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38437 )
Change subject: nb/intel/sandybridge: sort LANEBASE_* defines by their address
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nb/intel/sandybridge: sort LANEBASE_* defines by their address
Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/northbridge/intel/sandybridge/sandybridge.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38437/1
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index ef1df06..f5c1e41 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -139,11 +139,11 @@
#define LANEBASE_B1 0x0200
#define LANEBASE_B2 0x0400
#define LANEBASE_B3 0x0600
+#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */
#define LANEBASE_B4 0x1000
#define LANEBASE_B5 0x1200
#define LANEBASE_B6 0x1400
#define LANEBASE_B7 0x1600
-#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */
/* byte lane register offsets */
#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */
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