Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38298 )
Change subject: intel/sandybridge,bd82x6x: Move enable_smbus() call ......................................................................
intel/sandybridge,bd82x6x: Move enable_smbus() call
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_pch.c 2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38298/1
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 079e1b1..7d1c019 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -82,9 +82,6 @@
mainboard_early_init(s3resume);
- /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - post_code(0x39);
perform_raminit(s3resume); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index b19216b..6f06a57 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -327,4 +327,7 @@ pch_enable_gbe();
setup_pch_gpios(&mainboard_gpio_map); + + if (ENV_ROMSTAGE) + enable_smbus(); }
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38298 )
Change subject: intel/sandybridge,bd82x6x: Move enable_smbus() call ......................................................................
Patch Set 1: Code-Review+2
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38298
to look at the new patch set (#2).
Change subject: intel/sandybridge,bd82x6x: Move enable_smbus() call ......................................................................
intel/sandybridge,bd82x6x: Move enable_smbus() call
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_pch.c 2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38298/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38298 )
Change subject: intel/sandybridge,bd82x6x: Move enable_smbus() call ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38298 )
Change subject: intel/sandybridge,bd82x6x: Move enable_smbus() call ......................................................................
intel/sandybridge,bd82x6x: Move enable_smbus() call
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38298 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_pch.c 2 files changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 079e1b1..7d1c019 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -82,9 +82,6 @@
mainboard_early_init(s3resume);
- /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - post_code(0x39);
perform_raminit(s3resume); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index b19216b..6f06a57 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -327,4 +327,7 @@ pch_enable_gbe();
setup_pch_gpios(&mainboard_gpio_map); + + if (ENV_ROMSTAGE) + enable_smbus(); }
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Kyösti Mälkki (Code Review)
-
Patrick Georgi (Code Review)