Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38225
to look at the new patch set (#5).
Change subject: doc/tutorial/part1.md: Add information for yum- & pacman-based distro
......................................................................
doc/tutorial/part1.md: Add information for yum- & pacman-based distro
* Additional information on non-debian cli tools
* Improve Spellings and descriptions to the best of my knowledge
Adding info about needed tools in other distribution's package
managers was requested at the coreboot beginner's workshop at 36C3.
Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237
Signed-off-by: Patrik Tesarik <mail(a)patrik-tesarik.de>
---
D 3rdparty/amd_blobs
M Documentation/tutorial/part1.md
2 files changed, 22 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38225/5
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237
Gerrit-Change-Number: 38225
Gerrit-PatchSet: 5
Gerrit-Owner: Patrik Tesarik
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
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awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36192 )
Change subject: vc/amd/agesa/f16kb: Fix out of bounds read
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vc/amd/agesa/f16kb: Fix out of bounds read
ByteLane is incorrectly used unitialized from prior for statement.
Found nothing in following code that attempted to reference
PassTestRxEnDly at that index, so appears safe to delete.
Additionally, found nothing following with the
OutOfRange[ByteLane]==TRUE condition that would expect
'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];'.
Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Signed-off-by: Joe Moore <awokd(a)danwin1210.me>
Found-by: Coverity CID 1241804
---
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36192/1
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
index ce295ac..caf8f51 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -314,7 +314,6 @@
//
IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Setting PassTestRxEnDly\n");
IDS_HDT_CONSOLE (MEM_FLOW, "\t PassTestRxEnDly: ");
- PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];
for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
if (RxEnDlyTargetFound[ByteLane] == FALSE) {
// Calculate "PassTestRxEnDly" from current "RxEnDly"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Gerrit-Change-Number: 36192
Gerrit-PatchSet: 1
Gerrit-Owner: awokd(a)danwin1210.me
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