Change in coreboot[master]: sb/intel/common: Declare common smbus_base() and enable_smbus()
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38232 )
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/northbridge/intel/gm45/raminit.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 20 files changed, 84 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/1
diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 2a02fb7..def6bbb 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -15,6 +15,7 @@ #define __DEVICE_SMBUS_HOST_H__
#include <stdint.h> +#include <console/console.h>
/* Low-level SMBUS host controller. */
@@ -34,7 +35,17 @@
/* Upstream API */
+uintptr_t smbus_base(void); +int smbus_enable_iobar(uintptr_t base); void smbus_host_reset(uintptr_t base); void smbus_set_slave_addr(uintptr_t base, u8 slave_address);
+static inline void enable_smbus(void) +{ + uintptr_t base = smbus_base(); + smbus_enable_iobar(base); + smbus_host_reset(base); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); +} + #endif diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b1da177..5de87cf 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -21,6 +21,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/device.h> +#include <device/smbus_host.h> #include <spd.h> #include <console/console.h> #include <lib.h> diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 62f8e42..8a6cdd4 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <mrc_cache.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -32,13 +33,18 @@ #include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h>
-static void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_BASE_ADDRESS; +} + +int smbus_enable_iobar(uintptr_t base) { uint32_t reg; const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
/* SMBus I/O BAR */ - reg = SMBUS_BASE_ADDRESS | 2; + reg = base | 2; pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); /* Enable decode of I/O space. */ reg = pci_read_config16(smbus_dev, PCI_COMMAND); diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 4631652..114de95 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -42,6 +42,5 @@ void pch_uart_init(void); void intel_early_me_status(void);
-void enable_smbus(void);
#endif diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 5ecce28..3467720 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "pch.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev;
@@ -34,7 +39,7 @@
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +47,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 5f353af..5348478 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -62,7 +62,6 @@ int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-void enable_smbus(void); void enable_usb_bar(void);
#if ENV_ROMSTAGE diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 917a3b4..78e4ecf 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -23,7 +23,12 @@ #include <device/smbus_host.h> #include "i82371eb.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; u8 reg8; @@ -34,7 +39,7 @@ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the SMBus I/O base. */ - pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); + pci_write_config32(dev, SMBBA, base | 1);
/* Enable the SMBus controller host interface. */ reg8 = pci_read_config8(dev, SMBHSTCFG); @@ -46,9 +51,7 @@ reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; }
int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 55242ef..ea7efef 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,7 +19,6 @@
#if !defined(__ACPI__)
-void enable_smbus(void); void enable_pm(void);
#if ENV_ROMSTAGE diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 77b0aa0..163e8d2 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -16,25 +16,27 @@
#include <device/pci_ops.h> #include <device/pci_def.h> -#include <console/console.h> #include <device/smbus_host.h>
#include "i82801dx.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* set smbus iobase */ - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config32(dev, 0x20, base | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 50122d8..9895de1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -35,7 +35,6 @@ #include "chip.h"
void i82801dx_enable(struct device *dev); -void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void);
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 60fcceb..fdc98ab 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "i82801gx.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev;
@@ -33,7 +38,7 @@
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -41,9 +46,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 0516a7a..688f1c3 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -37,7 +37,6 @@ #include <device/device.h> void i82801gx_enable(struct device *dev);
-void enable_smbus(void); void i82801gx_lpc_setup(void); void i82801gx_setup_bars(void); void i82801gx_early_init(void); diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 4286760..678c653 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -22,7 +22,12 @@ #include <device/smbus_host.h> #include "i82801ix.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev;
@@ -35,7 +40,7 @@
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -43,9 +48,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 906d24e..f60aad3 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -208,7 +208,6 @@
void aseg_smm_lock(void);
-void enable_smbus(void); void i82801ix_early_init(void); void i82801ix_lpc_decode(void); void i82801ix_dmi_setup(void); diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 594400f..de48038 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -21,7 +21,12 @@ #include <device/smbus_host.h> #include "i82801jx.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev;
@@ -30,7 +35,7 @@
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -38,9 +43,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 26a99f4..abf6187 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -226,7 +226,6 @@ #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
#if ENV_ROMSTAGE -void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index fdf0c32..4aefb0b 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "pch.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev;
@@ -34,7 +39,7 @@
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +47,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 529b7a2..424bf42 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -52,7 +52,6 @@ #define DEBUG_PERIODIC_SMIS 0
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void enable_smbus(void); void enable_usb_bar(void);
#if ENV_ROMSTAGE diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 5ecce28..3467720 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -20,7 +20,12 @@ #include <device/smbus_host.h> #include "pch.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev;
@@ -34,7 +39,7 @@
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +47,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 71f42ea..9622c67 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -174,7 +174,6 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
-void enable_smbus(void);
#if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address);
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38232
to look at the new patch set (#2).
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/smbus.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 31 files changed, 103 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/2
Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38232
to look at the new patch set (#3).
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/smbus.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 33 files changed, 116 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/3
Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38232
to look at the new patch set (#4).
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/smbus.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 33 files changed, 118 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38232 )
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38232/4/src/soc/intel/baytrail/roms... File src/soc/intel/baytrail/romstage/raminit.c:
https://review.coreboot.org/c/coreboot/+/38232/4/src/soc/intel/baytrail/roms... PS4, Line 61: trailing whitespace
Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38232
to look at the new patch set (#5).
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/nehalem/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/smbus.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 33 files changed, 118 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38232 )
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
Patch Set 6: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38232 )
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38232/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38232/6//COMMIT_MSG@7 PS6, Line 7: smbus_base Is there any case in which smbus_base() does not return a constant? If so, I think it would be good to call enable_smbus() with the corresponding base address, and save it inside a static variable.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38232 )
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38232/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38232/6//COMMIT_MSG@7 PS6, Line 7: smbus_base
Is there any case in which smbus_base() does not return a constant? If so, I think it would be good […]
Read comment below. Call-sites of enable_smbus() will then need to include sb/soc specific headers. There is still lots more to tidy.
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38232
to look at the new patch set (#7).
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/smbus.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 27 files changed, 112 insertions(+), 86 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/7
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38232
to look at the new patch set (#8).
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/smbus.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 27 files changed, 111 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38232/8
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38232 )
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
Patch Set 9: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38232/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38232/6//COMMIT_MSG@7 PS6, Line 7: smbus_base
Read comment below. Call-sites of enable_smbus() will then need to include sb/soc specific headers. […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38232 )
Change subject: sb/intel/common: Declare common smbus_base() and enable_smbus() ......................................................................
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/include/device/smbus_host.h M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/smbus.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 27 files changed, 111 insertions(+), 85 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index cb31d02..c12718d 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -15,6 +15,7 @@ #define __DEVICE_SMBUS_HOST_H__
#include <stdint.h> +#include <console/console.h>
/* Low-level SMBUS host controller. */
@@ -34,7 +35,20 @@
/* Upstream API */
+uintptr_t smbus_base(void); +int smbus_enable_iobar(uintptr_t base); void smbus_host_reset(uintptr_t base); void smbus_set_slave_addr(uintptr_t base, u8 slave_address);
+static inline void enable_smbus(void) +{ + uintptr_t base = smbus_base(); + + if (smbus_enable_iobar(base) < 0) + die("SMBus controller not found!"); + + smbus_host_reset(base); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); +} + #endif diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 62f8e42..c21a0c4 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <mrc_cache.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -32,13 +33,18 @@ #include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h>
-static void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_BASE_ADDRESS; +} + +int smbus_enable_iobar(uintptr_t base) { uint32_t reg; const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
/* SMBus I/O BAR */ - reg = SMBUS_BASE_ADDRESS | 2; + reg = base | 2; pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); /* Enable decode of I/O space. */ reg = pci_read_config16(smbus_dev, PCI_COMMAND); @@ -52,6 +58,8 @@ /* Configure pads to be used for SMBus */ score_select_func(PCU_SMB_CLK_PAD, 1); score_select_func(PCU_SMB_DATA_PAD, 1); + + return 0; }
static void ABI_X86 send_to_console(unsigned char b) diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 4631652..b32b043 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -42,6 +42,4 @@ void pch_uart_init(void); void intel_early_me_status(void);
-void enable_smbus(void); - #endif diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index af8ea53..e8f4eb8 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <reg_script.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c index dd5d030..4b08b4c 100644 --- a/src/soc/intel/broadwell/romstage/smbus.c +++ b/src/soc/intel/broadwell/romstage/smbus.c @@ -15,6 +15,7 @@ */
#include <device/pci_def.h> +#include <device/smbus_host.h> #include <reg_script.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -36,7 +37,13 @@ REG_SCRIPT_END, };
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_BASE_ADDRESS; +} + +int smbus_enable_iobar(uintptr_t base) { reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); + return 0; } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6f06a57..2213878 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -18,6 +18,7 @@ #include <cf9_reset.h> #include <ip_checksum.h> #include <device/pci_def.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 5ecce28..91f1bc3 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -15,26 +15,27 @@ */
#include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "pch.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +}
+int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } + if (pci_read_config16(dev, 0x0) != 0x8086) + return -1;
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +43,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 5f353af..5348478 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -62,7 +62,6 @@ int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-void enable_smbus(void); void enable_usb_bar(void);
#if ENV_ROMSTAGE diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index f69cb93..671bfc5 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -15,7 +15,6 @@ */
#include <stdint.h> -#include <console/console.h> #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -29,7 +28,12 @@ enable_pm(); }
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev; u8 reg8; @@ -40,7 +44,7 @@ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the SMBus I/O base. */ - pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); + pci_write_config32(dev, SMBBA, base | 1);
/* Enable the SMBus controller host interface. */ reg8 = pci_read_config8(dev, SMBHSTCFG); @@ -52,9 +56,7 @@ reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; }
int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index b292beb..2b53010 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,7 +19,6 @@
#if !defined(__ACPI__)
-void enable_smbus(void); void enable_pm(void); void i82371eb_early_init(void);
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index de0bc93..5ab7f8d 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -16,9 +16,7 @@
#include <device/pci_ops.h> #include <device/pci_def.h> -#include <console/console.h> #include <device/smbus_host.h> - #include "i82801dx.h"
void i82801dx_early_init(void) @@ -26,20 +24,23 @@ enable_smbus(); }
-void enable_smbus(void) +uintptr_t smbus_base(void) +{ + return SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* set smbus iobase */ - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config32(dev, 0x20, base | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 8717e59..18db9e9 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -36,7 +36,6 @@
void i82801dx_enable(struct device *dev); void i82801dx_early_init(void); -void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void);
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 29c4550..a627cc1 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -14,6 +14,7 @@ #include <stdint.h> #include <console/console.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include "i82801gx.h" diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 60fcceb..b89e57d 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -15,25 +15,27 @@ */
#include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "i82801gx.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +}
+int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */ if (pci_read_config16(dev, 0x2) != 0x27da) - die("SMBus controller not found!"); + return -1;
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -41,9 +43,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 0516a7a..688f1c3 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -37,7 +37,6 @@ #include <device/device.h> void i82801gx_enable(struct device *dev);
-void enable_smbus(void); void i82801gx_lpc_setup(void); void i82801gx_setup_bars(void); void i82801gx_early_init(void); diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 4ce4fbe..9c1e6c0 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -16,6 +16,7 @@
#include <arch/io.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include "i82801ix.h" #include "chip.h"
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 4286760..60f49d2 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -16,26 +16,28 @@ */
#include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/smbus_host.h> #include "i82801ix.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +}
+int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */ if (pci_read_config16(dev, 0x2) != PCI_DEVICE_ID_INTEL_82801IB_SMB) - die("SMBus controller not found!"); + return -1;
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -43,9 +45,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 906d24e..f60aad3 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -208,7 +208,6 @@
void aseg_smm_lock(void);
-void enable_smbus(void); void i82801ix_early_init(void); void i82801ix_lpc_decode(void); void i82801ix_dmi_setup(void); diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 87831bb..c10c421 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -14,6 +14,7 @@
#include <console/console.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include "i82801jx.h" diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 594400f..8e3329c 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -16,21 +16,23 @@ */
#include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "i82801jx.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +}
+int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -38,9 +40,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2c5135e..abf6187 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -225,7 +225,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
-void enable_smbus(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index e462dd8..56331cc 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -18,6 +18,7 @@
#include <stdint.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index fdf0c32..52d483d 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -15,26 +15,27 @@ */
#include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "pch.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +}
+int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } + if (pci_read_config16(dev, 0x0) != 0x8086) + return -1;
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +43,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 529b7a2..424bf42 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -52,7 +52,6 @@ #define DEBUG_PERIODIC_SMIS 0
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void enable_smbus(void); void enable_usb_bar(void);
#if ENV_ROMSTAGE diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 25ffdc4..e0e4613 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -19,6 +19,7 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> +#include <device/smbus_host.h> #include <southbridge/intel/common/pmclib.h> #include <elog.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 5ecce28..91f1bc3 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -15,26 +15,27 @@ */
#include <device/pci_ops.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/smbus_host.h> #include "pch.h"
-void enable_smbus(void) +uintptr_t smbus_base(void) { - pci_devfn_t dev; + return SMBUS_IO_BASE; +}
+int smbus_enable_iobar(uintptr_t base) +{ /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } + if (pci_read_config16(dev, 0x0) != 0x8086) + return -1;
/* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -42,9 +43,7 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE); - - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); + return 0; }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 71f42ea..9622c67 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -174,7 +174,6 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
-void enable_smbus(void);
#if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address);
-
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