coreboot-gerrit July 2019

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 03 Jul '19

03 Jul '19

Hello Patrick Rudolph, Aaron Durbin, dhaval v sharma, Subrata Banik, Patrick Rudolph, Paul Menzel, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27369 to look at the new patch set (#40). Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If so, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config TOP_SWAP_BASED_VBOOT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sue that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 4 files changed, 257 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 40 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode up...
by Rizwan Qureshi (Code Review) 03 Jul '19

03 Jul '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33939 Change subject: mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode update ...................................................................... mb/google/hatch:[TESTONLY] Add FMAP regions required for microcode update Add a region RW_UCODE_STAGED, which will hold the rw microcode which inturn will be referenced by the FIT in top swap bootblock Add a region RW_UPDATE_STATE, to hold the firmware update state Change-Id: Ia44eb00123c0b8c0fcb9a2c540e5bc3660cfa38f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/chromeos.fmd 1 file changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33939/1 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 393ac80..1a5f204 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -8,28 +8,29 @@ # of BIOS regions start at 16MiB boundary. Since this is a 32MiB # SPI flash only the top 16MiB actually gets memory mapped. RW_LEGACY(CBFS)@0x0 0x1000000 - RW_SECTION_A@0x1000000 0x3e0000 { + RW_SECTION_A@0x1000000 0x3b0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x39ffc0 + RW_FWID_A@0x3affc0 0x40 } - RW_SECTION_B@0x13e0000 0x3e0000 { + RW_SECTION_B@0x13b0000 0x3b0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x39ffc0 + RW_FWID_B@0x3affc0 0x40 } - RW_MISC@0x17c0000 0x40000 { - UNIFIED_MRC_CACHE@0x0 0x30000 { + RW_MISC@0x1760000 0xa0000 { + RW_UCODE_STAGED(PRESERVE)@0x0 0x60000 + UNIFIED_MRC_CACHE@0x60000 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x4000 - RW_SHARED@0x34000 0x4000 { + RW_ELOG(PRESERVE)@0x90000 0x4000 + RW_SHARED@0x94000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_VPD(PRESERVE)@0x98000 0x2000 + RW_NVRAM(PRESERVE)@0x9a000 0x6000 } # Make WP_RO region align with SPI vendor # memory protected range specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/33939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia44eb00123c0b8c0fcb9a2c540e5bc3660cfa38f Gerrit-Change-Number: 33939 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Use 3rdparty/intel-microcode
by Arthur Heymans (Code Review) 03 Jul '19

03 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33554 Change subject: Use 3rdparty/intel-microcode ...................................................................... Use 3rdparty/intel-microcode Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel. Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products. Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_65x/Makefile.inc M src/cpu/intel/model_67x/Makefile.inc M src/cpu/intel/model_68x/Makefile.inc M src/cpu/intel/model_6bx/Makefile.inc M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/skylake/Makefile.inc 19 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33554/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index f83d5db..b0ca79f 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -39,5 +39,5 @@ subdirs-y += ../turbo subdirs-y += ../common -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 451df6e..caeab56 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -4,4 +4,4 @@ subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index eec544d..a1f2d0d 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -4,4 +4,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*) diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 39246c0..f494e9b 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -23,7 +23,7 @@ ramstage-y += stage_cache.c postcar-y += stage_cache.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e1fa879..78a6283 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -28,8 +28,8 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc index 05ea68e..c1f471c 100644 --- a/src/cpu/intel/model_65x/Makefile.inc +++ b/src/cpu/intel/model_65x/Makefile.inc @@ -16,4 +16,4 @@ ramstage-y += model_65x_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*) diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc index 219a0d2..ef68df4 100644 --- a/src/cpu/intel/model_67x/Makefile.inc +++ b/src/cpu/intel/model_67x/Makefile.inc @@ -16,4 +16,4 @@ ramstage-y += model_67x_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*) diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc index 7e09dc6..95aacb3 100644 --- a/src/cpu/intel/model_68x/Makefile.inc +++ b/src/cpu/intel/model_68x/Makefile.inc @@ -17,4 +17,4 @@ ramstage-y += model_68x_init.c subdirs-y += ../../x86/name -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*) diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc index 81e64e3..84f4ff0 100644 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ b/src/cpu/intel/model_6bx/Makefile.inc @@ -1,4 +1,4 @@ ramstage-y += model_6bx_init.c subdirs-y += ../../x86/name -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*) diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 46ae7c7..cef2b0b 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -4,4 +4,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-y += ../model_1067x/mp_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*) diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index 9564bf9..9121e3b 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -4,4 +4,4 @@ ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index 3ac510f..b2f87ab 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1,3 +1,3 @@ ramstage-y += model_6xx_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_66x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-06-*) diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 589e49e..9bb5dca 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,3 +1,3 @@ ramstage-y += model_f2x_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 19b2e93..ed1eb5f 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -2,4 +2,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 6fbc9ae..196d63e 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -2,4 +2,4 @@ subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1fd1603..4fc16d5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -177,10 +177,10 @@ ifeq ($(CONFIG_SOC_INTEL_GLK),y) # Gemini Lake B0 (706a1) only atm. -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_706ax/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*) else # Apollo Lake 506c2, B0 (506c9) and E0 (506ca) only atm. -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506cx/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*) endif endif # if CONFIG_SOC_INTEL_APOLLOLAKE diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 1328944..239004b 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -91,9 +91,9 @@ endif # Coffeelake U43e D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-86-*) # Coffeelake H/S/E3 B0 U0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-96-*) CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 0a23170..e8a3189 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -39,6 +39,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_5066x/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-56-*) endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index e9f555f..9237188 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -83,13 +83,13 @@ # Skylake D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-4e-*) # Skylake H Q0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5e-*) # Kabylake H0, Y0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-8e-*) # Kabylake HB0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-9e-*) # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples. -- To view, visit https://review.coreboot.org/c/coreboot/+/33554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Gerrit-Change-Number: 33554 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Add Kabylake-R microcode update files
by Arthur Heymans (Code Review) 03 Jul '19

03 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34000 Change subject: soc/intel/skylake: Add Kabylake-R microcode update files ...................................................................... soc/intel/skylake: Add Kabylake-R microcode update files Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/skylake/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34000/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 25dce05..5e4b111 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -91,6 +91,8 @@ cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03 # Kabylake H0, Y0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09 +# Kabylake-R +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a endif # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples. -- To view, visit https://review.coreboot.org/c/coreboot/+/34000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8 Gerrit-Change-Number: 34000 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Frank Chu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Abandoned CL:33820 already fix touch pad issue -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 5: (1 comment) > Patch Set 5: > > (1 comment) > > > Patch Set 3: > > > > (1 comment) https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/gpio.c: https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… PS3, Line 37: PAD_CFG_GPI_APIC(GPP_A21, NONE, DEEP, LEVEL, NONE), > I have a try, follow hatch sol to PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), touch p […] sorry, type wrong PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT), -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jul 2019 06:45:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Comment-In-Reply-To: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 5: (1 comment) > Patch Set 3: > > (1 comment) https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/gpio.c: https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… PS3, Line 37: PAD_CFG_GPI_APIC(GPP_A21, NONE, DEEP, LEVEL, NONE), > Ah, I missed that this change was still pending: https://review.coreboot.org/c/coreboot/+/33820/5 […] I have a try, follow hatch sol to PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), touch pad still work, I will abort this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jul 2019 06:39:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 5: (1 comment) > Patch Set 3: > > (2 comments) I have a try that restore change PM config, touch pad still work https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/overridetree.cb: https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… PS3, Line 2: # GPIO community PM configuration : register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_2]" = "0" : register "gpio_pm[COMM_3]" = "0" > Did you try without this change to see if touchpad works? i have a try, if restore this change, touch pad still work -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jul 2019 06:26:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus: Override DDI1 DDC SDA/SCL for Garg HDMI
by Kevin Chiu (Code Review) 03 Jul '19

03 Jul '19

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33552 to review the following change. Change subject: mb/google/octopus: Override DDI1 DDC SDA/SCL for Garg HDMI ...................................................................... mb/google/octopus: Override DDI1 DDC SDA/SCL for Garg HDMI BUG=b:134912735 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I6ad8e5aa52f503121b10fe353e4bf4021aee2061 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/octopus/variants/garg/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33552/1 diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index a436240..8467846 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -22,6 +22,9 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_DDC_SCL */ + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), -- To view, visit https://review.coreboot.org/c/coreboot/+/33552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ad8e5aa52f503121b10fe353e4bf4021aee2061 Gerrit-Change-Number: 33552 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update SPD sources
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Hello Paul Fagerburg, Kane Chen, Philip Chen, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33953 to look at the new patch set (#3). Change subject: mb/google/hatch/variants/helios: Update SPD sources ...................................................................... mb/google/hatch/variants/helios: Update SPD sources Add SPD_SOURCES "empty_ddr4", "LP_8G_2133" and "LP_16G_2133" BUG=b:133455595 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 --- M src/mainboard/google/hatch/variants/helios/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33953/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2019