coreboot-gerrit July 2019

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Change in ...coreboot[master]: soc/amd/picasso: Add xhci1 and remove ehci
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33987 Change subject: soc/amd/picasso: Add xhci1 and remove ehci ...................................................................... soc/amd/picasso: Add xhci1 and remove ehci Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/usb.c 4 files changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33987/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 19921e1..dad9d22 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -96,8 +96,6 @@ return "PBR8"; case HDA1_DEVFN: return "AZHD"; - case EHCI1_DEVFN: - return "EHC0"; case LPC_DEVFN: return "LPCB"; case SATA_DEVFN: @@ -106,8 +104,10 @@ return "SDCN"; case SMBUS_DEVFN: return "SBUS"; - case XHCI_DEVFN: + case XHCI0_DEVFN: return "XHC0"; + case XHCI1_DEVFN: + return "XHC1"; default: return NULL; } diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 478a2cb..c823fdb 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -151,12 +151,19 @@ #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) -/* XHCI */ -#define XHCI_DEV 0x10 -#define XHCI_FUNC 0 -#define XHCI_DEVID 0x7914 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) -#define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) +/* USB 3.1 */ +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVID 0x15e0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) +#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) + +/* USB 3.1 */ +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVID 0x15e1 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) +#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) /* SATA */ #define SATA_DEV 0x11 @@ -167,13 +174,6 @@ #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) -/* EHCI */ -#define EHCI_DEV 0x12 -#define EHCI_FUNC 0 -#define EHCI_DEVID 0x7908 -#define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) -#define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a5892bb..4392e4f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -367,8 +367,8 @@ * over current support. */ #define USB_OC_DISABLE_ALL 0xffff -int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); -int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); +int mainboard_get_xhci0_oc_map(uint16_t *usb_oc_map); +int mainboard_get_xhci1_oc_map(uint16_t *usb_oc_map); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index ae6c476..66c8266 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -28,23 +28,24 @@ { uint16_t map = USB_OC_DISABLE_ALL; - if (dev->path.pci.devfn == XHCI_DEVFN) { - if (mainboard_get_xhci_oc_map(&map) == 0) + if (dev->path.pci.devfn == XHCI0_DEVFN) { + if (mainboard_get_xhci0_oc_map(&map) == 0) ; // TODO } - if (dev->path.pci.devfn == EHCI1_DEVFN) - if (mainboard_get_ehci_oc_map(&map) == 0) + if (dev->path.pci.devfn == XHCI1_DEVFN) { + if (mainboard_get_xhci1_oc_map(&map) == 0) ; // TODO + } } -int __weak mainboard_get_xhci_oc_map(uint16_t *map) +int __weak mainboard_get_xhci0_oc_map(uint16_t *map) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; } -int __weak mainboard_get_ehci_oc_map(uint16_t *map) +int __weak mainboard_get_xhci1_oc_map(uint16_t *map) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/33987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7 Gerrit-Change-Number: 33987 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: soc/amd/picasso: Remove most stoneyridge USB
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33752 Change subject: soc/amd/picasso: Remove most stoneyridge USB ...................................................................... soc/amd/picasso: Remove most stoneyridge USB Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove source that uses these. Remove USB devices from the AOAC registers. Remove the D0/D3 isupport from ASL, including all supporting xHCI firmware loading support. Remove xHCI firmware from amdfw.rom. Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/acpi/usb.asl M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/picasso/usb.c 10 files changed, 9 insertions(+), 475 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33752/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9317119..f692f95 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -151,27 +151,6 @@ hex default 0xfef00000 -config STONEYRIDGE_XHCI_ENABLE - bool "Enable Stoney Ridge XHCI Controller" - default y - help - The XHCI controller must be enabled and the XHCI firmware - must be added in order to have USB 3.0 support configured - by coreboot. The OS will be responsible for enabling the XHCI - controller if the XHCI firmware is available but the - XHCI controller is not enabled by coreboot. - -config STONEYRIDGE_XHCI_FWM - bool "Add xhci firmware" - default y - help - Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 - -config STONEYRIDGE_XHCI_FWM_FILE - string "XHCI firmware path and filename" - default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" - depends on STONEYRIDGE_XHCI_FWM - config AMD_PUBKEY_FILE string "AMD public Key" default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9aedbd1..dbb0e8e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -175,8 +175,6 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) - OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) @@ -196,8 +194,7 @@ OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ @@ -215,7 +212,6 @@ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_SMUFWM_FILE) \ diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index e780a64..cdb32cc 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -58,19 +58,10 @@ UT1E, 1, // UART1, 12 , 2, ST_E, 1, // SATA, 15 - , 2, - EHCE, 1, // EHCI, 18 - , 4, - XHCE, 1, // XCHI, 23 + , 8, SD_E, 1, // SD, 24 , 2, ESPI, 1, // ESPI, 27 - , 4, - FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM - FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM - FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM - FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM - EH10, 32, // 0x44 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 3623814..8cdb4d2 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -208,27 +208,6 @@ U2RP, 1, /* Usb2 Ref Clock Powerdown */ U3RP, 1, /* Usb3 Ref Clock Powerdown */ - /* XHCI_PM registers */ - offset (0x1c00), - , 1, - ,6, - U3PY, 1, - , 7, - UD3P, 1, /* bit 15 */ - U3PR, 1, /* bit 16 */ - , 11, - FWLM, 1, /* FirmWare Load Mode */ - FPLS, 1, /* Fw PreLoad Start */ - FPLC, 1, /* Fw PreLoad Complete */ - - offset (0x1c04), - UA04, 16, - , 15, - ROAM, 1, /* 1= ROM 0=RAM */ - - offset (0x1c08), - UA08, 32, - /* AOAC Registers */ offset (0x1e4a), /* I2C0 D3 Control */ I0TD, 2, @@ -442,8 +421,6 @@ } } /* todo Case(15) { STD0()} */ /* SATA */ - Case(18) { U2D0()} /* EHCI */ - Case(23) { U3D0()} /* XHCI */ Case(24) { /* SD */ Store(0x00, SDTD) Store(One, SDPD) @@ -505,8 +482,6 @@ Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ - Case(18) { U2D3()} /* EHCI */ - Case(23) { U3D3()} /* XHCI */ Case(24) { /* SD */ Store(Zero, SDPD) Store(SDDS, Local0) @@ -541,26 +516,10 @@ Method(FPTS,0, Serialized) /* FCH _PTS */ { - if(LEqual(\XHCE, one)) { - if(LNotEqual(U3TD, 0x03)) { - FDDC(23, 3) - } - } - if(LNotEqual(U2TD, 0x03)) { - FDDC(18, 3) - } } Method(FWAK,0, Serialized) /* FCH _WAK */ { - if(LEqual(\XHCE, one)) { - if(LEqual(U3TD, 0x03)) { - FDDC(23, 0) - } - } - if(LEqual(U2TD, 0x03)) { - FDDC(18, 0) - } if(LEqual(\UT0E, zero)) { if(LNotEqual(U0TD, 0x03)) { FDDC(11, 3) diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl index f2ee8f6..2af0c1a 100644 --- a/src/soc/amd/picasso/acpi/usb.asl +++ b/src/soc/amd/picasso/acpi/usb.asl @@ -30,9 +30,6 @@ Device (HS08) { Name (_ADR, 8) } } - Name(_PR0, Package() { P0U2 }) /* Indicate support for D0 */ - Name(_PR3, Package() { P3U2 }) /* Indicate support for D3cold */ - Method(_S0W,0) { Return(0) } @@ -55,9 +52,6 @@ Device (SS02) { Name (_ADR, 2) } Device (SS03) { Name (_ADR, 3) } - Name(_PR0, Package() { P0U3 }) /* Indicate support for D0 */ - Name(_PR3, Package() { P3U3 }) /* Indicate support for D3cold */ - Method(_S0W,0) { Return(0) } @@ -71,322 +65,3 @@ } } /* end XHC0 */ - -Scope(\_SB) -{ - Name(XHD0, 0) - Name(XHD3, 0) - PowerResource(P0U3, 0, 0) { - Method(_STA) { - Return(XHD0) - } - Method(_ON) { - Store(0x01, XHD0) - } - Method(_OFF) { - Store(0x00, XHD0) - } - } - PowerResource(P3U3, 0, 0) { - Method(_STA) { - Return(XHD3) - } - Method(_ON) { - Store(0x01, XHD3) - } - Method(_OFF) { - Store(0x00, XHD3) - } - } - - Name(EHD0, 0) - Name(EHD3, 0) - PowerResource(P0U2, 0, 0) { - Method(_STA) { - Return(EHD0) - } - Method(_ON) { - Store(0x01, EHD0) - } - Method(_OFF) { - Store(0x00, EHD0) - } - } - PowerResource(P3U2, 0, 0) { - Method(_STA) { - Return(EHD3) - } - Method(_ON) { - Store(0x01, EHD3) - } - Method(_OFF) { - Store(0x00, EHD3) - } - } -} - -OperationRegion(EHMC, SystemMemory, EH10, 0x100) -Field(EHMC, DwordAcc, NoLock, Preserve) -{ - Offset(0xb0), - , 5, - ESIM, 1, -} - -Method(U2D3,0, Serialized) -{ - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (ESIM, SSIM) - } - - if (LEqual(E_PS, 3)) { - Store (Zero, RQTY) - Store (One, RQ18) - - Store (U2SR, Local0) - while (Local0) { - Store (U2SR, Local0) - } - - Store (Zero, U2PD) - - Store (U2DS, Local0) - while (LNotEqual(Local0, Zero)) { - Store (U2DS, Local0) - } - - Store (0x03,U2TD) - - if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */ - PWGC (0x40, 0) - Store (One, U2RP) - } - } -} - -Method(U2D0,0, Serialized) -{ - PWGC (0x40, 1) - Store (Zero, U2RP) - Store (0x00,U2TD) - - Store (Zero, U2TD) - Store (One, U2PD) - - Store (U2DS, Local0) - while (LNotEqual(Local0,0x7)) { - Store (U2DS, Local0) - } - - Store (One, RQTY) - Store (One, RQ18) - Store (U2SR, Local0) - while (LNot(Local0)) { - Store (U2SR, Local0) - } - Store (EHID, EH2C) - - - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (SSIM, ESIM) - } - - Store (ES54, EH54) - Store (ES64, EH64) -} - -Method(LXFW,3, Serialized) //Load Xhci FirmWare -{ - Store (One, FWLM) /* Firmware Load Mode */ - Store (Arg0, ROAM) /* ROM/RAM */ - Store (Arg1, UA04) - Store (Arg2, UA08) - Store (One, FPLS) /* Firmware Preload Start */ - Store (FPLC, Local0) /* Firmware Preload Complete */ - while (LNot(Local0)) { - Store (FPLC, Local0) - } - Store (Zero, FPLS) -} - -Method(U3D3,0, Serialized) -{ - if (LEqual(U_PS, 3)) { - X0_S () - - Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */ - And (PGA3, 0x20, Local0) - while (LNot(Local0)) { /* wait for it to complete */ - And (PGA3, 0x20, Local0) - } - Store (One, UD3P) /* U3P_D3Cold_PWRDN */ - - Store (Zero, U3PD) /* PwrOnDev */ - Store (U3DS, Local0) - while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */ - Store (U3DS, Local0) - } - - Store (0x3, U3TD) /* TargetedDeviceState */ - - Store (One, U3RP) /* USB3_RefClk_Pwdn */ - - if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */ - And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */ - Store (One, U2RP) /* USB2_RefClk_Pwdn */ - } - Store (Zero, U3PG) /* XhcPwrGood */ - Store (One, U3PS) /* Usb3PowerSel */ - } -} - -Method(U3D0,0, Serialized) -{ - Store (Zero, U3PS) /* Usb3PowerSel */ - Store (One, U3PG) /* XhcPwrGood */ - - Store (Zero, U2RP) - Store (Zero, U3RP) - - And (PGA3, 0xdf, Local0) - Or (Local0, 0x40, Local0) - Store (Local0, PGA3) /* SwUsb2S5RstB */ - - Store (Zero, U3TD) /* TargetedDeviceState */ - Store (One, U3PD) /* PwrOnDev */ - - Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */ - while (LNot(Lequal(Local0, 0x7))) { - Store (U3DS, Local0) - } - - Store (U3PY, Local0) /* USB3 PHY Lock */ - while (LNot(Local0)) { - Store (U3PY, Local0) - } - - Store (Zero, U3PR) /* U3P_RESTORE_RESET */ - - Store (AUSS, Local0) /* AutoSizeStart */ - if (LNotEqual(Local0,1)) { - Store(One, AUSS) - } - Store (AUSS, Local0) - while (LNotEqual(Local0,1)) { - Store (AUSS, Local0) - } - - LXFW (1, FW00, FW01) - LXFW (0, FW02, FW03) - - X0_R () - - Store (One, U3PR) /* U3P_RESTORE_RESET */ - Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */ - Store (One, U3TD) /* TargetedDeviceState */ -} - -Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */ -CreateDWordField(SVBF, 0x000, S000) /* will be easier to add from there */ -CreateDWordField(SVBF, 0x004, S004) -CreateDWordField(SVBF, 0x008, S008) -CreateDWordField(SVBF, 0x00C, S00C) -CreateDWordField(SVBF, 0x018, S018) -CreateDWordField(SVBF, 0x01C, S01C) -CreateDWordField(SVBF, 0x020, S020) -CreateDWordField(SVBF, 0x030, S030) -CreateDWordField(SVBF, 0x118, S118) -CreateDWordField(SVBF, 0x158, S158) -CreateDWordField(SVBF, 0x198, S198) -CreateDWordField(SVBF, 0x1D8, S1D8) -CreateDWordField(SVBF, 0x300, S300) -CreateDWordField(SVBF, 0x304, S304) -CreateDWordField(SVBF, 0x308, S308) -CreateDWordField(SVBF, 0x30C, S30C) -CreateDWordField(SVBF, 0x310, S310) -CreateDWordField(SVBF, 0x428, S428) -CreateDWordField(SVBF, 0x438, S438) -CreateDWordField(SVBF, 0x43C, S43C) -CreateDWordField(SVBF, 0x458, S458) -CreateDWordField(SVBF, 0x468, S468) -CreateDWordField(SVBF, 0x46C, S46C) -CreateDWordField(SVBF, 0x470, S470) -CreateDWordField(SVBF, 0x480, S480) -CreateDWordField(SVBF, 0x484, S484) -CreateDWordField(SVBF, 0x488, S488) -CreateDWordField(SVBF, 0x48C, S48C) -CreateDWordField(SVBF, 0x730, EHID) /* EHCI SSID */ -CreateDWordField(SVBF, 0x734, XHID) /* XHCI SSID */ -CreateByteField(SVBF, 0x740, ES54) /* EHCI PCIx54 */ -CreateByteField(SVBF, 0x741, ES64) /* EHCI PCIx64 */ -CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */ - -Method(X0_S,0) -{ - Store (XH2C, XHID) - Store (0x00000000, IDEX) Store (DATA, S000) - Store (0x00000004, IDEX) Store (DATA, S004) - Store (0x00000008, IDEX) Store (DATA, S008) - Store (0x0000000c, IDEX) Store (DATA, S00C) - Store (0x00000018, IDEX) Store (DATA, S018) - Store (0x0000001c, IDEX) Store (DATA, S01C) - Store (0x00000020, IDEX) Store (DATA, S020) - Store (0x00000030, IDEX) Store (DATA, S030) - Store (0x00000118, IDEX) Store (DATA, S118) - Store (0x00000158, IDEX) Store (DATA, S158) - Store (0x00000198, IDEX) Store (DATA, S198) - Store (0x000001d8, IDEX) Store (DATA, S1D8) - Store (0x00000300, IDEX) Store (DATA, S300) - Store (0x00000304, IDEX) Store (DATA, S304) - Store (0x00000308, IDEX) Store (DATA, S308) - Store (0x0000030c, IDEX) Store (DATA, S30C) - Store (0x00000310, IDEX) Store (DATA, S310) - Store (0x40000028, IDEX) Store (DATA, S428) - Store (0x40000038, IDEX) Store (DATA, S438) - Store (0x4000003c, IDEX) Store (DATA, S43C) - Store (0x40000058, IDEX) Store (DATA, S458) - Store (0x40000068, IDEX) Store (DATA, S468) - Store (0x4000006c, IDEX) Store (DATA, S46C) - Store (0x40000070, IDEX) Store (DATA, S470) - Store (0x40000080, IDEX) Store (DATA, S480) - Store (0x40000084, IDEX) Store (DATA, S484) - Store (0x40000088, IDEX) Store (DATA, S488) - Store (0x4000008c, IDEX) Store (DATA, S48C) -} - -Method(X0_R,0) -{ - Store (XHID, XH2C) - Store (0x00000000, IDEX) Store (S000, DATA) - Store (0x00000004, IDEX) Store (S004, DATA) - Store (0x00000008, IDEX) Store (S008, DATA) - Store (0x0000000c, IDEX) Store (S00C, DATA) - Store (0x00000018, IDEX) Store (S018, DATA) - Store (0x0000001c, IDEX) Store (S01C, DATA) - Store (0x00000020, IDEX) Store (S020, DATA) - Store (0x00000030, IDEX) Store (S030, DATA) - Store (0x00000118, IDEX) Store (S118, DATA) - Store (0x00000158, IDEX) Store (S158, DATA) - Store (0x00000198, IDEX) Store (S198, DATA) - Store (0x000001d8, IDEX) Store (S1D8, DATA) - Store (0x00000300, IDEX) Store (S300, DATA) - Store (0x00000304, IDEX) Store (S304, DATA) - Store (0x00000308, IDEX) Store (S308, DATA) - Store (0x0000030c, IDEX) Store (S30C, DATA) - Store (0x00000310, IDEX) Store (S310, DATA) - Store (0x40000028, IDEX) Store (S428, DATA) - Store (0x40000038, IDEX) Store (S438, DATA) - Store (0x4000003c, IDEX) Store (S43C, DATA) - Store (0x40000058, IDEX) Store (S458, DATA) - Store (0x40000068, IDEX) Store (S468, DATA) - Store (0x4000006c, IDEX) Store (S46C, DATA) - Store (0x40000070, IDEX) Store (S470, DATA) - Store (0x40000080, IDEX) Store (S480, DATA) - Store (0x40000084, IDEX) Store (S484, DATA) - Store (0x40000088, IDEX) Store (S488, DATA) - Store (0x4000008c, IDEX) Store (S48C, DATA) -} diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 7e2b7fc..ad76f3a 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -39,7 +39,6 @@ #define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ #define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ #define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ -#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ #define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ #define ALINK_AHB_ADDRESS 0xfedc0000 diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 5023df6..1c02bb7 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -52,12 +52,7 @@ uint8_t tmax; /* 0x30 - CPU Tj_max */ uint8_t pad1[3]; aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ - uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ - uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ - uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ - uint32_t eh10; /* 0x40 - EHCI BAR */ - uint8_t unused[184]; + uint8_t unused[200]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 7ba179f..665874a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -178,31 +178,6 @@ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ -/* XHCI_PM Registers: 0xfed81c00 */ -#define XHCI_PM_INDIRECT_INDEX 0x48 -#define XHCI_PM_INDIRECT_DATA 0x4c -#define XHCI_OVER_CURRENT_CONTROL 0x30 -#define USB_OC0 0 -#define USB_OC1 1 -#define USB_OC2 2 -#define USB_OC3 3 -#define USB_OC4 4 -#define USB_OC5 5 -#define USB_OC6 6 -#define USB_OC7 7 -#define USB_OC_DISABLE 0xf -#define USB_OC_DISABLE_ALL 0xffff -#define OC_PORT0_SHIFT 0 -#define OC_PORT1_SHIFT 4 -#define OC_PORT2_SHIFT 8 -#define OC_PORT3_SHIFT 12 - -#define EHCI_OVER_CURRENT_CONTROL 0x70 -#define EHCI_HUB_CONFIG4 0x90 -#define DEBUG_PORT_SELECT_SHIFT 16 -#define DEBUG_PORT_ENABLE BIT(18) -#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) - /* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 #define FCH_AOAC_D3_CONTROL_I2C0 0x4a @@ -231,8 +206,6 @@ #define FCH_AOAC_D3_STATE_UART0 0x57 #define FCH_AOAC_D3_STATE_UART1 0x59 #define FCH_AOAC_D3_STATE_AMBA 0x63 -#define FCH_AOAC_D3_STATE_USB2 0x65 -#define FCH_AOAC_D3_STATE_USB3 0x6f /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) @@ -332,10 +305,7 @@ unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; unsigned int st_e:1; /* 15: SATA */ - unsigned int :2; - unsigned int ehce:1; /* 18: EHCI */ - unsigned int :4; - unsigned int xhce:1; /* 23: xHCI */ + unsigned int :8; unsigned int sd_e:1; /* 24: SDIO */ unsigned int :2; unsigned int espi:1; /* 27: ESPI */ @@ -350,11 +320,6 @@ uint16_t wake_from; }; -#define XHCI_FW_SIG_OFFSET 0xc -#define XHCI_FW_ADDR_OFFSET 0x6 -#define XHCI_FW_SIZE_OFFSET 0x8 -#define XHCI_FW_BOOTRAM_SIZE 0x8000 - void enable_aoac_devices(void); void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); @@ -403,6 +368,7 @@ * a default weak function in usb.c if the mainboard doesn't have any * over current support. */ +#define USB_OC_DISABLE_ALL 0xffff int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 711ebc5..dca3591 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -77,7 +77,6 @@ void SetFchResetParams(FCH_RESET_INTERFACE *params) { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); if (dev && dev->enabled) { params->SataEnable = sb_sata_enable(); params->IdeEnable = sb_ide_enable(); @@ -579,10 +578,6 @@ static void set_sb_final_nvs(void) { - uintptr_t amdfw_rom; - uintptr_t xhci_fw; - uintptr_t fwaddr; - size_t fwsize; const struct device *sd, *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); @@ -595,29 +590,12 @@ gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; - - amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); - - fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - gnvs->fw00 = 0; - gnvs->fw01 = ((32 * KiB) << 16) + 0; - gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; - gnvs->fw03 = fwsize << 16; - - gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) - & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } void southbridge_final(void *chip_info) diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 00f8237..ae6c476 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -29,17 +29,13 @@ uint16_t map = USB_OC_DISABLE_ALL; if (dev->path.pci.devfn == XHCI_DEVFN) { - if (mainboard_get_xhci_oc_map(&map) == 0) { - xhci_pm_write32(XHCI_PM_INDIRECT_INDEX, - XHCI_OVER_CURRENT_CONTROL); - xhci_pm_write16(XHCI_PM_INDIRECT_DATA, map); - } + if (mainboard_get_xhci_oc_map(&map) == 0) + ; // TODO } - if (dev->path.pci.devfn == EHCI1_DEVFN) { + if (dev->path.pci.devfn == EHCI1_DEVFN) if (mainboard_get_ehci_oc_map(&map) == 0) - pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map); - } + ; // TODO } int __weak mainboard_get_xhci_oc_map(uint16_t *map) -- To view, visit https://review.coreboot.org/c/coreboot/+/33752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Gerrit-Change-Number: 33752 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: soc/amd/picasso: Remove stoneyridge GEC
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33751 Change subject: soc/amd/picasso: Remove stoneyridge GEC ...................................................................... soc/amd/picasso: Remove stoneyridge GEC Remove the hudson-style support for the Gigabit Ethernet Controller. Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33751/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9e96c1e..9317119 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -167,22 +167,11 @@ help Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 -config STONEYRIDGE_GEC_FWM - bool - default n - help - Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. - Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. - config STONEYRIDGE_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" depends on STONEYRIDGE_XHCI_FWM -config STONEYRIDGE_GEC_FWM_FILE - string "GEC firmware path and filename" - depends on STONEYRIDGE_GEC_FWM - config AMD_PUBKEY_FILE string "AMD public Key" default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b8a29c2..9aedbd1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -176,7 +176,6 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) -OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec) OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) @@ -198,7 +197,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ @@ -218,7 +216,6 @@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ - $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_SMUFWM_FILE) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/33751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216 Gerrit-Change-Number: 33751 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/amd/picasso: Change all remaining soc names
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33749 Change subject: soc/amd/picasso: Change all remaining soc names ...................................................................... soc/amd/picasso: Change all remaining soc names Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/southbridge.c 13 files changed, 65 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33749/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 382aaef..9e96c1e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -185,9 +185,9 @@ config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" -config STONEYRIDGE_SATA_MODE +config PICASSO_SATA_MODE int "SATA Mode" default 0 range 0 6 @@ -203,33 +203,33 @@ 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. comment "NATIVE" - depends on STONEYRIDGE_SATA_MODE = 0 + depends on PICASSO_SATA_MODE = 0 comment "AHCI" - depends on STONEYRIDGE_SATA_MODE = 2 + depends on PICASSO_SATA_MODE = 2 comment "LEGACY IDE" - depends on STONEYRIDGE_SATA_MODE = 3 + depends on PICASSO_SATA_MODE = 3 comment "IDE to AHCI" - depends on STONEYRIDGE_SATA_MODE = 4 + depends on PICASSO_SATA_MODE = 4 comment "AHCI7804" - depends on STONEYRIDGE_SATA_MODE = 5 + depends on PICASSO_SATA_MODE = 5 comment "IDE to AHCI7804" - depends on STONEYRIDGE_SATA_MODE = 6 + depends on PICASSO_SATA_MODE = 6 -if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 +if PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 config AHCI_ROM_ID string "AHCI device PCI IDs" - default "1022,7801" if STONEYRIDGE_SATA_MODE = 2 - default "1022,7804" if STONEYRIDGE_SATA_MODE = 5 + default "1022,7801" if PICASSO_SATA_MODE = 2 + default "1022,7804" if PICASSO_SATA_MODE = 5 -endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 +endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 -config STONEYRIDGE_LEGACY_FREE +config PICASSO_LEGACY_FREE bool "System is legacy free" help Select y if there is no keyboard controller in the system. @@ -242,22 +242,22 @@ Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode. -config STONEYRIDGE_ACPI_IO_BASE +config PICASSO_ACPI_IO_BASE hex default 0x400 help Base address for the ACPI registers. This value must match the hardcoded value of AGESA. -config STONEYRIDGE_UART - bool "UART controller on Stoney Ridge" +config PICASSO_UART + bool "UART controller on Picasso" default n select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO select UART_OVERRIDE_REFCLK help - There are two UART controllers in Stoney Ridge. + There are two UART controllers in Picasso. The UART registers are memory-mapped. UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e8c022f..b8a29c2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -52,7 +52,7 @@ romstage-y += reset.c romstage-y += smbus.c romstage-y += ramtop.c -romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_SPI_FLASH) += spi.c @@ -63,12 +63,12 @@ verstage-y += monotonic_timer.c verstage-y += pmutil.c verstage-y += reset.c -verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c -postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-$(CONFIG_PICASSO_UART) += uart.c postcar-y += ramtop.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -90,7 +90,7 @@ ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_SPI_FLASH) += spi.c @@ -117,7 +117,7 @@ # +-----------+ # # EC ROM should be 64K aligned. -STONEYRIDGE_FWM_POSITION=$(call int-add, \ +PICASSO_FWM_POSITION=$(call int-add, \ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) @@ -247,7 +247,7 @@ $(OPT_SMUSCS_FILE) \ --combo-capable \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ + --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) @@ -255,23 +255,23 @@ INTERMEDIATE+=add_amdfw # Calculate firmware position inside the ROM -STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ +PICASSO_FWM_ROM_POSITION=$(call int-add, \ $(call int-subtract, $(CONFIG_ROM_SIZE) \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ - "$(STONEYRIDGE_FWM_ROM_POSITION)" + "$(PICASSO_FWM_ROM_POSITION)" dd if=$(obj)/amdfw.rom \ of=$(obj)/coreboot.pre conv=notrunc bs=1 \ - seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 + seek=$(PICASSO_FWM_ROM_POSITION) >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) +apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index d1ea24f..daeb7b6 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -75,7 +75,7 @@ { acpi_header_t *header = &(fadt->header); - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); @@ -241,7 +241,7 @@ { int cores, cpu; - /* Stoney Ridge is single node, just report # of cores */ + /* Picasso is single node, just report # of cores */ cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK; cores++; /* number of cores is CmpCap+1 */ diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 7221f95..19921e1 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -32,14 +32,14 @@ #include "chip.h" /* Supplied by i2c.c */ -extern struct device_operations stoneyridge_i2c_mmio_ops; +extern struct device_operations picasso_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = stoney_init_cpus, + .init = picasso_init_cpus, .acpi_fill_ssdt_generator = generate_cpu_entries, }; @@ -132,7 +132,7 @@ sb_enable(dev); else if (dev->path.type == DEVICE_PATH_MMIO) if (i2c_acpi_name(dev) != NULL) - dev->ops = &stoneyridge_i2c_mmio_ops; + dev->ops = &picasso_i2c_mmio_ops; } static void soc_init(void *chip_info) @@ -147,8 +147,8 @@ fam15_finalize(chip_info); } -struct chip_operations soc_amd_stoneyridge_ops = { - CHIP_NAME("AMD StoneyRidge SOC") +struct chip_operations soc_amd_picasso_ops = { + CHIP_NAME("AMD Picasso SOC") .enable_dev = enable_dev, .init = soc_init, .final = soc_final diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 4f241e7..ff9c845 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -27,9 +27,9 @@ #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 -#define STONEY_I2C_DEV_MAX 4 +#define PICASSO_I2C_DEV_MAX 4 -struct soc_amd_stoneyridge_config { +struct soc_amd_picasso_config { u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; enum { DRAM_CONTENTS_KEEP, @@ -59,7 +59,7 @@ * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ u8 i2c_scl_reset; - struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX]; + struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; u8 stapm_percent; u32 stapm_time_ms; u32 stapm_power_mw; @@ -74,7 +74,7 @@ u8 lvds_poseq_blon_to_varybl; }; -typedef struct soc_amd_stoneyridge_config config_t; +typedef struct soc_amd_picasso_config config_t; extern struct device_operations pci_domain_ops; diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 1d9804d..fc9e9ec 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -105,7 +105,7 @@ .post_mp_init = enable_smi_generation, }; -void stoney_init_cpus(struct device *dev) +void picasso_init_cpus(struct device *dev) { /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 7f65a4f..9fe1588 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -46,7 +46,7 @@ return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; } -static const struct soc_amd_stoneyridge_config *get_soc_config(void) +static const struct soc_amd_picasso_config *get_soc_config(void) { const struct device *dev = pcidev_path_on_root(GNB_DEVFN); @@ -61,7 +61,7 @@ const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { - const struct soc_amd_stoneyridge_config *config; + const struct soc_amd_picasso_config *config; if (bus >= ARRAY_SIZE(i2c_bus_address)) return NULL; @@ -107,7 +107,7 @@ static void dw_i2c_soc_init(bool is_early_init) { size_t i; - const struct soc_amd_stoneyridge_config *config; + const struct soc_amd_picasso_config *config; config = get_soc_config(); @@ -135,7 +135,7 @@ dw_i2c_soc_init(false); } -struct device_operations stoneyridge_i2c_mmio_ops = { +struct device_operations picasso_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, @@ -188,7 +188,7 @@ /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ void sb_reset_i2c_slaves(void) { - const struct soc_amd_stoneyridge_config *cfg; + const struct soc_amd_picasso_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct soc_amd_i2c_save save_table[saved_pins_count]; uint8_t i, j, control; diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 71fe10e..f141a05 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -20,7 +20,7 @@ #include <arch/acpi.h> -#if CONFIG(STONEYRIDGE_LEGACY_FREE) +#if CONFIG(PICASSO_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index d9d48ad..7d47645 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -29,7 +29,7 @@ #define SOC_EARLY_VMTRR_CAR_HEAP 2 #define SOC_EARLY_VMTRR_TEMPRAM 3 -void stoney_init_cpus(struct device *dev); +void picasso_init_cpus(struct device *dev); void check_mca(void); #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index a63b164..7e2b7fc 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -61,16 +61,16 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE -#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE +#define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ -#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index fa9206e..7ba179f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -316,7 +316,7 @@ #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct stoneyridge_aoac { +struct picasso_aoac { int enable; int status; }; diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 12ee2a8..5d1ed18 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -187,7 +187,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams) { - const struct soc_amd_stoneyridge_config *cfg; + const struct soc_amd_picasso_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); if (!dev || !dev->chip_info) { @@ -224,7 +224,7 @@ void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) { - const struct soc_amd_stoneyridge_config *cfg; + const struct soc_amd_picasso_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct _PLATFORM_CONFIGURATION *platform; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 45408ea..711ebc5 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -44,7 +44,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +const static struct picasso_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -56,22 +56,22 @@ static int is_sata_config(void) { - return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) - || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); + return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE) + || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE)); } static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); + return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || + (SataAhci == CONFIG_PICASSO_SATA_MODE); } static inline int sb_ide_enable(void) { /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); + return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || + (SataLegacyIde == CONFIG_PICASSO_SATA_MODE); } void SetFchResetParams(FCH_RESET_INTERFACE *params) @@ -91,11 +91,11 @@ { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); params->AzaliaController = AzEnable; - params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + params->SataClass = CONFIG_PICASSO_SATA_MODE; if (dev && dev->enabled) { params->SataEnable = is_sata_config(); params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE == SataLegacyIde); } else { params->SataEnable = FALSE; @@ -227,7 +227,7 @@ | DECODE_ENABLE_ADLIB_PORT; /* Decode SIOs at 2E/2F and 4E/4F */ - if (CONFIG(STONEYRIDGE_LEGACY_FREE)) + if (CONFIG(PICASSO_LEGACY_FREE)) tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; lpc_enable_decode(tmp); -- To view, visit https://review.coreboot.org/c/coreboot/+/33749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Gerrit-Change-Number: 33749 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: util/amdfwtool: Add new BIOS compression tool
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33401 Change subject: util/amdfwtool: Add new BIOS compression tool ...................................................................... util/amdfwtool: Add new BIOS compression tool Add a utility to generate a compressed BIOS image for AMD Family 17h. If the input is an elf file, the utility extracts the program portion for compression. Otherwise the file is compressed as-is. In modern AMD systems, the PSP brings up DRAM then uncompresses the BIOS image into memory prior to x86 beginning execution. The PSP supports a zlib engine, and interprets the first 256 bytes as a header, where offset 0x14 containing the uncompressed size. For further details, see AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:127766506 TEST=Use with WIP Picasso Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M Makefile.inc M util/cbfstool/Makefile.inc A util/cbfstool/amdcompress.c 3 files changed, 349 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33401/1 diff --git a/Makefile.inc b/Makefile.inc index 14cd50c..2c4680c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -512,6 +512,7 @@ FMAPTOOL:=$(objutil)/cbfstool/fmaptool RMODTOOL:=$(objutil)/cbfstool/rmodtool IFWITOOL:=$(objutil)/cbfstool/ifwitool +AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -525,6 +526,9 @@ $(obj)/ifwitool: $(IFWITOOL) cp $< $@ +$(obj)/amdcompress: $(AMDCOMPRESS) + cp $< $@ + _WINCHECK=$(shell uname -o 2> /dev/null) STACK= ifeq ($(_WINCHECK),Msys) @@ -637,7 +641,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) ########################################################################### # Common recipes for all stages diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 7928520..2f803b3 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -70,6 +70,12 @@ cbfscompobj += $(compressionobj) cbfscompobj += cbfscomptool.o +amdcompobj := +amdcompobj += amdcompress.o +amdcompobj += elfheaders.o +amdcompobj += common.o +amdcompobj += xdr.o + TOOLCFLAGS ?= -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings @@ -153,6 +159,10 @@ printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfscompobj)) +$(objutil)/cbfstool/amdcompress: $(addprefix $(objutil)/cbfstool/,$(amdcompobj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(amdcompobj)) -lz + # Yacc source is superset of header $(objutil)/cbfstool/fmd.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c new file mode 100644 index 0000000..efa332f --- /dev/null +++ b/util/cbfstool/amdcompress.c @@ -0,0 +1,334 @@ +#include <stdio.h> +#include <stdlib.h> +#include <fcntl.h> +#include <sys/stat.h> +#include <getopt.h> +#include <elfparsing.h> +#include "zlib.h" + +#define DEBUG_FILE 0 + +#define HDR_SIZE 256 +#define UNCOMP_MAX 0x300000 + +#define DIR_UNDEF 0 +#define DIR_COMP 1 +#define DIR_UNCOMP 2 + +typedef struct _header { + uint32_t rsvd1[5]; + uint32_t size; + uint32_t rsvd2[58]; +} __attribute__((packed)) header; + +static const char *optstring = "i:o:cm:uh"; + +static struct option long_options[] = { + {"infile", required_argument, 0, 'i' }, + {"outfile", required_argument, 0, 'o' }, + {"compress", required_argument, 0, 'c' }, + {"maxsize", required_argument, 0, 'h' }, + {"uncompress", required_argument, 0, 'u' }, + {"help", no_argument, 0, 'h' }, +}; + +static void usage(void) +{ + printf("<name>: Extract or create a zlib compressed BIOS binary\n"); + printf(" image. A compressed image contains a 256 byte\n"); + printf(" header with a 32-bit size at 0x14.\n"); + printf("Usage: <name> -i in_file -o out_file -[c|u]\n"); + printf("-i | --infile <FILE> Input file\n"); + printf("-o | --outfile <FILE> Output file\n"); + printf("-c | --compress Compress\n"); + printf("-m | --maxsize <HEX_VAL> Maximum uncompressed size (optional)\n"); + printf(" * On compress: verify uncompressed size\n"); + printf(" will be less than or equal maxsize\n"); + printf(" * On uncompress: override default buffer size\n"); + printf(" allocation of 0x%x bytes\n", UNCOMP_MAX); + printf("-u | --uncompress Uncompress\n"); + printf("-h | --help Display this message\n"); + + exit(1); +} + +static int do_file(char *name, size_t *size, int oflag) +{ + struct stat fd_stat; + int fd; + + fd = open(name, oflag, 0666); + if (fd < 0) { + return -1; + } + + if (fstat(fd, &fd_stat)) { + close(fd); + return -1; + } + + if (size) + *size = fd_stat.st_size; + return fd; +} + +static int parse_elf_to_xip_ram(const struct buffer *input, + struct buffer *output) +{ + struct parsed_elf pelf; + + if (parse_elf(input, &pelf, ELF_PARSE_ALL)) + return 1; + if (buffer_create(output, pelf.phdr->p_filesz, "") != 0) + return 1; + + memcpy(output->data, input->data + pelf.phdr->p_offset, output->size); + + return 0; +} + +static int iself(const void *input) +{ + const Elf32_Ehdr *ehdr = input; + return !memcmp(ehdr->e_ident, ELFMAG, 4); +} + +/* todo: Consider using deflate() and inflate() instead of compress() and + * decompress(), especially if memory allocation somehow becomes a problem. + * Those two functions can operate on streams and process chunks of data. + */ + +static void do_compress(char *outf, char *inf, size_t max_size) +{ + int out_fd, in_fd; + char *in_buf, *out_buf; + struct buffer bios_buf; + size_t size_unc, size_comp; + size_t bytes; + int err; + + in_fd = do_file(inf, &size_unc, O_RDONLY); + if (in_fd < 0) { + printf("\tError opening input file %s\n", inf); + err = 1; + goto out; + } + + out_fd = do_file(outf, 0, O_CREAT | O_WRONLY); + if (out_fd < 0) { + printf("\tError opening output file %s\n", outf); + err = 1; + goto out_close_in; + } + + in_buf = malloc(size_unc); + if (!in_buf) { + printf("\tError allocating 0x%zx bytes for input buffer\n", + size_unc); + err = 1; + goto out_close_out; + } + + bytes = read(in_fd, in_buf, size_unc); + if (bytes != size_unc) { + printf("\tError reading input file %s\n", inf); + err = 1; + goto out_free_in; + } + + struct buffer inbf; + inbf.data = in_buf; + inbf.size = size_unc; + + if (iself(in_buf)) { + /* if elf, convert the in_buf to point to the progbits */ + err = parse_elf_to_xip_ram(&inbf, &bios_buf); + if (err) { + err = 1; + printf("\tError parsing ELF file %s\n", inf); + goto out_free_in; + } + free(in_buf); + in_buf = bios_buf.data; + size_unc = bios_buf.size; + } + + size_comp = size_unc; /* todo: tbd worst case? */ + if (max_size && size_unc > max_size) { + printf("\tError - size (%zx) exceeds specified max_size (%zx)\n", + size_unc, max_size); + err = 1; + goto out_free_in; + } + + out_buf = malloc(size_comp + sizeof(header)); + if (!out_buf) { + printf("\tError allocating 0x%zx bytes for output buffer\n", + size_comp + sizeof(header)); + err = 1; + goto out_free_in; + } + + err = compress((Bytef *)(out_buf + sizeof(header)), &size_comp, + (Bytef *)in_buf, size_unc); + if (err != Z_OK) { + printf("\tzlib compression error %d\n", err); + err = 1; + goto out_free_out; + } + + if (DEBUG_FILE) + printf("\tCompressed 0x%zx bytes into 0x%zx\n", + size_unc, size_comp); + + memset(out_buf, 0, sizeof(header)); + ((header *)out_buf)->size = size_comp; + + bytes = write(out_fd, out_buf, size_comp + sizeof(header)); + if (bytes != size_comp + sizeof(header)) { + printf("\tError writing to %s\n", outf); + err = 1; + /* fall through to out_free_out */ + } + +out_free_out: + free(out_buf); +out_free_in: + free(in_buf); +out_close_out: + close(out_fd); +out_close_in: + close(in_fd); +out: + if (err) + exit(err); +} + +static void do_uncompress(char *outf, char *inf, size_t max_size) +{ + int out_fd, in_fd; + char *in_buf, *out_buf; + size_t size_unc, size_comp; + size_t bytes; + int err; + + in_fd = do_file(inf, &size_comp, O_RDONLY); + if (in_fd < 0) { + printf("\tError opening input file %s\n", inf); + err = 1; + goto out; + } + + out_fd = do_file(outf, 0, O_CREAT | O_WRONLY); + if (out_fd < 0) { + printf("\tError opening output file %s\n", outf); + err = 1; + goto out_close_in; + } + + in_buf = malloc(size_comp); + if (!in_buf) { + printf("\tError allocating 0x%zx bytes for input buffer\n", + size_comp); + err = 1; + goto out_close_out; + } + + bytes = read(in_fd, in_buf, size_comp); + if (bytes != size_comp) { + printf("\tError reading input file %s\n", inf); + err = 1; + goto out_free_in; + } + + size_comp = ((header *)in_buf)->size; + + size_unc = max_size ? max_size : UNCOMP_MAX; + out_buf = malloc(size_unc); + if (!out_buf) { + printf("\tError allocating 0x%zx bytes for output buffer\n", + size_unc); + err = 1; + goto out_free_in; + } + + err = uncompress((Bytef *)out_buf, &size_unc, + (Bytef *)in_buf + sizeof(header), size_comp); + if (err != Z_OK) { + printf("\tzlib uncompression error %d\n", err); + err = 1; + goto out_free_out; + } + + if (DEBUG_FILE) + printf("Uncompressed 0x%zx bytes into 0x%zx\n", + size_comp, size_unc); + + bytes = write(out_fd, out_buf, size_unc); + if (bytes != size_unc) { + printf("\tError writing to %s\n", outf); + err = 1; + /* fall through to out_free_out */ + } + +out_free_out: + free(out_buf); +out_free_in: + free(in_buf); +out_close_out: + close(out_fd); +out_close_in: + close(in_fd); +out: + if (err) + exit(err); +} + +int main(int argc, char *argv[]) +{ + int c; + char *inf = 0, *outf = 0, *scratch; + int direction = DIR_UNDEF; + size_t max_size = 0; + + while (1) { + int optindex = 0; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + if (c == -1) + break; + + switch (c) { + case 'i': + inf = optarg; + break; + case 'o': + outf = optarg; + break; + case 'c': + if (direction != DIR_UNDEF) + usage(); + direction = DIR_COMP; + break; + case 'u': + if (direction != DIR_UNDEF) + usage(); + direction = DIR_UNCOMP; + break; + case 'm': + max_size = strtoull(optarg, &scratch, 16); + break; + case 'h': + usage(); + } + } + if (!inf || !outf || direction == DIR_UNDEF) + usage(); + + if (direction == DIR_COMP) + do_compress(outf, inf, max_size); + else + do_uncompress(outf, inf, max_size); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8 Gerrit-Change-Number: 33401 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

6 26

Change in ...coreboot[master]: libpayload/usb: Increase the SET ADDRESS timeout
by Keith Short (Code Review) 03 Jul '19

03 Jul '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33671 Change subject: libpayload/usb: Increase the SET ADDRESS timeout ...................................................................... libpayload/usb: Increase the SET ADDRESS timeout The SET ADDRESS timeout was set to only 100 ms for the xHCI driver. The USB specification indicates a maximum response time of 50 ms for the SET ADDRESS request, but this does not account for propagation time of the request through USB hubs. Analysis of other USB host driver timeouts: EHCI: 3 seconds OHCI: 2 seconds UHCI: 30 ms DWC: 3 seconds BUG=b:124730179 BRANCH=none TEST=Build libpayload and depthcharge on sarien/arcada. TEST=Without change replicate USB set address timeouts in depthcharge when dock and 4K monitor connected (which includes a total of 4 USB hubs). With timeout fix, depthcharge boots OS with no USB errors and the same USB topology. Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M payloads/libpayload/drivers/usb/xhci_events.c 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33671/1 diff --git a/payloads/libpayload/drivers/usb/xhci_events.c b/payloads/libpayload/drivers/usb/xhci_events.c index dacb5d86..e2c124f 100644 --- a/payloads/libpayload/drivers/usb/xhci_events.c +++ b/payloads/libpayload/drivers/usb/xhci_events.c @@ -281,12 +281,13 @@ const int clear_event) { /* - * The Address Device Command should take most time, as it has to - * communicate with the USB device. Set address processing shouldn't - * take longer than 50ms (at the slave). Let's take a timeout of - * 100ms. + * The USB specification indicates that maximum response time to a SET + * ADDRESS request is 50 ms. However, this time does not account for + * the propagation delay to send the request through any hubs connected + * between the device and the root hub. Set the timeout to the maximum + * USB processing time, 5 seconds, to allow for complex USB topologies. */ - unsigned long timeout_us = 100 * 1000; /* 100ms */ + unsigned long timeout_us = 5 * 1000 * 1000; /* 5s */ int cc = TIMEOUT; while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) { if ((xhci->er.cur->ptr_low == virt_to_phys(address)) && -- To view, visit https://review.coreboot.org/c/coreboot/+/33671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468 Gerrit-Change-Number: 33671 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

7 24

Change in ...coreboot[master]: aopen/dxplplusu: Replace use of dev_find_slot()
by Kyösti Mälkki (Code Review) 03 Jul '19

03 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34002 Change subject: aopen/dxplplusu: Replace use of dev_find_slot() ...................................................................... aopen/dxplplusu: Replace use of dev_find_slot() To use fixed PCI bus numbers is always invalid. Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/acpi_tables.c D src/mainboard/aopen/dxplplusu/bus.h 2 files changed, 22 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/34002/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 039e4ec..769f434 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -20,13 +20,17 @@ #include <arch/acpi.h> #include <device/pci.h> -#include <assert.h> -#include "bus.h" + +#define IOAPIC_ICH4 2 +#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */ +#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */ + +#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */ unsigned long acpi_fill_madt(unsigned long current) { unsigned int irq_start = 0; - struct device *dev = NULL; + struct device *bdev, *dev = NULL; struct resource* res = NULL; /* SJM: Hard-code CPU LAPIC entries for now */ @@ -39,22 +43,24 @@ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start); irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + bdev = pcidev_on_root(2, 0); /* P64H2 Bus B IOAPIC */ - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); - if (!dev) - BUG(); /* Config.lb error? */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + if (bdev) + dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + } /* P64H2 Bus A IOAPIC */ - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); - if (!dev) - BUG(); /* Config.lb error? */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; - + if (bdev) + dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + } /* Map ISA IRQ 0 to IRQ 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0); diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h deleted file mode 100644 index 12eef12..0000000 --- a/src/mainboard/aopen/dxplplusu/bus.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef DXPLPLUSU_BUS_H_INCLUDED -#define DXPLPLUSU_BUS_H_INCLUDED - -/* These were determined by seeing how coreboot enumerates the various - * PCI (and PCI-like) buses on the board. - */ - -#define PCI_BUS_ROOT 0 -#define PCI_BUS_AGP 1 /* AGP */ -#define PCI_BUS_E7501_HI_B 2 /* P64H2#1 */ -#define PCI_BUS_P64H2_B 3 /* P64H2#1 bus B */ -#define PCI_BUS_P64H2_A 4 /* P64H2#1 bus A */ -#define PCI_BUS_ICH4 5 /* ICH4 */ - -/* IOAPIC addresses determined by coreboot enumeration. */ -/* Someday add functions to get APIC IDs and versions from the chips themselves. */ - -#define IOAPIC_ICH4 2 -#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */ -#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */ - -#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */ - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff Gerrit-Change-Number: 34002 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: aopen/dxplplusu: Remove PIRQ table
by Kyösti Mälkki (Code Review) 03 Jul '19

03 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34001 Change subject: aopen/dxplplusu: Remove PIRQ table ...................................................................... aopen/dxplplusu: Remove PIRQ table It was never tested or injected. Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/Kconfig D src/mainboard/aopen/dxplplusu/irq_tables.c 2 files changed, 0 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34001/1 diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 905ddd5..7dc0eab 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -7,8 +7,6 @@ select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X -# select HAVE_PIRQ_TABLE -# select PIRQ_ROUTE select UDELAY_TSC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c deleted file mode 100644 index b7e1187..0000000 --- a/src/mainboard/aopen/dxplplusu/irq_tables.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include "bus.h" - -#define UNUSED_INTERRUPT {0, 0} -#define PIRQ_A 0x60 -#define PIRQ_B 0x61 -#define PIRQ_C 0x62 -#define PIRQ_D 0x63 -#define PIRQ_E 0x68 -#define PIRQ_F 0x69 -#define PIRQ_G 0x6A -#define PIRQ_H 0x6B - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Size of this struct in bytes */ - 0, /* PCI bus number on which the interrupt router resides */ - PCI_DEVFN(31, 0), /* PCI device/function number of the interrupt router */ - 0, /* PCI-exclusive IRQ bitmap */ - PCI_VENDOR_ID_INTEL, /* Vendor ID of compatible PCI interrupt router */ - PCI_DEVICE_ID_INTEL_82801DB_LPC, /* Device ID of compatible PCI interrupt router */ - 0, /* Additional miniport information */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* Reserved, must be zero */ - 0xB1, /* Checksum of the entire structure (causes 8-bit sum == 0) */ - { - /* NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space */ - /* This was determined from linux-2.6.11/arch/i386/pci/irq.c */ - /* bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 */ - /* ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 */ - /* Not sure why IRQ9 isn't routable (inherited from Tyan S2735) */ - - /* INTA# INTB# INTC# INTD# */ - /* bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu */ - - {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, /* IDE / SMBus */ - {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* USB 1.1 */ - - {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* GbE */ - - {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* SCSI */ - - {PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* 32-bit slot */ - - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3 Gerrit-Change-Number: 34001 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/e7505: Drop debug code
by Kyösti Mälkki (Code Review) 03 Jul '19

03 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33958 Change subject: intel/e7505: Drop debug code ...................................................................... intel/e7505: Drop debug code Only (conditionally) used part was dump_pci_device() and that was never particularly useful either. Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/e7505/Makefile.inc D src/northbridge/intel/e7505/debug.c D src/northbridge/intel/e7505/debug.h M src/northbridge/intel/e7505/raminit.c 4 files changed, 0 insertions(+), 222 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33958/1 diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 7f7c5e4..4eda3d1 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -4,7 +4,6 @@ ramstage-y += memmap.c romstage-y += raminit.c -romstage-y += debug.c romstage-y += memmap.c postcar-y += memmap.c diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c deleted file mode 100644 index 357a963..0000000 --- a/src/northbridge/intel/e7505/debug.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_def.h> -#include <console/console.h> -#include <stdlib.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <spd.h> - -#include "raminit.h" -#include "debug.h" - -/* - * generic debug code, used by mainboard specific romstage.c - * - */ - -void print_debug_pci_dev(unsigned dev) -{ - printk(BIOS_DEBUG, "PCI: %02x:%02x.%x", - (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7); -} - -void print_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, "\n"); - } -} - -void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - - for (i = 0; i < 256; i++) { - unsigned char val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "\n%02x:",i); - val = pci_read_config8(dev, i); - printk(BIOS_DEBUG, " %02x", val); - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_pci_devices_on_bus(unsigned busn) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - printk(BIOS_DEBUG, "\n"); - for (i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); - status = spd_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); - status = spd_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - } -} -void dump_smbus_registers(void) -{ - unsigned device; - printk(BIOS_DEBUG, "\n"); - for (device = 1; device < 0x80; device++) { - int j; - if (spd_read_byte(device, 0) < 0) - continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = spd_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ",j); - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } -} - -void dump_io_resources(unsigned port) -{ - int i; - printk(BIOS_DEBUG, "%04x:\n", port); - for (i = 0; i < 256; i++) { - uint8_t val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = inb(port); - printk(BIOS_DEBUG, " %02x",val); - if ((i & 0x0f) == 0x0f) { - printk(BIOS_DEBUG, "\n"); - } - port++; - } -} diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h deleted file mode 100644 index 98ca848..0000000 --- a/src/northbridge/intel/e7505/debug.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef E7505_DEBUG_H -#define E7505_DEBUG_H - -void print_debug_pci_dev(unsigned dev); -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_pci_devices_on_bus(unsigned busn); -void dump_spd_registers(const struct mem_controller *ctrl); -void dump_smbus_registers(void); -void dump_io_resources(unsigned port); - -#endif diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 3bb1f67..8a336e6 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -43,7 +43,6 @@ #include "raminit.h" #include "e7505.h" -#include "debug.h" /*----------------------------------------------------------------------------- Definitions: @@ -58,12 +57,10 @@ #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) -#define DUMPNORTH() dump_pci_device(MCHDEV) #else #define RAM_DEBUG_MESSAGE(x) #define RAM_DEBUG_HEX32(x) #define RAM_DEBUG_HEX8(x) -#define DUMPNORTH() #endif #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) @@ -1768,9 +1765,6 @@ */ void e7505_mch_init(const struct mem_controller *memctrl) { - RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); - DUMPNORTH(); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_set_registers(memctrl); @@ -1783,9 +1777,6 @@ sdram_post_ecc(memctrl); timestamp_add_now(TS_AFTER_INITRAM); - - RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); - DUMPNORTH(); } int e7505_mch_is_ready(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/33958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670 Gerrit-Change-Number: 33958 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove variable length arrays
by build bot (Jenkins) (Code Review) 03 Jul '19

03 Jul '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33821 ) Change subject: src: Remove variable length arrays ...................................................................... Patch Set 9: (3 comments) https://review.coreboot.org/c/coreboot/+/33821/9/src/northbridge/amd/amdmct… File src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c: https://review.coreboot.org/c/coreboot/+/33821/9/src/northbridge/amd/amdmct… PS9, Line 1260: struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t receiver_start, uint8_t receiver_end, uint8_t lane_start) line over 96 characters https://review.coreboot.org/c/coreboot/+/33821/9/src/northbridge/amd/amdmct… PS9, Line 1741: dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane); line over 96 characters https://review.coreboot.org/c/coreboot/+/33821/9/src/northbridge/amd/amdmct… PS9, Line 1797: TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/33821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Gerrit-Change-Number: 33821 Gerrit-PatchSet: 9 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jul 2019 16:42:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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