coreboot-gerrit July 2019

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Change in coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Ken Lu (Code Review) 03 Jul '19

03 Jul '19

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 5: > Patch Set 5: > > (1 comment) Correct the CL link . https://review.coreboot.org/c/coreboot/+/33820 -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jul 2019 04:05:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/33954/5/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/overridetree.cb: https://review.coreboot.org/c/coreboot/+/33954/5/src/mainboard/google/hatch… PS5, Line 81: CPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" > You will still need this change for helios. CL:33820 have modify GPP_A21 -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jul 2019 02:40:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus/variants/fleex: Enable EMR function for Grob360S
by Chris Zhou (Code Review) 03 Jul '19

03 Jul '19

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33802 Change subject: mb/google/octopus/variants/fleex: Enable EMR function for Grob360S ...................................................................... mb/google/octopus/variants/fleex: Enable EMR function for Grob360S Enable EMR function for Grob360S BUG=b:135968368 BRANCH=octopus TEST=Work normally with I2C6 which HW reworked. Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478 Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/fleex/overridetree.cb 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33802/1 diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 89adfb8..330cc02 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -30,7 +30,7 @@ PAD_NC(GPIO_138, UP_20K), PAD_NC(GPIO_139, UP_20K), - PAD_NC(GPIO_140, UP_20K), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* GPIO_140 -- PEN_RESET */ PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), PAD_NC(GPIO_145, UP_20K), diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 19246e0..3050a7b 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -61,6 +61,9 @@ .speed_mhz = 1, .early_init = 1, }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 104, @@ -80,7 +83,19 @@ }" device domain 0 on - device pci 16.0 off end # - I2C 0 + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 device pci 16.1 off end # - I2C 1 device pci 17.1 on chip drivers/i2c/da7219 -- To view, visit https://review.coreboot.org/c/coreboot/+/33802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478 Gerrit-Change-Number: 33802 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common/lpc: Add Picasso ID
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33758 Change subject: soc/amd/common/lpc: Add Picasso ID ...................................................................... soc/amd/common/lpc: Add Picasso ID Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33758/1 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b896517..c794601 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -337,6 +337,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_LPC, PCI_DEVICE_ID_AMD_CZ_LPC, + PCI_DEVICE_ID_AMD_PCO_LPC, 0 }; static const struct pci_driver lpc_driver __pci_driver = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed Gerrit-Change-Number: 33758 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common/iommu: Add Picasso ID
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33757 Change subject: soc/amd/common/iommu: Add Picasso ID ...................................................................... soc/amd/common/iommu: Add Picasso ID Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ib000e12cd568dd83b9533efe66e67878b806b3f3 --- M src/soc/amd/common/block/iommu/iommu.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33757/1 diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 1c982ca..c068501 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -49,6 +49,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, + PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib000e12cd568dd83b9533efe66e67878b806b3f3 Gerrit-Change-Number: 33757 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Add custom SAR values for Blooguard
by Tony Huang (Code Review) 03 Jul '19

03 Jul '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33935 Change subject: mb/google/octopus: Add custom SAR values for Blooguard ...................................................................... mb/google/octopus: Add custom SAR values for Blooguard Blooguard would use different SAR values. Use sku-id to load SAR values. BUG=b:135078377 BRANCH=octopus TEST=build Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/Makefile.inc A src/mainboard/google/octopus/variants/bloog/mainboard.c 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33935/1 diff --git a/src/mainboard/google/octopus/variants/bloog/Makefile.inc b/src/mainboard/google/octopus/variants/bloog/Makefile.inc index 9fb63f5..152b46e 100644 --- a/src/mainboard/google/octopus/variants/bloog/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bloog/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/bloog/mainboard.c b/src/mainboard/google/octopus/variants/bloog/mainboard.c new file mode 100644 index 0000000..46dba61 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + return NULL; + + if (sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52) + filename = "wifi_sar-blooguard.hex"; + + return filename; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97 Gerrit-Change-Number: 33935 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/commom/hda: Add Picasso IDs
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33756 Change subject: soc/amd/commom/hda: Add Picasso IDs ...................................................................... soc/amd/commom/hda: Add Picasso IDs Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I02b279a2b625ecbdf827cb4643d772eb81ddfe70 --- M src/soc/amd/common/block/hda/hda.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33756/1 diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index f4ea732..49fc1a6 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -21,6 +21,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, PCI_DEVICE_ID_AMD_CZ_HDA, + PCI_DEVICE_ID_AMD_PCO_HDA0, + PCI_DEVICE_ID_AMD_PCO_HDA1, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02b279a2b625ecbdf827cb4643d772eb81ddfe70 Gerrit-Change-Number: 33756 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: soc/amd/picasso: Remove all PSP runtime functions
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33754 Change subject: soc/amd/picasso: Remove all PSP runtime functions ...................................................................... soc/amd/picasso: Remove all PSP runtime functions Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/romstage.c 8 files changed, 0 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33754/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f691cb5..33aae26 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -50,7 +50,6 @@ select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select C_ENVIRONMENT_BOOTBLOCK @@ -65,7 +64,6 @@ select POSTCAR_CONSOLE select SSE2 select RTC - select SOC_AMD_PSP_SELECTABLE_SMU_FW config VBOOT select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f6fa9fa..93a8bbb 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -257,8 +257,6 @@ endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) - cbfs-files-y += smu_fw cbfs-files-y += smu_fw2 smu_fw-file := $(SMUFWM_FILE) @@ -266,6 +264,4 @@ smu_fw2-file := $(SMUFIRMWARE2_FILE) smu_fw2-type := raw -endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) - endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 19921e1..6dc47cd 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -25,7 +25,6 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <amdblocks/psp.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> @@ -159,10 +158,6 @@ int s3_resume = acpi_s3_resume_allowed() && romstage_handoff_is_resume(); if (!s3_resume) { - post_code(0x46); - if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); - post_code(0x47); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index fc9e9ec..bee2b4b 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -121,23 +121,6 @@ { check_mca(); setup_lapic(); - - /* - * Per AMD, sync an undocumented MSR with the PSP base address. - * Experiments showed that if you write to the MSR after it has - * been previously programmed, it causes a general protection fault. - * Also, the MSR survives warm reset and S3 cycles, so we need to - * test if it was previously written before writing to it. - */ - msr_t psp_msr; - uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ - psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); - psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - psp_msr = rdmsr(0xc00110a2); - if (psp_msr.lo == 0) { - psp_msr.lo = psp_bar; - wrmsr(0xc00110a2, psp_msr); - } } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index ad76f3a..1d89fd7 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -18,7 +18,6 @@ #define __SOC_PICASSO_IOMAP_H__ /* MMIO Ranges */ -#define PSP_MAILBOX_BAR3_BASE 0xf0a00000 #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 478a2cb..56f1a810 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -95,13 +95,6 @@ #define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) #define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) -/* Platform Security Processor */ -#define PSP_DEV 0x8 -#define PSP_FUNC 0 -#define PSP_DEVID 0x1578 -#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC) -#define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC) - /* HD Audio 1 */ #define HDA1_DEV 0x9 #define HDA1_FUNC 2 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 665874a..9e2b901 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -279,11 +279,6 @@ #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) -/* Platform Security Processor D8F0 */ -#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_BAR_ENABLES 0x48 -#define PSP_MAILBOX_BAR_EN 0x10 - /* IO 0xcf9 - Reset control port*/ #define FULL_RST BIT(3) #define RST_CMD BIT(2) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 5d1ed18..904f556 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -32,7 +32,6 @@ #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/southbridge.h> -#include <amdblocks/psp.h> #include "chip.h" @@ -41,28 +40,6 @@ /* By default, don't do anything */ } -static void load_smu_fw1(void) -{ - u32 base, limit, cmd; - - /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ - base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); - - /* Preload a value into "BAR3" and enable it */ - pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); - pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); - - /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); -} - static void agesa_call(void) { post_code(0x37); @@ -94,9 +71,6 @@ console_init(); - if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - load_smu_fw1(); - mainboard_romstage_entry(s3_resume); bsp_agesa_call(); @@ -143,9 +117,6 @@ post_code(0x61); } - post_code(0x42); - psp_notify_dram(); - post_code(0x43); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/33754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Gerrit-Change-Number: 33754 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: soc/amd/picasso: Remove fanless SKU option
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33753 Change subject: soc/amd/picasso: Remove fanless SKU option ...................................................................... soc/amd/picasso: Remove fanless SKU option The command line options for picasso will look different than stoneyridge. Remove the fanned/fanless distinction to simplify the makefile. Picasso will use subprograms instead of fanned/fanless SKUs. Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 2 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33753/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f692f95..f691cb5 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -271,22 +271,6 @@ If unsure, answer 'y' -config SOC_AMD_SMU_FANLESS - bool - depends on SOC_AMD_PSP_SELECTABLE_SMU_FW - default n if SOC_AMD_SMU_NOTFANLESS - default y - -config SOC_AMD_SMU_FANNED - bool - depends on SOC_AMD_PSP_SELECTABLE_SMU_FW - default n - select SOC_AMD_SMU_NOTFANLESS - -config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use - bool - depends on SOC_AMD_PSP_SELECTABLE_SMU_FW - config AMDFW_OUTSIDE_CBFS bool "The AMD firmware is outside CBFS" default n diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index dbb0e8e..f6fa9fa 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -141,10 +141,8 @@ ###8 - Check for SMU firmware named either *.sbin or *.csbin ### TODO: Remove *.sbin section after the blobs repo is updated. SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFWM_FILE))","") SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin endif ###95 @@ -167,10 +165,8 @@ ###18- Check for SMU firmware2 named either *.sbin or *.csbin ### TODO: Remove *.sbin section after the blobs repo is updated. SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) @@ -189,10 +185,6 @@ endif OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) -SUBPROG_FN_SMU_FW=1 -OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) -OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ @@ -201,13 +193,11 @@ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ $(call strip_quotes, $(PSPNVRAM_FILE)) \ $(call strip_quotes, $(SMUFWM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FN_FILE)) \ $(call strip_quotes, $(SMUSCS_FILE)) \ $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -227,7 +217,6 @@ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_SMUFWM_FILE) \ - $(OPT_SMUFWM_FN_FILE) \ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ $(OPT_PSPSCUREOS_FILE) \ @@ -236,7 +225,6 @@ $(OPT_PSPTRUSTLETS_FILE) \ $(OPT_TRUSTLETKEY_FILE) \ $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUFIRMWARE2_FN_FILE) \ $(OPT_SMUSCS_FILE) \ --combo-capable \ --flashsize $(CONFIG_ROM_SIZE) \ @@ -273,18 +261,10 @@ cbfs-files-y += smu_fw cbfs-files-y += smu_fw2 -smu_fw-type := raw -smu_fw2-type := raw - -ifeq ($(CONFIG_SOC_AMD_SMU_FANLESS),y) -smu_fw-file := $(SMUFWM_FN_FILE) -smu_fw2-file := $(SMUFIRMWARE2_FN_FILE) -else ifeq ($(CONFIG_SOC_AMD_SMU_FANNED),y) smu_fw-file := $(SMUFWM_FILE) +smu_fw-type := raw smu_fw2-file := $(SMUFIRMWARE2_FILE) -else -$(error "Proper SMU Firmware not selected") -endif +smu_fw2-type := raw endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/33753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace Gerrit-Change-Number: 33753 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Remove SD controller
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33988 Change subject: soc/amd/picasso: Remove SD controller ...................................................................... soc/amd/picasso: Remove SD controller Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 6 files changed, 3 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33988/1 diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index cdb32cc..cc264e6 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -58,9 +58,7 @@ UT1E, 1, // UART1, 12 , 2, ST_E, 1, // SATA, 15 - , 8, - SD_E, 1, // SD, 24 - , 2, + , 11, ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 8cdb4d2..206fdfd 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -53,21 +53,6 @@ /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> -/* 0:14.7 - SD Controller */ -Device(SDCN) { - Name(_ADR, 0x00140007) - - Method(_PS0) { - FDDC(24, 0) - } - Method(_PS3) { - FDDC(24, 3) - } - Method(_PSC) { - Return(SDTD) - } -} /* end SDCN */ - Name(CRES, ResourceTemplate() { /* Set the Bus number and Secondary Bus number for the PCI0 device * The Secondary bus range for PCI0 lets the system @@ -272,15 +257,6 @@ offset (0x1e6f), /* USB3 D3 State */ U3DS, 3, - offset (0x1e70), /* SD D3 Control */ - SDTD, 2, - , 1, - SDPD, 1, - , 1, - , 1, - SDRT, 1, - SDSC, 1, - offset (0x1e71), /* SD D3 State */ SDDS, 3, @@ -421,14 +397,6 @@ } } /* todo Case(15) { STD0()} */ /* SATA */ - Case(24) { /* SD */ - Store(0x00, SDTD) - Store(One, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(SDDS, Local0) - } - } } } else { /* put device into D3cold */ @@ -482,20 +450,6 @@ Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ - Case(24) { /* SD */ - Store(Zero, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(SDDS, Local0) - } - Store(0x03, SDTD) - } - } - /* Turn off Power */ - if(LEqual(I0TD, 3)) { - if(LEqual(SATD, 3)) { - if(LEqual(SDTD, 3)) { Store(Zero, PG1A) } - } } if(LEqual(I1TD, 3)) { if(LEqual(I2TD, 3)) { diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index dad9d22..776f328 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -100,8 +100,6 @@ return "LPCB"; case SATA_DEVFN: return "STCR"; - case SD_DEVFN: - return "SDCN"; case SMBUS_DEVFN: return "SBUS"; case XHCI0_DEVFN: diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index c823fdb..8a885f2 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -188,11 +188,4 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -/* SD Controller */ -#define SD_DEV 0x14 -#define SD_FUNC 7 -#define SD_DEVID 0x7906 -#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) -#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) - #endif /* __PI_PICASSO_PCI_DEVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 4392e4f..0f72a68 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -303,9 +303,7 @@ unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; unsigned int st_e:1; /* 15: SATA */ - unsigned int :8; - unsigned int sd_e:1; /* 24: SDIO */ - unsigned int :2; + unsigned int :11; unsigned int espi:1; /* 27: ESPI */ unsigned int :4; } __packed aoac_devs_t; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index dca3591..87b933e 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -578,7 +578,7 @@ static void set_sb_final_nvs(void) { - const struct device *sd, *sata; + const struct device *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs == NULL) @@ -591,8 +591,6 @@ gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); /* Rely on these being in sync with devicetree */ - sd = pcidev_path_on_root(SD_DEVFN); - gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/33988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d Gerrit-Change-Number: 33988 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019