coreboot-gerrit July 2019

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix outb order
by Jeremy Soller (Code Review) 06 Jul '19

06 Jul '19

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33940 Change subject: soc/intel/cannonlake: Fix outb order ...................................................................... soc/intel/cannonlake: Fix outb order outb accepts a value followed by a port Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I6fe3961b4f8cb2454e3b2564c3eae6af06c9e69d --- M src/soc/intel/cannonlake/lpc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33940/1 diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 6cc3451..1fe0416 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -201,10 +201,10 @@ /* Setup NMI on errors, disable SERR */ reg8 = (inb(0x61)) & 0xf0; - outb(0x61, (reg8 | (1 << 2))); + outb((reg8 | (1 << 2)), 0x61); /* Disable NMI sources */ - outb(0x70, (1 << 7)); + outb((1 << 7), 0x70); }; void lpc_soc_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/33940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fe3961b4f8cb2454e3b2564c3eae6af06c9e69d Gerrit-Change-Number: 33940 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Fix PRE-CBMEM console overflow issue
by Subrata Banik (Code Review) 06 Jul '19

06 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34006 Change subject: mb/google/hatch: Fix PRE-CBMEM console overflow issue ...................................................................... mb/google/hatch: Fix PRE-CBMEM console overflow issue This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix *** Pre-CBMEM romstage console overflowed, log truncated! *** issue. Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34006/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 8045129..26601d8 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -108,6 +108,10 @@ default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xe00 + config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN -- To view, visit https://review.coreboot.org/c/coreboot/+/34006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a Gerrit-Change-Number: 34006 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_mPGA604: Switch to TSC_CONSTANT_RATE
by Kyösti Mälkki (Code Review) 06 Jul '19

06 Jul '19

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31343 ) Change subject: cpu/intel/socket_mPGA604: Switch to TSC_CONSTANT_RATE ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/31343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02b93cefc9a8e18ad55c944fa7119b04fbbacd66 Gerrit-Change-Number: 31343 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE w...
by Subrata Banik (Code Review) 06 Jul '19

06 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34070 ) Change subject: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width ...................................................................... soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width As per EDS Sata port implemented register is byte width (bits[3:0]) hence converting required DWORD based read/write to BYTE width read/write. TEST=Able to boot from SATA device on CML hatch. Change-Id: I545b823318bae461137d41a4490117eba7c87330 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34070/1 diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 0801cb7..7dacc6e 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -43,14 +43,14 @@ static void sata_final(struct device *dev) { void *ahcibar = sata_get_ahci_bar(dev); - u32 port_impl, temp; + u8 port_impl, temp; /* Set Bus Master */ temp = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); /* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); + port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) port_impl = ~port_impl; @@ -58,9 +58,9 @@ port_impl &= 0x07; /* bit 0-2 */ /* Port enable */ - temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); + temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS); temp |= port_impl; - pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); + pci_write_config8(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/34070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I545b823318bae461137d41a4490117eba7c87330 Gerrit-Change-Number: 34070 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Fix 'inlining failed'
by HAOUAS Elyes (Code Review) 05 Jul '19

05 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34093 ) Change subject: src: Fix 'inlining failed' ...................................................................... src: Fix 'inlining failed' This is spotted out using -Winline Change-Id: I0d57a3914c7ba0cbeea151d86e604843039730bc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/cpu.h M src/commonlib/include/commonlib/endian.h M src/cpu/intel/microcode/microcode.c M src/include/bcd.h M src/include/device/i2c_bus.h M src/include/device/smbus.h M src/include/pc80/mc146818rtc.h M src/lib/memrange.c M src/lib/ramtest.c 9 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34093/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 38066c1..ac757c1 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -272,7 +272,7 @@ uint8_t x86_mask; }; -static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) +static void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) { c->x86 = (tfms >> 8) & 0xf; c->x86_model = (tfms >> 4) & 0xf; diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h index 7b08eee..86084e2 100644 --- a/src/commonlib/include/commonlib/endian.h +++ b/src/commonlib/include/commonlib/endian.h @@ -95,7 +95,7 @@ write_be16(d, val); } -static inline uint32_t read_be32(const void *src) +static uint32_t read_be32(const void *src) { const uint8_t *s = src; return (((uint32_t)s[0]) << 24) | (((uint32_t)s[1]) << 16) | @@ -199,7 +199,7 @@ write_le16(d, val); } -static inline uint32_t read_le32(const void *src) +static uint32_t read_le32(const void *src) { const uint8_t *s = src; return (((uint32_t)s[3]) << 24) | (((uint32_t)s[2]) << 16) | diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 44f7f1f..5b80662 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -49,7 +49,7 @@ u32 reserved[3]; }; -static inline u32 read_microcode_rev(void) +static u32 read_microcode_rev(void) { /* Some Intel CPUs can be very finicky about the * CPUID sequence used. So this is implemented in diff --git a/src/include/bcd.h b/src/include/bcd.h index faf3b18..298abfd 100644 --- a/src/include/bcd.h +++ b/src/include/bcd.h @@ -18,12 +18,12 @@ #include <stdint.h> -static inline uint8_t bcd2bin(uint8_t val) +static uint8_t bcd2bin(uint8_t val) { return ((val >> 4) & 0xf) * 10 + (val & 0xf); } -static inline uint8_t bin2bcd(uint8_t val) +static uint8_t bin2bcd(uint8_t val) { return ((val / 10) << 4) | (val % 10); } diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 6aa4f9b..58d885f 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -39,7 +39,7 @@ * * Returns NULL if i2c_link(dev) returns NULL. */ -static inline DEVTREE_CONST struct device *i2c_busdev(struct device *dev) +static DEVTREE_CONST struct device *i2c_busdev(struct device *dev) { struct bus *const link = i2c_link(dev); return link ? link->dev : NULL; diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 2953b25..ca264d9 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -17,7 +17,7 @@ const u8 *buffer); }; -static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) +static const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) { const struct smbus_bus_operations *bops; diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 6fa5e46..477edfc2 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -103,7 +103,7 @@ #define PC_CKS_RANGE_END 45 #define PC_CKS_LOC 46 -static inline unsigned char cmos_read(unsigned char addr) +static unsigned char cmos_read(unsigned char addr) { int offs = 0; if (addr >= 128) { @@ -135,7 +135,7 @@ outb(val, RTC_BASE_PORT + offs + 1); } -static inline void cmos_write(unsigned char val, unsigned char addr) +static void cmos_write(unsigned char val, unsigned char addr) { u8 control_state = cmos_read(RTC_CONTROL); /* There are various places where RTC bits might be hiding, diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 79a1b0e..e910d65 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -52,7 +52,7 @@ return NULL; } -static inline struct range_entry * +static struct range_entry * range_list_add(struct memranges *ranges, struct range_entry **prev_ptr, resource_t begin, resource_t end, unsigned long tag) { diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 489ca28..2cb41ba 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -45,7 +45,7 @@ * @param addr Memory to access on idx * @param value Value to write or read at addr */ -static inline void test_pattern(unsigned short int idx, +static void test_pattern(unsigned short int idx, unsigned long *addr, unsigned long *value) { uint8_t j, k; -- To view, visit https://review.coreboot.org/c/coreboot/+/34093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d57a3914c7ba0cbeea151d86e604843039730bc Gerrit-Change-Number: 34093 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add ability to begin romstage in DRAM
by Martin Roth (Code Review) 05 Jul '19

05 Jul '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Add ability to begin romstage in DRAM ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Jul 2019 17:43:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/commmon/itss: Add support to pass interrupt config to FSP
by Aamir Bohra (Code Review) 05 Jul '19

05 Jul '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/commmon/itss: Add support to pass interrupt config to FSP ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Jul 2019 13:10:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H
by Jeremy Soller (Code Review) 05 Jul '19

05 Jul '19

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33941 Change subject: src/soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H ...................................................................... src/soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H In order for GPEs to work properly, a number of the values used for GPIO_CFG and MISCCFG were not correct. This adjusts them in order to have GPE_EN set correctly, and thus enable GPEs, on the following GPIO blocks of PCH-H: GPP_E GPP_F GPP_H GPP_I GPP_J GPP_K GPD Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d --- M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33941/1 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index 5176ac7..16dd520 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -26,14 +26,14 @@ #define GPP_B 1 #define GPP_C 2 #define GPP_D 3 +#define GPP_E 6 +#define GPP_F 7 #define GPP_G 4 -#define GPP_K 5 -#define GPP_H 6 -#define GPP_E 7 -#define GPP_F 8 -#define GPP_I 9 -#define GPP_J 0xA -#define GPD 0xC +#define GPP_H 8 +#define GPP_I 0xA +#define GPP_J 0xB +#define GPP_K 9 +#define GPD 5 #define GPIO_NUM_GROUPS 12 #define GPIO_MAX_NUM_PER_GROUP 24 diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 67854d4..f990f6b 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -121,14 +121,14 @@ #define PMC_GPP_B 0x1 #define PMC_GPP_C 0x2 #define PMC_GPP_D 0x3 -#define PMC_GPP_E 0x7 -#define PMC_GPP_F 0x8 +#define PMC_GPP_E 0xA +#define PMC_GPP_F 0xB #define PMC_GPP_G 0x4 -#define PMC_GPP_H 0x6 -#define PMC_GPP_I 0x9 -#define PMC_GPP_J 0xA -#define PMC_GPP_K 0x5 -#define PMC_GPD 0xC +#define PMC_GPP_H 0x9 +#define PMC_GPP_I 0xC +#define PMC_GPP_J 0xD +#define PMC_GPP_K 0x8 +#define PMC_GPD 0x7 #else #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d Gerrit-Change-Number: 33941 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mainboard/lippert: Early SEMA watchdog disable
by Kyösti Mälkki (Code Review) 05 Jul '19

05 Jul '19

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/21318 ) Change subject: [WIP] mainboard/lippert: Early SEMA watchdog disable ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/21318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacc6a6baefcc91bdd4bbe7ce63da764ccfd59a86 Gerrit-Change-Number: 21318 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: test
by HAOUAS Elyes (Code Review) 05 Jul '19

05 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33672 Change subject: test ...................................................................... test Change-Id: I1eb58673e1737d91af8cf20a128bcaa58d690275 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M 3rdparty/chromeec M 3rdparty/fsp M 3rdparty/libgfxinit 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33672/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..860fe29 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d diff --git a/3rdparty/fsp b/3rdparty/fsp index 1d2b7e1..5996417 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 1d2b7e1a94c6a7c25a6fed1ac37caebf500f5f1a +Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index b3b9fa3..d49b56b 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit b3b9fa34bb99d33d0fc6a69c64966a71cebd5bd6 +Subproject commit d49b56baf97136e1b65f032a985291bf40a73260 -- To view, visit https://review.coreboot.org/c/coreboot/+/33672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1eb58673e1737d91af8cf20a128bcaa58d690275 Gerrit-Change-Number: 33672 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019