Change in coreboot[master]: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE w...
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34070 )
Change subject: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width ......................................................................
soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width
As per EDS Sata port implemented register is byte width (bits[3:0]) hence converting required DWORD based read/write to BYTE width read/write.
TEST=Able to boot from SATA device on CML hatch.
Change-Id: I545b823318bae461137d41a4490117eba7c87330 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34070/1
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 0801cb7..7dacc6e 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -43,14 +43,14 @@ static void sata_final(struct device *dev) { void *ahcibar = sata_get_ahci_bar(dev); - u32 port_impl, temp; + u8 port_impl, temp;
/* Set Bus Master */ temp = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
/* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); + port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) port_impl = ~port_impl; @@ -58,9 +58,9 @@ port_impl &= 0x07; /* bit 0-2 */
/* Port enable */ - temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); + temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS); temp |= port_impl; - pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); + pci_write_config8(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); }
static struct device_operations sata_ops = {
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34070 )
Change subject: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34070 )
Change subject: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34070/1/src/soc/intel/common/block/... File src/soc/intel/common/block/sata/sata.c:
https://review.coreboot.org/c/coreboot/+/34070/1/src/soc/intel/common/block/... PS1, Line 55: if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) Not the scope... but is a kconfig entry really required for this? Can't you decide this from combination of PCI IDs and revisions?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34070 )
Change subject: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width ......................................................................
Patch Set 1: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34070 )
Change subject: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34070/1/src/soc/intel/common/block/... File src/soc/intel/common/block/sata/sata.c:
https://review.coreboot.org/c/coreboot/+/34070/1/src/soc/intel/common/block/... PS1, Line 55: if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT))
Not the scope... […]
it can be done but then it won't be much different than current situation where except bunch of SPT PCI IDs, all other falls into SOC_AHCI_PORT_IMPLEMENTED_INVERT category. And it will continue in that way for coming PCH as well.
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34070 )
Change subject: soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width ......................................................................
soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width
As per EDS Sata port implemented register is byte width (bits[3:0]) hence converting required DWORD based read/write to BYTE width read/write.
TEST=Able to boot from SATA device on CML hatch.
Change-Id: I545b823318bae461137d41a4490117eba7c87330 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070 Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Aamir Bohra: Looks good to me, approved
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 0801cb7..7dacc6e 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -43,14 +43,14 @@ static void sata_final(struct device *dev) { void *ahcibar = sata_get_ahci_bar(dev); - u32 port_impl, temp; + u8 port_impl, temp;
/* Set Bus Master */ temp = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
/* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); + port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) port_impl = ~port_impl; @@ -58,9 +58,9 @@ port_impl &= 0x07; /* bit 0-2 */
/* Port enable */ - temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); + temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS); temp |= port_impl; - pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); + pci_write_config8(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); }
static struct device_operations sata_ops = {
-
Aamir Bohra (Code Review) -
Kyösti Mälkki (Code Review)
-
Paul Menzel (Code Review)
-
Subrata Banik (Code Review)