coreboot-gerrit July 2019

coreboot-gerrit@coreboot.org

1 participants
1550 discussions

Change in ...coreboot[master]: device/pci_rom.c: Fix indent for 'if' statement and remove unneeded '...
by HAOUAS Elyes (Code Review) 05 Jul '19

05 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33330 Change subject: device/pci_rom.c: Fix indent for 'if' statement and remove unneeded 'else' ...................................................................... device/pci_rom.c: Fix indent for 'if' statement and remove unneeded 'else' 'else' is not needed after a 'break' or 'return'. Change-Id: Ie9adb60323742d379cc4ad0af069a793b9ddd79b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_rom.c 1 file changed, 21 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33330/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 2dbfb51..f1f6c41 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -56,32 +56,31 @@ printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); } else if (!CONFIG(ON_DEVICE_ROM_LOAD)) { - printk(BIOS_DEBUG, "PCI Option ROM loading disabled " - "for %s\n", dev_path(dev)); + printk(BIOS_DEBUG, "PCI Option ROM loading disabled " + "for %s\n", dev_path(dev)); + return NULL; + } + uintptr_t rom_address; + + rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); + + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { +#if CONFIG(BOARD_EMULATION_QEMU_X86) + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) + rom_address = 0xc0000; + else +#endif return NULL; } else { - uintptr_t rom_address; - - rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); - - if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if CONFIG(BOARD_EMULATION_QEMU_X86) - if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) - rom_address = 0xc0000; - else -#endif - return NULL; - } else { - /* Enable expansion ROM address decoding. */ - pci_write_config32(dev, PCI_ROM_ADDRESS, - rom_address|PCI_ROM_ADDRESS_ENABLE); - } - - printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", - dev_path(dev), (unsigned long)rom_address); - rom_header = (struct rom_header *)rom_address; + /* Enable expansion ROM address decoding. */ + pci_write_config32(dev, PCI_ROM_ADDRESS, + rom_address|PCI_ROM_ADDRESS_ENABLE); } + printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", + dev_path(dev), (unsigned long)rom_address); + rom_header = (struct rom_header *)rom_address; + printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, " "INIT size 0x%04x, data ptr 0x%04x\n", le32_to_cpu(rom_header->signature), -- To view, visit https://review.coreboot.org/c/coreboot/+/33330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9adb60323742d379cc4ad0af069a793b9ddd79b Gerrit-Change-Number: 33330 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: console: Implement j specifier in vtxprintf()
by Jacob Garber (Code Review) 04 Jul '19

04 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34027 ) Change subject: console: Implement j specifier in vtxprintf() ...................................................................... console: Implement j specifier in vtxprintf() It is occasionally useful to print a uintmax_t or intmax_t, so add support for the j specifier. This also makes defining the PRI* macros in <inttypes.h> simpler. Change-Id: I656e3992029199b48e62a9df2d56f54c34e4e10f Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/console/vtxprintf.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/34027/1 diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 01091c8..94e370f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -18,6 +18,7 @@ #include <console/vtxprintf.h> #include <ctype.h> #include <string.h> +#include <stdint.h> #define call_tx(x) tx_byte(x, data) @@ -138,7 +139,7 @@ int field_width; /* width of output field */ int precision; /* min. # of digits for integers; max number of chars for from string */ - int qualifier; /* 'h', 'H', 'l', or 'L' for integer fields */ + int qualifier; /* 'h', 'H', 'l', 'L', 'z', or 'j' for integer fields */ int count; @@ -192,7 +193,7 @@ /* get the conversion qualifier */ qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z') { + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z' || *fmt == 'j') { qualifier = *fmt; ++fmt; if (*fmt == 'l') { @@ -293,6 +294,8 @@ num = va_arg(args, unsigned long); } else if (qualifier == 'z') { num = va_arg(args, size_t); + } else if (qualifier == 'j') { + num = va_arg(args, uintmax_t); } else if (qualifier == 'h') { num = (unsigned short) va_arg(args, int); if (flags & SIGN) -- To view, visit https://review.coreboot.org/c/coreboot/+/34027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I656e3992029199b48e62a9df2d56f54c34e4e10f Gerrit-Change-Number: 34027 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: console: Remove support for printing extra bases
by Jacob Garber (Code Review) 04 Jul '19

04 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34028 ) Change subject: console: Remove support for printing extra bases ...................................................................... console: Remove support for printing extra bases vtxprintf() can only print numbers in base 8, 10, and 16, so the extra letters in the alphabet aren't needed. Change-Id: I6a51c13f3298a597e801440f86bf698bdd8c736a Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/console/vtxprintf.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34028/1 diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 01091c8..2d4953d 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -38,7 +38,7 @@ void *data) { char c, sign, tmp[66]; - const char *digits = "0123456789abcdefghijklmnopqrstuvwxyz"; + const char *digits = "0123456789abcdef"; int i; int count = 0; #ifdef SUPPORT_64BIT_INTS @@ -57,11 +57,9 @@ #endif if (type & LARGE) - digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + digits = "0123456789ABCDEF"; if (type & LEFT) type &= ~ZEROPAD; - if (base < 2 || base > 36) - return 0; c = (type & ZEROPAD) ? '0' : ' '; sign = 0; if (type & SIGN) { -- To view, visit https://review.coreboot.org/c/coreboot/+/34028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a51c13f3298a597e801440f86bf698bdd8c736a Gerrit-Change-Number: 34028 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: include: Add stdbool.h
by Jacob Garber (Code Review) 04 Jul '19

04 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34074 ) Change subject: include: Add stdbool.h ...................................................................... include: Add stdbool.h Change-Id: I8d24c266ae23c50ced5a92b0192a49b179c669a4 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- A src/include/stdbool.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/34074/1 diff --git a/src/include/stdbool.h b/src/include/stdbool.h new file mode 100644 index 0000000..b10e878 --- /dev/null +++ b/src/include/stdbool.h @@ -0,0 +1,8 @@ +#ifndef STDBOOL_H +#define STDBOOL_H + +#define bool _Bool +#define true 1 +#define false 0 + +#endif /* STDBOOL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d24c266ae23c50ced5a92b0192a49b179c669a4 Gerrit-Change-Number: 34074 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: mb/google/hatch/variants/helios: Update GPIO table for proto stage
by Furquan Shaikh (Code Review) 04 Jul '19

04 Jul '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33826 ) Change subject: mb/google/hatch/variants/helios: Update GPIO table for proto stage ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/c/coreboot/+/33826/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33826/3//COMMIT_MSG@12 PS3, Line 12: BRANCH=Master not required for master branch. https://review.coreboot.org/c/coreboot/+/33826/3/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/gpio.c: https://review.coreboot.org/c/coreboot/+/33826/3/src/mainboard/google/hatch… PS3, Line 42: /* C11 : GPP_C11 ==> EN_PP3300_PP1800_FP */ : PAD_CFG_GPO(GPP_C11, 0, DEEP), This is already done in baseboard/gpio.c for hatch, right? https://review.coreboot.org/c/coreboot/+/33826/3/src/mainboard/google/hatch… PS3, Line 56: /* D9 : GPP_D9 ==> EN_PP3300_TOUCHSCREEN_DX */ : PAD_CFG_GPO(GPP_D9, 0, DEEP), This is being added to baseboard here: https://review.coreboot.org/c/coreboot/+/33808/4/src/mainboard/google/hatch… https://review.coreboot.org/c/coreboot/+/33826/3/src/mainboard/google/hatch… PS3, Line 101: 1 Shouldn't this be done as part of ACPI to ensure timing requirements are met? -- To view, visit https://review.coreboot.org/c/coreboot/+/33826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I257a90a97e11651cdf5f85ca743e530ef5e61e56 Gerrit-Change-Number: 33826 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jul 2019 18:00:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Furquan Shaikh (Code Review) 04 Jul '19

04 Jul '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > (1 comment) > > Correct the CL link . > https://review.coreboot.org/c/coreboot/+/33820 That change affects the overridetree for hatch only. You still need to update override tree for helios here. -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jul 2019 16:34:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/common: Increase SMM_MODULE_STACK stack to 0x800
by Kane Chen (Code Review) 04 Jul '19

04 Jul '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33999 Change subject: soc/intel/common: Increase SMM_MODULE_STACK stack to 0x800 ...................................................................... soc/intel/common: Increase SMM_MODULE_STACK stack to 0x800 While running the s0ix cycling test, we observed SMM Handler caused a stack overflow. This error happens during event log access. This change is to increase the SMM_MODULE_STACK size to 0x800 BUG=b:135551854 TEST=suspend_resume test pass 500+ cycles, originally issue happenes within 150 cycle Change-Id: Ib4686b4d2d4fc3976068779314f4ee15ef4a8ae2 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/common/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/33999/1 diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index ac22686..523d1f5 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -68,4 +68,8 @@ Set this option to enable default debug interface of SoC such as DBC or DCI. +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + endif # SOC_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/33999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4686b4d2d4fc3976068779314f4ee15ef4a8ae2 Gerrit-Change-Number: 33999 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by Frans Hendriks (Code Review) 04 Jul '19

04 Jul '19

Hello Patrick Rudolph, Felix Held, Piotr Król, David Hendricks, Paul Menzel, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29470 to look at the new patch set (#16). Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... mainboard/portwell/m107: Do initial mainboard commit Initial support for Portwell PQ7-M107 (Q7) module. Code based on Intel Strago mainboard. BUG=N/A TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/portwell/pq7-m107.md A src/mainboard/portwell/Kconfig A src/mainboard/portwell/Kconfig.name A src/mainboard/portwell/m107/Kconfig A src/mainboard/portwell/m107/Kconfig.name A src/mainboard/portwell/m107/Makefile.inc A src/mainboard/portwell/m107/acpi/ec.asl A src/mainboard/portwell/m107/acpi/mainboard.asl A src/mainboard/portwell/m107/acpi/sleepstates.asl A src/mainboard/portwell/m107/acpi/superio.asl A src/mainboard/portwell/m107/acpi_tables.c A src/mainboard/portwell/m107/board_info.txt A src/mainboard/portwell/m107/cmos.layout A src/mainboard/portwell/m107/com_init.c A src/mainboard/portwell/m107/devicetree.cb A src/mainboard/portwell/m107/dsdt.asl A src/mainboard/portwell/m107/fadt.c A src/mainboard/portwell/m107/gpio.c A src/mainboard/portwell/m107/hda_verb.c A src/mainboard/portwell/m107/irqroute.c A src/mainboard/portwell/m107/irqroute.h A src/mainboard/portwell/m107/mainboard.c A src/mainboard/portwell/m107/onboard.h A src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/portwell/m107/w25q64.c 28 files changed, 1,830 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29470/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 16 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/intel/icelake: Enable Audio FSP UPD based on devicetree HDA presence
by Subrata Banik (Code Review) 04 Jul '19

04 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33933 Change subject: soc/intel/icelake: Enable Audio FSP UPD based on devicetree HDA presence ...................................................................... soc/intel/icelake: Enable Audio FSP UPD based on devicetree HDA presence Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33933/1 diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 3c49fee..3179d1a 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -25,7 +25,7 @@ const struct soc_intel_icelake_config *config) { unsigned int i; - const struct device *dev = pcidev_on_root(0, 0); + const struct device *dev; uint32_t mask = 0; /* Set IGD stolen size to 60MB. */ @@ -36,6 +36,7 @@ m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; m_cfg->SkipMbpHob = 1; + dev = pcidev_on_root(0x1f, 3); /* If Audio Codec is enabled, enable FSP UPD */ if (!dev) m_cfg->PchHdaEnable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48 Gerrit-Change-Number: 33933 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: src/lib/romstage_stack: Remove unused 'define ROMSTAGE_RAM_STACK_SIZE'
by HAOUAS Elyes (Code Review) 04 Jul '19

04 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34068 ) Change subject: src/lib/romstage_stack: Remove unused 'define ROMSTAGE_RAM_STACK_SIZE' ...................................................................... src/lib/romstage_stack: Remove unused 'define ROMSTAGE_RAM_STACK_SIZE' Change-Id: I0f263132724b1cef03f708563e3c05951dbe8a19 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/romstage_stack.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/34068/1 diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c index 4fe1459..acc1405 100644 --- a/src/lib/romstage_stack.c +++ b/src/lib/romstage_stack.c @@ -21,7 +21,6 @@ * Romstage needs quite a bit of stack for decompressing images since the lzma * lib keeps its state on the stack during romstage. */ -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 uintptr_t romstage_ram_stack_base(size_t size, int src) { -- To view, visit https://review.coreboot.org/c/coreboot/+/34068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f263132724b1cef03f708563e3c05951dbe8a19 Gerrit-Change-Number: 34068 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2019