coreboot-gerrit July 2019

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Change in coreboot[master]: soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param
by Furquan Shaikh (Code Review) 07 Jul '19

07 Jul '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34117 ) Change subject: soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param ...................................................................... soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/sarien/chromeos.c M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/cannonlake/pmc.c 3 files changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/34117/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index fafc469..7aaf401 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -122,6 +122,6 @@ { #if ENV_RAMSTAGE /* Ensure system powers up after CR50 reset */ - pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON); + pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); #endif } diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index e0d2614..252c719 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -171,7 +171,6 @@ #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 -struct device; -void pmc_set_afterg3(struct device *dev, int s5pwr); +void pmc_set_afterg3(int s5pwr); #endif diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 0b23568..8eb81b0 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -32,7 +32,7 @@ * Set which power state system will be after reapplying * the power (from G3 State) */ -void pmc_set_afterg3(struct device *dev, int s5pwr) +void pmc_set_afterg3(int s5pwr) { uint8_t reg8; uint8_t *pmcbase = pmc_mmio_regs(); @@ -60,7 +60,7 @@ */ void pmc_soc_restore_power_failure(void) { - pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE); } static void pm1_enable_pwrbtn_smi(void *unused) @@ -119,7 +119,7 @@ write32(pmcbase + DSX_CFG, reg); } -static void pch_power_options(struct device *dev) +static void pch_power_options(void) { const char *state; @@ -144,7 +144,7 @@ default: state = "undefined"; } - pmc_set_afterg3(dev, pwr_on); + pmc_set_afterg3(pwr_on); printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ @@ -159,7 +159,7 @@ rtc_init(); /* Initialize power management */ - pch_power_options(dev); + pch_power_options(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); -- To view, visit https://review.coreboot.org/c/coreboot/+/34117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1 Gerrit-Change-Number: 34117 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/non-x86: Flip HAVE_MONOTONIC_TIMER default
by Kyösti Mälkki (Code Review) 07 Jul '19

07 Jul '19

Hello ron minnich, Julius Werner, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34112 to look at the new patch set (#2). Change subject: arch/non-x86: Flip HAVE_MONOTONIC_TIMER default ...................................................................... arch/non-x86: Flip HAVE_MONOTONIC_TIMER default Also Enables qualcomm/ipq_806x monotonic timer. Change-Id: I9dfa9b92dc63375465e3bb87b73eeefad601c810 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/cpu/allwinner/a10/Kconfig M src/cpu/allwinner/a10/Makefile.inc D src/cpu/allwinner/a10/monotonic_timer.c M src/cpu/qemu-power8/Kconfig M src/cpu/ti/am335x/Kconfig M src/mainboard/emulation/qemu-armv7/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/imgtec/pistachio/Kconfig M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8183/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq806x/Kconfig M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/Kconfig M src/soc/samsung/exynos5250/Kconfig M src/soc/samsung/exynos5420/Kconfig M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 23 files changed, 17 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/34112/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfa9b92dc63375465e3bb87b73eeefad601c810 Gerrit-Change-Number: 34112 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: include/cpu/x86/mtrr: Fix return type
by HAOUAS Elyes (Code Review) 07 Jul '19

07 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33817 Change subject: include/cpu/x86/mtrr: Fix return type ...................................................................... include/cpu/x86/mtrr: Fix return type Change-Id: Ia328e1e5a79c2e7606961bb1b68c01db6b77da21 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/x86/mtrr.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/33817/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 49ed462..29256c8 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -120,7 +120,7 @@ /* fms: find most significant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { - int r; + unsigned int r; __asm__("bsrl %1,%0\n\t" "jnz 1f\n\t" @@ -132,7 +132,7 @@ /* fls: find least significant bit set */ static inline unsigned int fls(unsigned int x) { - int r; + unsigned int r; __asm__("bsfl %1,%0\n\t" "jnz 1f\n\t" -- To view, visit https://review.coreboot.org/c/coreboot/+/33817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia328e1e5a79c2e7606961bb1b68c01db6b77da21 Gerrit-Change-Number: 33817 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t60: Align ACPI C-state across the similar boards
by Nico Huber (Code Review) 07 Jul '19

07 Jul '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29160 ) Change subject: mb/lenovo/t60: Align ACPI C-state across the similar boards ...................................................................... mb/lenovo/t60: Align ACPI C-state across the similar boards We have 3 similar Lenovo mainboards - x60 (oldest), t60, and z61t (most recent addition). The only one with two consequent 2s as the C-types is t60: static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; It seems that 3 could be a better choice for the last line here. UNTESTED on a real hardware. Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29160 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t60/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index b78d862..5f59946 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -31,7 +31,7 @@ static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, - { 2, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, + { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, }; int get_cst_entries(acpi_cstate_t **entries) -- To view, visit https://review.coreboot.org/c/coreboot/+/29160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90 Gerrit-Change-Number: 29160 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/lenovo/t60: Align ACPI C-state across the similar boards
by Nico Huber (Code Review) 07 Jul '19

07 Jul '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29160 ) Change subject: mb/lenovo/t60: Align ACPI C-state across the similar boards ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90 Gerrit-Change-Number: 29160 Gerrit-PatchSet: 4 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 07 Jul 2019 00:15:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Angel Pons (Code Review) 07 Jul '19

07 Jul '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > The ACPI problems were caused by `get_cores_per_package()` function. It was using CPUID 0Bh function, that returns number of logical processes of requested level to EBX. According to Intel's manual, this value is not changed if HT was disabled. > > > > int totalcores = dev_count_cpu(); // this was 2 > > int cores_per_package = get_cores_per_package(); // this was 4, when it had to be 2 > > int numcpus = totalcores/cores_per_package; // so this was 0 > > > > I updated the `get_cores_per_package` function, now it uses MSR 0x35 instead of CPUID. I hope that doesn't break anything. > > > > AFAIK, 206ax only supports uni-processor systems anyway. I think we can > simply drop the `numcpus` loop. Server/workstation/enthusiast platforms for sandy (LGA2011) seem to use CPUs with CPUID 206dx. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Sat, 06 Jul 2019 22:49:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Nico Huber (Code Review) 07 Jul '19

07 Jul '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 4: > Patch Set 4: > > The ACPI problems were caused by `get_cores_per_package()` function. It was using CPUID 0Bh function, that returns number of logical processes of requested level to EBX. According to Intel's manual, this value is not changed if HT was disabled. > > int totalcores = dev_count_cpu(); // this was 2 > int cores_per_package = get_cores_per_package(); // this was 4, when it had to be 2 > int numcpus = totalcores/cores_per_package; // so this was 0 > > I updated the `get_cores_per_package` function, now it uses MSR 0x35 instead of CPUID. I hope that doesn't break anything. > AFAIK, 206ax only supports uni-processor systems anyway. I think we can simply drop the `numcpus` loop. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Sat, 06 Jul 2019 22:35:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/icelake: Fix outb order
by Lance Zhao (Code Review) 06 Jul '19

06 Jul '19

Hello Lijian Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33960 to review the following change. Change subject: soc/intel/icelake: Fix outb order ...................................................................... soc/intel/icelake: Fix outb order Similar to CB:33940, fix outb orders. Change-Id: I1d35235abc7e02e6058f07809b738635861cc9e4 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/icelake/espi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/33960/1 diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 9ca0c7c..8ab909d 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -194,10 +194,10 @@ /* Setup NMI on errors, disable SERR */ reg8 = (inb(0x61)) & 0xf0; - outb(0x61, (reg8 | (1 << 2))); + outb((reg8 | (1 << 2)), 0x61); /* Disable NMI sources */ - outb(0x70, (1 << 7)); + outb((1 << 7), 0x70); }; static void clock_gate_8254(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/33960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d35235abc7e02e6058f07809b738635861cc9e4 Gerrit-Change-Number: 33960 Gerrit-PatchSet: 1 Gerrit-Owner: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Remove all AGESA references
by Marshall Dawson (Code Review) 06 Jul '19

06 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33755 Change subject: soc/amd/picasso: Remove all AGESA references ...................................................................... soc/amd/picasso: Remove all AGESA references Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove all source, support functions, and comments related to AGESA. Family 17h requires v9 which has no similarities to v5 for integration into a host firmware. AGESA v9 support will be added via subsequent patches into the appropriate locations. Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/northbridge.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/southbridge.c 9 files changed, 11 insertions(+), 277 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33755/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 33aae26..a930f60 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,8 +49,6 @@ select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -106,18 +104,6 @@ int default 48 -config BOTTOMIO_POSITION - hex "Bottom of 32-bit IO space" - default 0xD0000000 - help - If PCI peripherals with big BARs are connected to the system - the bottom of the IO must be decreased to allocate such - devices. - - Declare the beginning of the 128MB-aligned MMIO region. This - option is useful when PCI peripherals requesting large address - ranges are present. - config MMCONF_BASE_ADDRESS hex default 0xF8000000 @@ -199,7 +185,7 @@ bool "System is legacy free" help Select y if there is no keyboard controller in the system. - This sets variables in AGESA and ACPI. + This sets a variable in ACPI. config SERIRQ_CONTINUOUS_MODE bool @@ -213,7 +199,6 @@ default 0x400 help Base address for the ACPI registers. - This value must match the hardcoded value of AGESA. config PICASSO_UART bool "UART controller on Picasso" diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 6dc47cd..249be98 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -25,9 +25,6 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> - #include "chip.h" /* Supplied by i2c.c */ @@ -152,19 +149,3 @@ .init = soc_init, .final = soc_final }; - -static void earliest_ramstage(void *unused) -{ - int s3_resume = acpi_s3_resume_allowed() && - romstage_handoff_is_resume(); - if (!s3_resume) { - post_code(0x47); - do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); - } else { - /* Complete the initial system restoration */ - post_code(0x46); - do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); - } -} - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ff9c845..39c7026 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -23,33 +23,9 @@ #include <soc/i2c.h> #include <arch/acpi_device.h> -#define MAX_NODES 1 -#define MAX_DRAM_CH 1 -#define MAX_DIMMS_PER_CH 2 - #define PICASSO_I2C_DEV_MAX 4 struct soc_amd_picasso_config { - u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; - enum { - DRAM_CONTENTS_KEEP, - DRAM_CONTENTS_CLEAR - } dram_clear_on_reset; - - enum { - /* Do not enable UMA in the system. */ - UMAMODE_NONE, - /* Enable UMA with a specific size. */ - UMAMODE_SPECIFIED_SIZE, - /* Let AGESA determine the proper size. Non-legacy requires - * the resolution to be specified PLATFORM_CONFIGURATION */ - UMAMODE_AUTO_LEGACY, - UMAMODE_AUTO_NON_LEGACY, - } uma_mode; - - /* Used if UMAMODE_SPECIFIED_SIZE is set. */ - size_t uma_size; - /* * If sb_reset_i2c_slaves() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. @@ -60,18 +36,6 @@ */ u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; - u8 stapm_percent; - u32 stapm_time_ms; - u32 stapm_power_mw; - /* - * This specifies the LVDS/eDP power-up sequence time for the delay - * between VaryBL and BLON. - * 0 - Use the VBIOS default (default). The video BIOS default is 32ms. - * n - Values other than zero specify a setting of (4 * n) milliseconds - * time delay. - */ - u8 lvds_poseq_varybl_to_blon; - u8 lvds_poseq_blon_to_varybl; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7d47645..7bc1810 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,16 +18,8 @@ #include <device/device.h> -/* - * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest - * numbered registers. Any values defined below are subtracted from the - * highest numbered registers. - * - * todo: Revisit this once AGESA no longer programs MTRRs. - */ #define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_CAR_HEAP 2 -#define SOC_EARLY_VMTRR_TEMPRAM 3 +#define SOC_EARLY_VMTRR_TEMPRAM 2 void picasso_init_cpus(struct device *dev); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index f7df277..65705b9 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -110,6 +110,8 @@ SMM_SUBREGION_NUM, }; +void amd_initcpuio(void); + /* * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 9e2b901..6733946 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -326,7 +326,7 @@ void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** - * @brief Save the UMA bize returned by AGESA + * @brief Save the UMA bize * * @param size = in bytes * @@ -334,7 +334,7 @@ */ void save_uma_size(uint32_t size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Save the UMA base address * * @param base = 64bit base address * diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 5985832..cace626 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -27,9 +27,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <romstage_handoff.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> -#include <agesa_headers.h> #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -188,6 +185,7 @@ return current; } +#if 0 /* TODO - different mechanism to collect this info for Family 17h */ static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -207,6 +205,7 @@ return (unsigned long)current; } +#endif static void northbridge_fill_ssdt_generator(struct device *device) { @@ -233,6 +232,7 @@ unsigned long current, acpi_rsdp_t *rsdp) { +#if 0 /* TODO - different mechanism to collect this info for Family 17h */ acpi_srat_t *srat; acpi_slit_t *slit; acpi_header_t *ssdt; @@ -333,6 +333,7 @@ acpi_add_table(rsdp, ssdt); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); +#endif return current; } @@ -401,9 +402,7 @@ void domain_enable_resources(struct device *dev) { - /* Must be called after PCI enumeration and resource allocation */ - if (!romstage_handoff_is_resume()) - do_agesawrapper(AMD_INIT_MID, "amdinitmid"); + /* TODO: placeholder for FSP call */ } void domain_set_resources(struct device *dev) @@ -474,19 +473,3 @@ return new_vendev; } - -__weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } - -void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) -{ - const struct device *dev = SOC_IOMMU_DEV; - params->IommuSupport = dev && dev->enabled; - set_board_env_params(params); -} - -void SetNbMidParams(GNB_MID_CONFIGURATION *params) -{ - /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ - params->iGpuVgaMode = 0; - params->GnbIoapicAddress = IO_APIC2_ADDR; -} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 904f556..950b41f 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -27,8 +27,6 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <elog.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/southbridge.h> @@ -40,22 +38,6 @@ /* By default, don't do anything */ } -static void agesa_call(void) -{ - post_code(0x37); - do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - - post_code(0x38); - /* APs will not exit amdinitearly */ - do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); -} - -static void bsp_agesa_call(void) -{ - set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ - agesa_call(); -} - asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -63,58 +45,20 @@ void *smm_base; size_t smm_size; uintptr_t tseg_base; - msr_t base, mask; - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); - int i; console_init(); mainboard_romstage_entry(s3_resume); - bsp_agesa_call(); - if (!s3_resume) { post_code(0x40); - do_agesawrapper(AMD_INIT_POST, "amdinitpost"); - post_code(0x41); - /* - * TODO: This is a hack to work around current AGESA behavior. - * AGESA needs to change to reflect that coreboot owns - * the MTRRs. - * - * After setting up DRAM, AGESA also completes the configuration - * of the MTRRs, setting regions to WB. Anything written to - * memory between now and and when CAR is dismantled will be - * in cache and lost. For now, set the regions UC to ensure - * the writes get to DRAM. - */ - for (i = 0 ; i < vmtrrs ; i++) { - base = rdmsr(MTRR_PHYS_BASE(i)); - mask = rdmsr(MTRR_PHYS_MASK(i)); - if (!(mask.lo & MTRR_PHYS_MASK_VALID)) - continue; - - if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { - base.lo &= ~0x7; - base.lo |= MTRR_TYPE_UNCACHEABLE; - wrmsr(MTRR_PHYS_BASE(i), base); - } - } - /* Disable WB from to region 4GB-TOM2. */ - msr_t sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; - wrmsr(SYSCFG_MSR, sys_cfg); if (CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); - - post_code(0x61); } post_code(0x43); @@ -155,64 +99,3 @@ post_code(0x50); /* Should never see this post code. */ } - -void SetMemParams(AMD_POST_PARAMS *PostParams) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); - /* In case of a BIOS error, only attempt to set UMA. */ - PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? - UMA_AUTO : UMA_NONE; - return; - } - - cfg = dev->chip_info; - - PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; - - switch (cfg->uma_mode) { - case UMAMODE_NONE: - PostParams->MemConfig.UmaMode = UMA_NONE; - break; - case UMAMODE_SPECIFIED_SIZE: - PostParams->MemConfig.UmaMode = UMA_SPECIFIED; - /* 64 KiB blocks. */ - PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); - break; - case UMAMODE_AUTO_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_LEGACY; - break; - case UMAMODE_AUTO_NON_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; - break; - } -} - -void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - struct _PLATFORM_CONFIGURATION *platform; - - if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" - " config, STAPM unchanged\n"); - return; - } - cfg = dev->chip_info; - platform = &InitEarly->PlatformConfig; - if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && - (cfg->stapm_power_mw)) { - platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; - platform->PlatStapmConfig.CfgStapmTimeConstant = - cfg->stapm_time_ms; - platform->PkgPwrLimitDC = cfg->stapm_power_mw; - platform->PkgPwrLimitAC = cfg->stapm_power_mw; - platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; - } -} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index dca3591..d0e12a9 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <amdblocks/amd_pci_util.h> -#include <amdblocks/agesawrapper.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> @@ -34,7 +33,6 @@ #include <soc/amd_pci_int_defs.h> #include <delay.h> #include <soc/pci_devs.h> -#include <agesa_headers.h> #include <soc/nvs.h> #include <types.h> @@ -54,60 +52,6 @@ { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } }; -static int is_sata_config(void) -{ - return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE) - || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE)); -} - -static inline int sb_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataAhci == CONFIG_PICASSO_SATA_MODE); -} - -static inline int sb_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataLegacyIde == CONFIG_PICASSO_SATA_MODE); -} - -void SetFchResetParams(FCH_RESET_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - if (dev && dev->enabled) { - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - } -} - -void SetFchEnvParams(FCH_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->AzaliaController = AzEnable; - params->SataClass = CONFIG_PICASSO_SATA_MODE; - if (dev && dev->enabled) { - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE == - SataLegacyIde); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - params->SataIdeMode = FALSE; - } -} - -void SetFchMidParams(FCH_INTERFACE *params) -{ - SetFchEnvParams(params); -} - /* * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME * provides a visible association with the index, therefore helping -- To view, visit https://review.coreboot.org/c/coreboot/+/33755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Gerrit-Change-Number: 33755 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Enable RTC eosc calibration feature to save power
by Ran Bi (Code Review) 06 Jul '19

06 Jul '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32339 Change subject: mediatek/mt8183: Enable RTC eosc calibration feature to save power ...................................................................... mediatek/mt8183: Enable RTC eosc calibration feature to save power When system shutdown, RTC enable eosc calibration feature to save power. Then coreboot RTC driver need to call rtc_enable_dcxo function at every boot up to switch RTC clock source to a more accurate one. BUG=b:128467245 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/soc/mediatek/mt8183/rtc.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/32339/1 diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..ba05f86 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -197,12 +197,6 @@ goto err; } - /* using dcxo 32K clock */ - if (!rtc_enable_dcxo()) { - ret = -RTC_STATUS_OSC_SETTING_FAIL; - goto err; - } - if (recover) mdelay(20); @@ -311,6 +305,10 @@ pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + /* using dcxo 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() fail\n"); + rtc_boot_common(); rtc_bbpu_power_on(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Gerrit-Change-Number: 32339 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019