coreboot-gerrit July 2019

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Change in coreboot[master]: device/pci_ops: Define pci_find_capability() just once
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31755 ) Change subject: device/pci_ops: Define pci_find_capability() just once ...................................................................... device/pci_ops: Define pci_find_capability() just once Wrap the simple romstage implementation to be called from ramstage. Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/pci_device.c M src/device/pci_early.c M src/device/pci_ops.c M src/drivers/usb/pci_ehci.c M src/include/device/pci.h M src/include/device/pci_ops.h M src/soc/cavium/common/ecam.c 7 files changed, 94 insertions(+), 133 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 31c35dc..a2af0ec 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -102,73 +102,6 @@ } /** - * Given a device, a capability type, and a last position, return the next - * matching capability. Always start at the head of the list. - * - * @param dev Pointer to the device structure. - * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. - * @param last Location of the PCI capability register to start from. - * @return The next matching capability. - */ -unsigned pci_find_next_capability(struct device *dev, unsigned cap, - unsigned last) -{ - unsigned pos = 0; - u16 status; - unsigned reps = 48; - - status = pci_read_config16(dev, PCI_STATUS); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - switch (dev->hdr_type & 0x7f) { - case PCI_HEADER_TYPE_NORMAL: - case PCI_HEADER_TYPE_BRIDGE: - pos = PCI_CAPABILITY_LIST; - break; - case PCI_HEADER_TYPE_CARDBUS: - pos = PCI_CB_CAPABILITY_LIST; - break; - default: - return 0; - } - - pos = pci_read_config8(dev, pos); - while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ - int this_cap; - - pos &= ~3; - this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); - printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", - this_cap, pos); - if (this_cap == 0xff) - break; - - if (!last && (this_cap == cap)) - return pos; - - if (last == pos) - last = 0; - - pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); - } - return 0; -} - -/** - * Given a device, and a capability type, return the next matching - * capability. Always start at the head of the list. - * - * @param dev Pointer to the device structure. - * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. - * @return The next matching capability. - */ -unsigned int pci_find_capability(struct device *dev, unsigned int cap) -{ - return pci_find_next_capability(dev, cap, 0); -} - -/** * Given a device and register, read the size of the BAR for that register. * * @param dev Pointer to the device structure. diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 5a1fb22..7c9ea00 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -21,54 +21,6 @@ #include <device/pci_type.h> #include <delay.h> -unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) -{ - unsigned pos = 0; - u16 status; - unsigned reps = 48; - - status = pci_read_config16(dev, PCI_STATUS); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - u8 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - switch (hdr_type & 0x7f) { - case PCI_HEADER_TYPE_NORMAL: - case PCI_HEADER_TYPE_BRIDGE: - pos = PCI_CAPABILITY_LIST; - break; - case PCI_HEADER_TYPE_CARDBUS: - pos = PCI_CB_CAPABILITY_LIST; - break; - default: - return 0; - } - - pos = pci_read_config8(dev, pos); - while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ - int this_cap; - - pos &= ~3; - this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); - if (this_cap == 0xff) - break; - - if (!last && (this_cap == cap)) - return pos; - - if (last == pos) - last = 0; - - pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); - } - return 0; -} - -unsigned pci_find_capability(pci_devfn_t dev, unsigned cap) -{ - return pci_find_next_capability(dev, cap, 0); -} - static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) { u16 reg16; diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 34f9d1e..9613315 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -11,6 +11,77 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <stdint.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS; + +/** + * Given a device, a capability type, and a last position, return the next + * matching capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @param last Location of the PCI capability register to start from. + * @return The next matching capability. + */ +u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last) +{ + u16 pos = 0; + u16 status; + int reps = 48; + + status = pci_s_read_config16(dev, PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + u8 hdr_type = pci_s_read_config8(dev, PCI_HEADER_TYPE); + switch (hdr_type & 0x7f) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + pos = PCI_CAPABILITY_LIST; + break; + case PCI_HEADER_TYPE_CARDBUS: + pos = PCI_CB_CAPABILITY_LIST; + break; + default: + return 0; + } + + pos = pci_s_read_config8(dev, pos); + while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ + int this_cap; + + pos &= ~3; + this_cap = pci_s_read_config8(dev, pos + PCI_CAP_LIST_ID); + if (this_cap == 0xff) + break; + + if (!last && (this_cap == cap)) + return pos; + + if (last == pos) + last = 0; + + pos = pci_s_read_config8(dev, pos + PCI_CAP_LIST_NEXT); + } + return 0; +} + +/** + * Given a device, and a capability type, return the next matching + * capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @return The next matching capability. + */ +u16 pci_s_find_capability(pci_devfn_t dev, u16 cap) +{ + return pci_s_find_next_capability(dev, cap, 0); +} diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 5621b37..34684cb 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -49,7 +49,7 @@ if (class != PCI_EHCI_CLASSCODE) return -1; - u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + u8 pm_cap = pci_s_find_capability(dbg_dev, PCI_CAP_ID_PM); if (pm_cap) { u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); /* Set to D0 and disable PM events. */ @@ -58,7 +58,7 @@ pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); } - u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); + u8 pos = pci_s_find_capability(dbg_dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f1de7bf..5f72b55 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -125,16 +125,6 @@ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); -#ifdef __SIMPLE_DEVICE__ -unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap, - unsigned int last); -unsigned int pci_find_capability(pci_devfn_t dev, unsigned int cap); -#else /* !__SIMPLE_DEVICE__ */ -unsigned int pci_find_next_capability(struct device *dev, unsigned int cap, - unsigned int last); -unsigned int pci_find_capability(struct device *dev, unsigned int cap); -#endif /* __SIMPLE_DEVICE__ */ - void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 454795f..9a9c575 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -175,4 +175,21 @@ pci_write_config32(dev, reg, reg32); } +u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); +u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); + +#ifndef __SIMPLE_DEVICE__ +static __always_inline +u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) +{ + return pci_s_find_next_capability(PCI_BDF(dev), cap, last); +} + +static __always_inline +u16 pci_find_capability(const struct device *dev, u16 cap) +{ + return pci_s_find_capability(PCI_BDF(dev), cap); +} +#endif + #endif /* PCI_OPS_H */ diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index ae2a91f..89c69db 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -17,6 +17,8 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ +#define __SIMPLE_DEVICE__ + #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/pci.h> @@ -27,15 +29,11 @@ * Get PCI BAR address from cavium specific extended capability. * Use regular BAR if not found in extended capability space. * - * @return The pyhsical address of the BAR, zero on error + * @return The physical address of the BAR, zero on error */ -#ifdef __SIMPLE_DEVICE__ uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar) -#else -uint64_t ecam0_get_bar_val(struct device *dev, u8 bar) -#endif { - size_t cap_offset = pci_find_capability(dev, 0x14); + size_t cap_offset = pci_s_find_capability(dev, 0x14); uint64_t h, l, ret = 0; if (cap_offset) { /* Found EA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Gerrit-Change-Number: 31755 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: pcengines/apuX: Replace use of dev_find_slot()
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34003 Change subject: pcengines/apuX: Replace use of dev_find_slot() ...................................................................... pcengines/apuX: Replace use of dev_find_slot() Find the NIC device based on the PCIe root port function. Change-Id: Ia8c6e115c9b836ee60862427dfc9d46ca3dd1b69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/mainboard.c 2 files changed, 16 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34003/1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index e5e30e0..088c839 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -206,17 +206,23 @@ const char *smbios_mainboard_serial_number(void) { static char serial[10]; - struct device *nic_dev; + struct device *dev; uintptr_t bar18; u32 mac_addr = 0; int i; - nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0)); - if ((serial[0] != 0) || !nic_dev) + /* Already initialized. */ + if (serial[0] != 0) + return serial; + + dev = pcidev_on_root(4, 0); + if (dev) + dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); + if (!dev) return serial; /* Read in the last 3 bytes of NIC's MAC address. */ - bar18 = pci_read_config32(nic_dev, 0x18); + bar18 = pci_read_config32(dev, 0x18); bar18 &= 0xFFFFFC00; for (i = 3; i < 6; i++) { mac_addr <<= 8; diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 5a19d20..7dff6b9 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -197,9 +197,12 @@ struct device *dev; uintptr_t bar10; u32 mac_addr = 0; - u32 bus_no; int i; + /* Already initialized. */ + if (serial[0] != 0) + return serial; + /* * In case we have PCIe module connected to mPCIe2 slot, BDF 1:0.0 may * not be a NIC, because mPCIe2 slot is routed to the very first PCIe @@ -208,11 +211,8 @@ * connected. */ dev = pcidev_on_root(2, 2); - if ((serial[0] != 0) || !dev) - return serial; - - bus_no = dev->link_list->secondary; - dev = dev_find_slot(bus_no, PCI_DEVFN(0, 0)); + if (dev) + dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); if (!dev) return serial; -- To view, visit https://review.coreboot.org/c/coreboot/+/34003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8c6e115c9b836ee60862427dfc9d46ca3dd1b69 Gerrit-Change-Number: 34003 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: qcs405: Add bl31 stage and elf
by Patrick Georgi (Code Review) 04 Jul '19

04 Jul '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 31: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 31 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jul 2019 09:04:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: Use correct bitwise operator
by Jacob Garber (Code Review) 04 Jul '19

04 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33963 Change subject: sb/intel/common: Use correct bitwise operator ...................................................................... sb/intel/common: Use correct bitwise operator Like the line above it, this should be & instead of | (otherwise it will always incorrectly return true). Change-Id: I5208b523c815d15d7263594f06ccfacd8a9510b1 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1402092 --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33963/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index e8c8f01..e9e66dc 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -338,7 +338,7 @@ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN); } else { - return !!(readw_(&cntlr->ich9_spi->hsfs) | HSFS_FLOCKDN); + return !!(readw_(&cntlr->ich9_spi->hsfs) & HSFS_FLOCKDN); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5208b523c815d15d7263594f06ccfacd8a9510b1 Gerrit-Change-Number: 33963 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lib/romstage_stack.c: Remove unused function
by Arthur Heymans (Code Review) 04 Jul '19

04 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33936 Change subject: lib/romstage_stack.c: Remove unused function ...................................................................... lib/romstage_stack.c: Remove unused function Change-Id: I1e66ff3fe7462dfeae2a7ce7e3a8083cf90a15f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/program_loading.h M src/lib/romstage_stack.c 2 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33936/1 diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 7be59e2..5644f1b 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -176,7 +176,6 @@ /* Determine where stack for ramstage loader is located. */ enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; uintptr_t romstage_ram_stack_base(size_t size, int src); -uintptr_t romstage_ram_stack_top(void); uintptr_t romstage_ram_stack_bottom(void); /* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c index ed6f09b..d085f75 100644 --- a/src/lib/romstage_stack.c +++ b/src/lib/romstage_stack.c @@ -38,14 +38,3 @@ return romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE, ROMSTAGE_STACK_CBMEM); } - -uintptr_t romstage_ram_stack_top(void) -{ - uintptr_t stack_top = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); - stack_top += ROMSTAGE_RAM_STACK_SIZE; - - /* Make it aligned to a 8-byte boundary. */ - stack_top = ALIGN_DOWN(stack_top, 8); - return stack_top; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/33936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e66ff3fe7462dfeae2a7ce7e3a8083cf90a15f9 Gerrit-Change-Number: 33936 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake/romstage: Increase size of postcar stack
by Mario Scheithauer (Code Review) 04 Jul '19

04 Jul '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33775 Change subject: soc/intel/apollolake/romstage: Increase size of postcar stack ...................................................................... soc/intel/apollolake/romstage: Increase size of postcar stack If you currently activate the measured boot on an Apollo Lake mainboard, you will run into a stack overflow during postcar. Such a behavior has already been observed on the Sky Lake platform and a corresponding patch has been made for this (https://review.coreboot.org/c/coreboot/+/33434). This issue occurs since the patch for the correct timestamp value in postcar comes up (https://review.coreboot.org/c/coreboot/+/32726 and https://review.coreboot.org/c/coreboot/+/32881). By increasing the stack size for postcar the issue is solved. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/apollolake/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33775/1 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 5bf501d..da8e581 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -240,7 +240,7 @@ else printk(BIOS_ERR, "Failed to determine variable data\n"); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 2*KiB)) die("Unable to initialize postcar frame.\n"); mainboard_save_dimm_info(); -- To view, visit https://review.coreboot.org/c/coreboot/+/33775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Gerrit-Change-Number: 33775 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Adjust postcar MTRRs
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33927 Change subject: drivers/intel/fsp1_1: Adjust postcar MTRRs ...................................................................... drivers/intel/fsp1_1: Adjust postcar MTRRs Use of romstage_ram_stack_bottom() was invalid, it potentially uses a different ROMSTAGE_RAM_STACK_SIZE from the postcar_frame_init() call. If alignment evaluated to 1 MiB, that WB MTRR may not have covered all of CBMEM range, having some impact on boot speeds. There is no need to accurately describe write-back MTRR ranges for postcar. Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_1/car.c 1 file changed, 7 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33927/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index bd3f478..b10a410 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -14,6 +14,7 @@ */ #include <arch/symbols.h> +#include <cbmem.h> #include <console/console.h> #include <commonlib/helpers.h> #include <cpu/intel/romstage.h> @@ -32,8 +33,7 @@ void platform_enter_postcar(void) { struct postcar_frame pcf; - size_t alignment; - uint32_t aligned_ram; + uintptr_t top_of_ram; if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); @@ -44,53 +44,12 @@ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. */ - - alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); - postcar_frame_add_mtrr(&pcf, aligned_ram, alignment, MTRR_TYPE_WRBACK); - - if (CONFIG(HAVE_SMI_HANDLER)) { - void *smm_base; - size_t smm_size; - - /* - * Cache the TSEG region at the top of ram. This region is not - * restricted to SMM mode until SMM has been relocated. By - * setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, (uintptr_t)smm_base, alignment, - MTRR_TYPE_WRBACK); - } + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47 Gerrit-Change-Number: 33927 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: Revert "soc/intel/skylake/romstage: Increase size of postcar stack"
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Hello Julius Werner, Arthur Heymans, Patrick Rudolph, Christian Walter, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33585 to review the following change. Change subject: Revert "soc/intel/skylake/romstage: Increase size of postcar stack" ...................................................................... Revert "soc/intel/skylake/romstage: Increase size of postcar stack" This reverts commit f70cb8bf968af75669325104756464ce6f4b824b. Reason for revert: Merged prematurely with some vague argumentation in the commit message. Change-Id: Ia336f3499fb29976a6b80383ef8b0f3d552f5640 --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33585/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 0eff793..2819c6f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -156,7 +156,7 @@ pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 8*KiB)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/33585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia336f3499fb29976a6b80383ef8b0f3d552f5640 Gerrit-Change-Number: 33585 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: amdfam10: Declare get_sysinfo()
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33995 Change subject: amdfam10: Declare get_sysinfo() ...................................................................... amdfam10: Declare get_sysinfo() It's forbidden to use derefence CAR_GLOBAL variables directly. The notation fails after CAR teardown for romstage. Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/raminit.h M src/northbridge/amd/amdfam10/raminit_amdmct.c 26 files changed, 31 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/33995/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index d8e6185..ca32977 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -46,7 +46,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index e9d391c..e2142f2 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -42,7 +42,6 @@ #include "cpu/amd/quadcore/quadcore.c" int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -52,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 2376414..3397d26 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -46,7 +46,6 @@ #include "cpu/amd/quadcore/quadcore.c" int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 1ba6542..3871c59 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -42,7 +42,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; static void memreset_setup(void) { @@ -167,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 9aa59b2..702e9db 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -44,7 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -55,7 +54,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 4bcfedd..51d178f 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -51,7 +51,6 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) { @@ -355,7 +354,7 @@ : "=r" (esp) ); - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); /* Limit the maximum HT speed to 2.6GHz to prevent lockups * due to HT CPU <--> CPU wiring not being validated to 3.2GHz diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 817e6db..7b20243 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -54,7 +54,6 @@ #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(unsigned int device, unsigned int address) { @@ -184,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 85ad0b6..637ec42 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -52,7 +52,6 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(unsigned int device, unsigned int address) { @@ -180,7 +179,7 @@ void activate_spd_rom(const struct mem_controller *ctrl) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); @@ -467,7 +466,7 @@ : "=r" (esp) ); - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); /* Limit the maximum HT speed to 2.6GHz to prevent lockups * due to HT CPU <--> CPU wiring not being validated to 3.2GHz diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 072b758..c52b35b 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index c03115d..b7af9e2 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index ad05371..1309d67 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -47,7 +47,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -58,7 +57,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 2d3c762..b4b536e 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -46,7 +46,6 @@ #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index cbcb54d..0d1f45d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 2af958b..384eccd 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 4a28a2e..48af367 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 94489c4..354bf12 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -53,7 +53,6 @@ #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { @@ -83,7 +82,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index fa57894..d8afd67 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -46,7 +46,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 8296b4c..33d40b8 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -51,7 +51,6 @@ #endif int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -61,7 +60,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ecb3ab9..2fc6fb4 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -45,7 +45,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) @@ -100,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; u8 reg; msr_t msr; diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c6f5d63..2750129 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -48,7 +48,6 @@ #define SUPERIO_DEV PNP_DEV(0x2e, 0) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) @@ -101,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 87957e9..56d9f35 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -51,7 +51,6 @@ #define SMBUS_SWITCH2 0x72 int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { @@ -154,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 93dca02..302e86f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -43,7 +43,6 @@ #include "cpu/amd/quadcore/quadcore.c" int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -53,7 +52,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = { RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0, //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0, diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 85824aa..f44346b 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -44,7 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) @@ -104,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index d2a0528..0fbcea6 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -989,12 +989,6 @@ struct DCTStatStruc DCTstatA[NODE_NUMS]; } __packed; - -/* -#ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; -#endif -*/ #ifndef __PRE_RAM__ struct device *get_node_pci(u32 nodeid, u32 fn); #endif diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 9d1d91d..c9c57ff 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -30,6 +30,7 @@ void mctSMBhub_Init(u32 node); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); void set_sysinfo_in_ram(u32 val); +struct sys_info *get_sysinfo(void); void raminit_amdmct(struct sys_info *sysinfo); void amdmct_cbmem_store_info(struct sys_info *sysinfo); void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 1f2b51d..440a026 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -29,7 +29,12 @@ /* Global allocation of sysinfo_car */ #include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; +static struct sys_info sysinfo_car CAR_GLOBAL; + +struct sys_info *get_sysinfo(void) +{ + return car_get_var_ptr(&sysinfo_car); +} struct mem_controller; extern int spd_read_byte(unsigned int device, unsigned int address); -- To view, visit https://review.coreboot.org/c/coreboot/+/33995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87 Gerrit-Change-Number: 33995 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: amdfam10: Declare empty activate_spd_rom() stub
by Kyösti Mälkki (Code Review) 04 Jul '19

04 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33994 Change subject: amdfam10: Declare empty activate_spd_rom() stub ...................................................................... amdfam10: Declare empty activate_spd_rom() stub Change-Id: I1d0940a08f7ae5901b812618a6859c4297274591 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdfam10/raminit.h M src/northbridge/amd/amdfam10/raminit_amdmct.c 25 files changed, 12 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33994/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 4a817cf..d8e6185 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -45,13 +45,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7b2f051..e9d391c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -41,13 +41,9 @@ #include "cpu/amd/quadcore/quadcore.c" -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index c73eb0d..2376414 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -45,11 +45,9 @@ #include "cpu/amd/quadcore/quadcore.c" -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index a525154..1ba6542 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -41,7 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index a45d8f6..9aa59b2 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -43,11 +43,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 6c40627..4bcfedd 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -50,7 +50,6 @@ #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index dbf704b..817e6db 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -53,7 +53,6 @@ #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; @@ -170,7 +169,8 @@ RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, }; -void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) +{ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index d017b06..85ad0b6 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -51,7 +51,6 @@ #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; @@ -179,7 +178,8 @@ RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; -void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) +{ struct sys_info *sysinfo = &sysinfo_car; printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index c99179e..072b758 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 1d59214..c03115d 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 9216ecb..ad05371 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -46,13 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 9347919..2d3c762 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -45,13 +45,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ca318a..cbcb54d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 746be76..2af958b 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 4d23bac..4a28a2e 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index c02b0e6..94489c4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -52,11 +52,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { u8 val; outb(0x3d, 0x0cd6); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 421e613..fa57894 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -45,11 +45,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 7fcb594..8296b4c 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -50,11 +50,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 2da427d..ecb3ab9 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -44,11 +44,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 4d6846c..c6f5d63 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -47,11 +47,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 051cd61..87957e9 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -50,11 +50,10 @@ #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index f3958f8..93dca02 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -42,13 +42,9 @@ #include "cpu/amd/quadcore/quadcore.c" -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 3f504e1..85824aa 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -43,11 +43,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 029fa0e..9d1d91d 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -24,6 +24,8 @@ struct DCTStatStruc; struct MCTStatStruc; +void activate_spd_rom(const struct mem_controller *ctrl); + int mctRead_SPD(u32 smaddr, u32 reg); void mctSMBhub_Init(u32 node); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 4f31a5e..1f2b51d 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -32,9 +32,12 @@ struct sys_info sysinfo_car CAR_GLOBAL; struct mem_controller; -extern void activate_spd_rom(const struct mem_controller *ctrl); extern int spd_read_byte(unsigned int device, unsigned int address); +void __weak activate_spd_rom(const struct mem_controller *ctrl) +{ +} + void fam15h_switch_dct(uint32_t dev, uint8_t dct) { uint32_t dword; -- To view, visit https://review.coreboot.org/c/coreboot/+/33994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0940a08f7ae5901b812618a6859c4297274591 Gerrit-Change-Number: 33994 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019