coreboot-gerrit July 2019

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Change in ...coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Hello Paul Fagerburg, Philip Chen, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33954 to look at the new patch set (#5). Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... mb/google/hatch/variants: Fix nonworking touch pad Modify GPP_A21 to interrupt and disable all GPIO PM config. BUG=b:135507215 BRANCH=Master TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 --- M src/mainboard/google/hatch/variants/helios/gpio.c M src/mainboard/google/hatch/variants/helios/overridetree.cb 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33954/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 03 Jul '19

03 Jul '19

Hello Paul Fagerburg, Philip Chen, Tim Wawrzynczak, Shelley Chen, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33954 to look at the new patch set (#4). Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... mb/google/hatch/variants: Fix nonworking touch pad Modify GPP_A21 to interrupt and disables PM configuration on all GPIO communities. BUG=b:135507215 BRANCH=Master TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 --- M src/mainboard/google/hatch/variants/helios/gpio.c M src/mainboard/google/hatch/variants/helios/overridetree.cb 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33954/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platforms
by Julius Werner (Code Review) 03 Jul '19

03 Jul '19

Hello Joel Kitching, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33952 to review the following change. Change subject: vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platforms ...................................................................... vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platforms When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on some Arm platforms the original working data buffer was in SRAM, which stays accessbile for the whole runtime of the system. There is no reason to migrate it into CBMEM on those platforms because ramstage and the payload could continue to access it in SRAM. Now that we've had a couple of months of experience with this option, we found that most of our Arm platforms have some issue that requires migrating anyway, because BL31 often claims SRAM for itself and makes it inaccessible to the payload. On the remaining platforms, accessing SRAM from the payload is possible but still an issue, because libpayload doesn't have enough memory layout information to set up proper page tables for it, so we're accessing it uncached and at risk of alignment errors. Rather than having to figure out how to map the right SRAM range for every platform in the payload, let's just get rid of the option. memcpy()ing 12KB isn't worth this much hassle. Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/Kconfig M src/security/vboot/common.c M src/security/vboot/vboot_loader.c M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/rockchip/rk3399/Kconfig 6 files changed, 3 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33952/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 66bcc1e..ea1f738 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -107,21 +107,6 @@ memory initialization). This implies that vboot working data is allocated in CBMEM. -config VBOOT_MIGRATE_WORKING_DATA - bool - default y if CACHE_AS_RAM - depends on !VBOOT_STARTS_IN_ROMSTAGE - help - In order to make vboot data structures available downstream, - migrate verified boot working data to CBMEM after CBMEM comes - online, when VBOOT_STARTS_IN_BOOTBLOCK is employed. This should - always be enabled on x86 architectures to migrate data from CAR - before losing access in ramstage, and should almost always be - disabled in SRAM architectures, where access to SRAM is usually - retained. Any SRAM platform where the original location of the - VBOOT_WORKBUF region becomes inaccessible in later stages should - manually select this option. - config VBOOT_MOCK_SECDATA bool "Mock secdata for firmware verification" default n diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index bd72683..626fbc5 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -117,13 +117,12 @@ return reg->size > 0; } -#if CONFIG(VBOOT_MIGRATE_WORKING_DATA) +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* * For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot * verification occurs before CBMEM is brought online, using pre-RAM. * In order to make vboot data structures available downstream, copy - * vboot_working_data from SRAM/CAR into CBMEM on platforms where this - * memory later becomes unavailable. + * vboot_working_data from SRAM/CAR into CBMEM. */ static void vboot_migrate_cbmem(int unused) { @@ -140,7 +139,7 @@ memcpy(wd_cbmem, wd_preram, cbmem_size); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) -#elif CONFIG(VBOOT_STARTS_IN_ROMSTAGE) +#else static void vboot_setup_cbmem(int unused) { struct vboot_working_data *wd_cbmem = diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 9e2cd00..af4a3fd 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -26,9 +26,6 @@ _Static_assert(CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) + CONFIG(VBOOT_STARTS_IN_ROMSTAGE) == 1, "vboot must either start in bootblock or romstage (not both!)"); -_Static_assert(CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) || - !CONFIG(VBOOT_MIGRATE_WORKING_DATA), - "no need to migrate working data after CBMEM is already up!"); _Static_assert(!CONFIG(VBOOT_SEPARATE_VERSTAGE) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "stand-alone verstage must start in (i.e. after) bootblock"); diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index e24993a..aa867c2 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -19,7 +19,6 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_MIGRATE_WORKING_DATA config QCS405_BLSP_SPI bool diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index f6268c9..459a441 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -19,7 +19,6 @@ select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_MIGRATE_WORKING_DATA config SDM845_QSPI bool diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 897a597..83fc437 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -17,7 +17,6 @@ if SOC_ROCKCHIP_RK3399 config VBOOT - select VBOOT_MIGRATE_WORKING_DATA select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY -- To view, visit https://review.coreboot.org/c/coreboot/+/33952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf Gerrit-Change-Number: 33952 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: _WIP_ soc/amd/picasso: Update southbridge
by Marshall Dawson (Code Review) 03 Jul '19

03 Jul '19

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33770 to look at the new patch set (#2). Change subject: _WIP_ soc/amd/picasso: Update southbridge ...................................................................... _WIP_ soc/amd/picasso: Update southbridge Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 --- M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 3 files changed, 94 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/33770/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sdm845: Update macro definition in CB clock driver
by Julius Werner (Code Review) 02 Jul '19

02 Jul '19

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33811 ) Change subject: sdm845: Update macro definition in CB clock driver ...................................................................... sdm845: Update macro definition in CB clock driver Use literals KHz & MHz for kilohertz and megahertz frequency usages in macro definition. Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/soc/qualcomm/sdm845/include/soc/clock.h 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index 6aee9c1..ea4d87d 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -30,9 +30,9 @@ #define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) #define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) -#define GPLL0_EVEN_HZ (300*Mhz) -#define GPLL0_MAIN_HZ (600*Mhz) -#define QUP_WRAP_CORE_2X_19_2MHZ (19200*Khz) +#define GPLL0_EVEN_HZ (300*MHz) +#define GPLL0_MAIN_HZ (600*MHz) +#define QUP_WRAP_CORE_2X_19_2MHZ (19200*KHz) #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba Gerrit-Change-Number: 33811 Gerrit-PatchSet: 2 Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: arch/x86: Fix spelling error in BERT comment
by Marshall Dawson (Code Review) 02 Jul '19

02 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33965 Change subject: arch/x86: Fix spelling error in BERT comment ...................................................................... arch/x86: Fix spelling error in BERT comment Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25 --- M src/arch/x86/include/arch/bert_storage.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33965/1 diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index c96918c..5c87aed 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -67,7 +67,7 @@ /* Find if errors were added, a BERT region is present, and ACPI table needed */ int bert_errors_present(void); -/* Get the number of entries accociated with status */ +/* Get the number of entries associated with status */ static inline size_t bert_entry_count(acpi_generic_error_status_t *status) { return (status->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) -- To view, visit https://review.coreboot.org/c/coreboot/+/33965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25 Gerrit-Change-Number: 33965 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cbfstool: show "preserved" flag in cbfstool layout output
by Patrick Georgi (Code Review) 02 Jul '19

02 Jul '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33604 Change subject: cbfstool: show "preserved" flag in cbfstool layout output ...................................................................... cbfstool: show "preserved" flag in cbfstool layout output The flag is useful for updaters to determine which areas to leave alone, such as VPD (vital product data) regions that are set in factory and might contain unique (MAC addresses) or hard to obtain (calibration output) data. It's also useful to see which regions are marked as such. Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/cbfstool/cbfstool.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33604/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index e8b1f6f..8fd13b5 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1047,6 +1047,8 @@ qualifier = "read-only, "; else if (region_is_modern_cbfs((const char *)current->name)) qualifier = "CBFS, "; + else if (current->flags & FMAP_AREA_PRESERVE) + qualifier = "preserve, "; printf(" (%ssize %u, offset %u)\n", qualifier, current->size, current->offset); -- To view, visit https://review.coreboot.org/c/coreboot/+/33604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6 Gerrit-Change-Number: 33604 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/amd/msr: Clarify MMIO_CONF shift value
by Marshall Dawson (Code Review) 02 Jul '19

02 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33942 Change subject: cpu/amd/msr: Clarify MMIO_CONF shift value ...................................................................... cpu/amd/msr: Clarify MMIO_CONF shift value MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field. Change it to simply 2. Otherwise its usage winds up evaluating to BusRange << (1 << 1). Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc --- M src/include/cpu/amd/msr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33942/1 diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 5d7b5e4..0f88e51 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -39,7 +39,7 @@ #define MSR_INTPEND 0xC0010055 #define MMIO_CONF_BASE 0xC0010058 #define MMIO_RANGE_EN (1 << 0) -#define MMIO_BUS_RANGE_SHIFT (1 << 1) +#define MMIO_BUS_RANGE_SHIFT 2 /* P-state Current Limit Register */ #define PS_LIM_REG 0xC0010061 /* P-state Maximum Value shift position */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc Gerrit-Change-Number: 33942 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Add ability to begin romstage in DRAM
by Richard Spiegel (Code Review) 02 Jul '19

02 Jul '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Add ability to begin romstage in DRAM ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jul 2019 17:04:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add support to log XHCI wake events
by Paul Fagerburg (Code Review) 02 Jul '19

02 Jul '19

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33843 Change subject: soc/intel/cannonlake: Add support to log XHCI wake events ...................................................................... soc/intel/cannonlake: Add support to log XHCI wake events Enhance elog wake source information with more details about which USB port resulted in a wake from S3 or S0ix. BUG=b:123429132 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Plug a keyboard into a USB port on the DUT. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). On the console, run ``powerd_dbus_suspend``. Wait for the DUT to enter low power mode. Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. Press a key on the USB keyboard. The DUT wakes up. On the console, run ``mosys eventlog list`` and look for the wake source. 156 | 2019-06-26 09:46:07 | S0ix Enter 157 | 2019-06-26 12:14:05 | S0ix Exit 158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0 159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109 Program image-hatch.serial.bin into the DUT using flashrom. Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list`` sequence. 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32 Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/elog.c 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/33843/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 2279df2..023b0c4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -93,6 +93,8 @@ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 2ec6b41..141aa45 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -20,9 +20,22 @@ #include <stdint.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x580 +#define XHCI_USB2_PORT_NUM 14 +#define XHCI_USB3_PORT_NUM 10 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -53,9 +66,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_xhci_update_wake_event(&usb_info); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/33843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32 Gerrit-Change-Number: 33843 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019