coreboot-gerrit July 2019

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Change in ...coreboot[master]: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms
by Arthur Heymans (Code Review) 02 Jul '19

02 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31311 Change subject: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms ...................................................................... arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31311/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af..f5253bb 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,6 +24,7 @@ # one implementation that will not have it due # to security concerns. bool + depends on ARCH_RISCV default n if ARCH_RISCV_M_DISABLED default y -- To view, visit https://review.coreboot.org/c/coreboot/+/31311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Gerrit-Change-Number: 31311 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/pc80/rtc/mc146818rtc_boot: Use size_t for length
by HAOUAS Elyes (Code Review) 02 Jul '19

02 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33805 Change subject: drivers/pc80/rtc/mc146818rtc_boot: Use size_t for length ...................................................................... drivers/pc80/rtc/mc146818rtc_boot: Use size_t for length Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/pc80/rtc/mc146818rtc_boot.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33805/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 26bcac5..0ac06b3 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -67,7 +67,7 @@ CBFS_COMPONENT_CMOS_DEFAULT, &length); #endif if (cmos_default) { - int i; + size_t i; cmos_disable_rtc(); for (i = 14; i < MIN(128, length); i++) cmos_write_inner(cmos_default[i], i); -- To view, visit https://review.coreboot.org/c/coreboot/+/33805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece Gerrit-Change-Number: 33805 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: src: Use CRx_TYPE type for cr
by HAOUAS Elyes (Code Review) 02 Jul '19

02 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33816 Change subject: src: Use CRx_TYPE type for cr ...................................................................... src: Use CRx_TYPE type for cr Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/cache.h M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct/mcttmrl.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c M src/soc/intel/quark/reg_access.c 9 files changed, 16 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33816/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0f73e71..cbbc10d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -417,7 +417,7 @@ * Seems that CR4 was cleared when AP start via lapic_start_cpu() * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled */ - u32 cr4_val; + CRx_TYPE cr4_val; cr4_val = read_cr4(); cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(cr4_val); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index c8d26ab..7f135e5 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -67,7 +67,7 @@ */ static __always_inline void enable_cache(void) { - unsigned long cr0; + CRx_TYPE cr0; cr0 = read_cr0(); cr0 &= ~(CR0_CD | CR0_NW); write_cr0(cr0); @@ -76,7 +76,7 @@ static __always_inline void disable_cache(void) { /* Disable and write back the cache */ - unsigned long cr0; + CRx_TYPE cr0; cr0 = read_cr0(); cr0 |= CR0_CD; wbinvd(); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 36ee3ab..2e52a39 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -278,7 +278,7 @@ u8 dqsWrDelay_end; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 649c1c8..406547e 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -129,7 +129,7 @@ u32 index_reg; u32 ch_start, ch_end, ch; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index a78d42d..6ec4d64 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -122,7 +122,7 @@ u32 PatternBuffer[60]; // FIXME: why not 48 + 4 u32 Margin; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 34b13ea..6b31294 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -16,6 +16,7 @@ #include <inttypes.h> #include <console/console.h> +#include <cpu/x86/cr.h> #include <string.h> #include <arch/cpu.h> #include <cpu/amd/msr.h> @@ -405,7 +406,7 @@ u32 dev; u32 addr; u8 valid; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u32 index_reg; uint32_t TestAddr; @@ -1617,7 +1618,7 @@ u8 _Wrap32Dis = 0, _SSE2 = 0; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint8_t dct; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index a6faf90..032152c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -22,6 +22,7 @@ #include <arch/cpu.h> #include <inttypes.h> #include <console/console.h> +#include <cpu/x86/cr.h> #include <string.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> @@ -612,7 +613,7 @@ u32 index_reg; u32 ch_start, ch_end, ch; msr_t msr; - u32 cr4; + CRx_TYPE cr4; uint32_t dword; uint8_t dimm; @@ -1186,7 +1187,7 @@ u32 index_reg; u32 ch_start, ch_end, ch; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; @@ -1583,7 +1584,7 @@ u32 index_reg; u32 ch_start, ch_end; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index e7b7883..ec9b8e4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -21,7 +21,7 @@ #include <inttypes.h> #include <console/console.h> #include <cpu/amd/msr.h> - +#include <cpu/x86/cr.h> #include "mct_d.h" #include "mct_d_gcc.h" @@ -119,7 +119,7 @@ u32 PatternBuffer[60]; /* FIXME: why not 48 + 4 */ u32 Margin; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 1063525..5e5acd8 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <assert.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> #include <console/console.h> #include <delay.h> #include <device/pci_ops.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72 Gerrit-Change-Number: 33816 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/variants: Touch pad no function
by Paul Fagerburg (Code Review) 02 Jul '19

02 Jul '19

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Touch pad no function ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/33954/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/33954/3//COMMIT_MSG@7 PS3, Line 7: mb/google/hatch/variants: Touch pad no function > Please make it a statement. […] Seconded. -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 16:13:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/cbmem: Enable -Wmissing-prototypes
by Jacob Garber (Code Review) 02 Jul '19

02 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33853 Change subject: util/cbmem: Enable -Wmissing-prototypes ...................................................................... util/cbmem: Enable -Wmissing-prototypes Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M util/cbmem/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33853/1 diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index e7318a1..485955b 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -19,7 +19,7 @@ INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 -CFLAGS += -Wall -Wextra -Werror +CFLAGS += -Wall -Wextra -Wmissing-prototypes -Werror CPPFLAGS += -I . -I $(ROOT)/commonlib/include CPPFLAGS += -include ../../src/commonlib/include/commonlib/compiler.h -- To view, visit https://review.coreboot.org/c/coreboot/+/33853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e Gerrit-Change-Number: 33853 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbmem: Make internal functions static
by Jacob Garber (Code Review) 02 Jul '19

02 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33852 Change subject: util/cbmem: Make internal functions static ...................................................................... util/cbmem: Make internal functions static These functions are only used in cbmem, so they can be made static. Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M util/cbmem/cbmem.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33852/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 9a443a8..914effa 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -521,7 +521,7 @@ debug("Timestamp tick frequency: %ld MHz\n", tick_freq_mhz); } -u64 arch_convert_raw_ts_entry(u64 ts) +static u64 arch_convert_raw_ts_entry(u64 ts) { return ts / tick_freq_mhz; } @@ -569,7 +569,7 @@ return step_time; } -uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) +static uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) { const char *name; uint64_t step_time; @@ -866,7 +866,7 @@ hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size)); } -void rawdump(uint64_t base, uint64_t size) +static void rawdump(uint64_t base, uint64_t size) { const uint8_t *m; struct mapping dump_mapping; @@ -927,7 +927,7 @@ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; #define MAX_STAGEx 10 -void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) +static void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) { const char *name; char stage_x[20]; -- To view, visit https://review.coreboot.org/c/coreboot/+/33852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006 Gerrit-Change-Number: 33852 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbmem: Enable -Wextra
by Jacob Garber (Code Review) 02 Jul '19

02 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33851 Change subject: util/cbmem: Enable -Wextra ...................................................................... util/cbmem: Enable -Wextra This enables extra useful warnings. Change-Id: I4afbbb0fefb32a7d954aafd87df17075b0abe6f7 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M util/cbmem/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33851/1 diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index eed08a4..e7318a1 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -19,7 +19,7 @@ INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 -CFLAGS += -Wall -Werror +CFLAGS += -Wall -Wextra -Werror CPPFLAGS += -I . -I $(ROOT)/commonlib/include CPPFLAGS += -include ../../src/commonlib/include/commonlib/compiler.h -- To view, visit https://review.coreboot.org/c/coreboot/+/33851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4afbbb0fefb32a7d954aafd87df17075b0abe6f7 Gerrit-Change-Number: 33851 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbmem: Use correct integer types for loop indices
by Jacob Garber (Code Review) 02 Jul '19

02 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33850 Change subject: util/cbmem: Use correct integer types for loop indices ...................................................................... util/cbmem: Use correct integer types for loop indices Make sure that the type of the loop index matches the type of the upper bound. This fixes several -Wsign-compare warnings. Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M util/cbmem/cbmem.c 1 file changed, 8 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33850/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 52fdc9b..9a443a8 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -543,9 +543,7 @@ static const char *timestamp_name(uint32_t id) { - int i; - - for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { + for (size_t i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { if (timestamp_ids[i].id == id) return timestamp_ids[i].name; } @@ -608,7 +606,6 @@ /* dump the timestamp table */ static void dump_timestamps(int mach_readable) { - int i; const struct timestamp_table *tst_p; struct timestamp_table *sorted_tst_p; size_t size; @@ -656,7 +653,7 @@ sizeof(struct timestamp_entry), compare_timestamp_entries); total_time = 0; - for (i = 0; i < sorted_tst_p->num_entries; i++) { + for (uint32_t i = 0; i < sorted_tst_p->num_entries; i++) { uint64_t stamp; const struct timestamp_entry *tse = &sorted_tst_p->entries[i]; @@ -685,7 +682,6 @@ /* dump the tcpa log table */ static void dump_tcpa_log(void) { - int i, j; const struct tcpa_table *tclt_p; size_t size; struct mapping tcpa_mapping; @@ -710,12 +706,12 @@ printf("coreboot TCPA log:\n\n"); - for (i = 0; i < tclt_p->num_entries; i++) { + for (uint16_t i = 0; i < tclt_p->num_entries; i++) { const struct tcpa_entry *tce = &tclt_p->entries[i]; printf(" PCR-%u ", tce->pcr); - for (j = 0; j < tce->digest_length; j++) + for (uint32_t j = 0; j < tce->digest_length; j++) printf("%02x", tce->digest[j]); printf(" %s [%s]\n", tce->digest_type, tce->name); @@ -804,9 +800,8 @@ BANNER_REGEX("romstage"), OVERFLOW_REGEX("ramstage"), BANNER_REGEX("ramstage") }; - int i; - for (i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { + for (size_t i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { regex_t re; regmatch_t match; assert(!regcomp(&re, regex[i], 0)); @@ -873,7 +868,6 @@ void rawdump(uint64_t base, uint64_t size) { - int i; const uint8_t *m; struct mapping dump_mapping; @@ -881,7 +875,7 @@ if (!m) die("Unable to map rawdump memory\n"); - for (i = 0 ; i < size; i++) + for (uint64_t i = 0 ; i < size; i++) printf("%c", m[i]); unmap_memory(&dump_mapping); @@ -935,12 +929,11 @@ #define MAX_STAGEx 10 void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) { - int i; const char *name; char stage_x[20]; name = NULL; - for (i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { + for (size_t i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { if (cbmem_ids[i].id == id) { name = cbmem_ids[i].name; break; @@ -1388,11 +1381,10 @@ parse_cbtable(baseaddr, cb_table_size); #else - int j; unsigned long long possible_base_addresses[] = { 0, 0xf0000 }; /* Find and parse coreboot table */ - for (j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) { + for (size_t j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) { if (!parse_cbtable(possible_base_addresses[j], 0)) break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac Gerrit-Change-Number: 33850 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] 3rdparty/fsp: Update submodule pointer
by Bora Guvendik (Code Review) 02 Jul '19

02 Jul '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33642 Change subject: [WIP] 3rdparty/fsp: Update submodule pointer ...................................................................... [WIP] 3rdparty/fsp: Update submodule pointer Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40 Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33642/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 1d2b7e1..5996417 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 1d2b7e1a94c6a7c25a6fed1ac37caebf500f5f1a +Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f -- To view, visit https://review.coreboot.org/c/coreboot/+/33642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12 Gerrit-Change-Number: 33642 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/: Fix cpu_cpuid_extended_level() returned value
by HAOUAS Elyes (Code Review) 02 Jul '19

02 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33814 Change subject: arch/x86/: Fix cpu_cpuid_extended_level() returned value ...................................................................... arch/x86/: Fix cpu_cpuid_extended_level() returned value Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/33814/1 diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 1191227..0fd0af0 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -49,7 +49,7 @@ } #endif -int cpu_cpuid_extended_level(void) +unsigned int cpu_cpuid_extended_level(void) { return cpuid_eax(0x80000000); } diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index ff1a33b..75f1f43 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -200,7 +200,7 @@ #define CPUID_CACHE_NO_OF_SETS_MASK 0xffffffff #define CPUID_CACHE_NO_OF_SETS(res) CPUID_CACHE(NO_OF_SETS, (res).ecx) -int cpu_cpuid_extended_level(void); +unsigned int cpu_cpuid_extended_level(void); int cpu_have_cpuid(void); void smm_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/33814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1 Gerrit-Change-Number: 33814 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019