coreboot-gerrit July 2019

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Change in ...coreboot[master]: util/docker/coreboot.org-status: Add more "nice" names for CPUs
by Patrick Georgi (Code Review) 02 Jul '19

02 Jul '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33930 Change subject: util/docker/coreboot.org-status: Add more "nice" names for CPUs ...................................................................... util/docker/coreboot.org-status: Add more "nice" names for CPUs It's not perfect and we'll need to find a better place for that, but I'll look into that as part of the big board-status rework. Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M util/docker/coreboot.org-status/board-status.html/tohtml.sh 1 file changed, 72 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33930/1 diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 1992826..41de9ff 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -248,7 +248,12 @@ southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" - cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY"|grep -v CPU_MICROCODE_CBFS_NONE)" + cpu="$(sed -n \ + -e "/ select CPU_/ s, select CPU_,,p" \ + -e "/ select SOC_/ s, select SOC_,,p" \ + "$vendor_board_dir/Kconfig" | \ + grep -v "AMD_AGESA_FAMILY" | \ + grep -v CPU_MICROCODE_CBFS_NONE)" case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" @@ -302,12 +307,24 @@ AMD_SC520) cpu_nice="AMD Élan™SC520"; socket_nice="—";; + AMD_STONEYRIDGE_FP4) + cpu_nice="AMD Stoney Ridge"; + socket_nice="FP4 BGA";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; + MEDIATEK_MT8173) + cpu_nice="MediaTek MT8173"; + socket_nice="—";; + NVIDIA_TEGRA124) + cpu_nice="NVIDIA Tegra 124"; + socket_nice="—";; + NVIDIA_TEGRA210) + cpu_nice="NVIDIA Tegra 210"; + socket_nice="—";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; socket_nice="?";; @@ -317,6 +334,42 @@ TI_AM335X) cpu_nice="TI AM335X"; socket_nice="?";; + IMGTEC_PISTACHIO) + cpu_nice="Imagination Technologies Pistachio"; + socket_nice="—";; + INTEL_APOLLOLAKE) + cpu_nice="Intel® Apollo Lake"; + socket_nice="—";; + INTEL_BAYTRAIL) + cpu_nice="Intel® Bay Trail"; + socket_nice="—";; + INTEL_BRASWELL) + cpu_nice="Intel® Braswell"; + socket_nice="—";; + INTEL_BROADWELL) + cpu_nice="Intel® Broadwell"; + socket_nice="—";; + INTEL_DENVERTON_NS) + cpu_nice="Intel® Denverton-NS"; + socket_nice="—";; + INTEL_FSP_BROADWELL_DE) + cpu_nice="Intel® Broadwell-DE"; + socket_nice="—";; + INTEL_GLK) + cpu_nice="Intel® Gemini Lake"; + socket_nice="—";; + INTEL_ICELAKE) + cpu_nice="Intel® Ice Lake"; + socket_nice="—";; + INTEL_KABYLAKE) + cpu_nice="Intel® Kaby Lake"; + socket_nice="—";; + INTEL_SANDYBRIDGE) + cpu_nice="Intel® Sandy Bridge"; + socket_nice="—";; + INTEL_SKYLAKE) + cpu_nice="Intel® Skylake"; + socket_nice="—";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; socket_nice="Slot 1";; @@ -384,6 +437,24 @@ INTEL_SOCKET_MFCBGA479) cpu_nice="Intel® Mobile Celeron" socket_nice="Socket 479";; + INTEL_WHISKEYLAKE) + cpu_nice="Intel® Whiskey Lake"; + socket_nice="—";; + QC_IPQ806X) + cpu_nice="Qualcomm IPQ806x"; + socket_nice="—";; + QUALCOMM_QCS405) + cpu_nice="Qualcomm QCS405"; + socket_nice="—";; + QUALCOMM_SDM845) + cpu_nice="Qualcomm SDM845"; + socket_nice="—";; + ROCKCHIP_RK3288) + cpu_nice="Rockchip RK3288"; + socket_nice="—";; + ROCKCHIP_RK3399) + cpu_nice="Rockchip RK3399"; + socket_nice="—";; VIA_C3) cpu_nice="VIA C3™"; socket_nice="?" -- To view, visit https://review.coreboot.org/c/coreboot/+/33930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Gerrit-Change-Number: 33930 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/release: add more categories
by Patrick Georgi (Code Review) 02 Jul '19

02 Jul '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33929 Change subject: util/release: add more categories ...................................................................... util/release: add more categories Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M util/release/genrelnotes 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33929/1 diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 9a88b49..e4f304b 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -291,7 +291,7 @@ echo "" >> "$LOGFILE" ### SPECIFIC AREAS FOR RELEASE ### -get_log_dedupe "cleanup" "" "spelling\|Use tabs\|transition away from device_t\|space [around\|before]\|code formatting\|commented code\|code cleanup\|capitalize\|unnecessary whitespace\|checkpatch" +get_log_dedupe "cleanup" "" "spelling\|Use tabs\|transition away from device_t\|space [around\|before]\|code formatting\|commented code\|code cleanup\|capitalize\|unnecessary whitespace\|checkpatch\|remove unused\|remove.*not used" get_log_dedupe "Google Kahlee / AMD Gardenia" "src/mainboard/google/kahlee src/mainboard/amd/gardenia" "kahlee\|gardenia" get_log_dedupe "AMD Stoney Ridge" "src/soc/amd/stoneyridge" "stoney" @@ -329,11 +329,16 @@ get_log_dedupe "Intel Common" "src/soc/intel/common src/southbridge/intel/common src/northbridge/intel/common" "" get_log_dedupe "Amd Common" "src/soc/amd/common src/southbridge/amd/common" "" +get_log_dedupe "Nvidia" "src/southbridge/nvidia" "" +get_log_dedupe "Via" "src/northbridge/via src/southbridge/via" "" +get_log_dedupe "Broadcom" "src/southbridge/broadcom" "" +get_log_dedupe "Qualcomm" "src/soc/qualcomm" "" + get_log_dedupe "Intel vendorcode / FSP" "src/drivers/intel/fsp* src/vendorcode/intel" "" get_log_dedupe "AMD vendorcode / AGESA / PI" "src/vendorcode/amd" "" get_log_dedupe "Google vendorcode" "src/vendorcode/google" -get_log_dedupe "TPM" "src/drivers/i2c/tpm" "tpm" +get_log_dedupe "TPM" "src/drivers/i2c/tpm src/security/tpm" "tpm" get_log_dedupe "Vboot" "src/vboot" "vboot" @@ -394,6 +399,9 @@ "Makefile Makefile.inc toolchain.inc src/Kconfig src/cpu/Makefile.inc" get_log_dedupe "Submodules" "3rdparty util/nvidia/cbootimage" + +get_log_dedupe "Maintainers" "MAINTAINERS" "" + # Finally, get anything that was missed above get_log_dedupe "MISC" "." -- To view, visit https://review.coreboot.org/c/coreboot/+/33929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25 Gerrit-Change-Number: 33929 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update SPD sources
by Paul Fagerburg (Code Review) 02 Jul '19

02 Jul '19

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update SPD sources ...................................................................... Patch Set 2: > Patch Set 1: > > > Patch Set 1: Code-Review-1 > > > > (1 comment) > The DRAM ID table at Proto stage is > > ID 0 Samsung 16Gb 2133MT/s K4E6E304EC/ED-EGCG > ID 1 Samsung 32Gb 2133MT/s K4EB304ED-EGCG > ID 2 Hynix 8Gb 2133MT/s H9CCNNN8GTALAR-NVD > ID 3 Hynix 16Gb 2133MT/s H9CCNNNBJTALAR-NVD > ID 4 Hynix 32Gb 2133MT/s H9CCNNNCLGALAR-NVD > > According to Intel's feedback , current SPD support the same capacity and speed with different brand , so ID 0 and ID 3 use 1 SPD file . ID 1 and ID 4 use another SPD file . Also, Helios will not be using the Hynix H9CCNNN8GTALAR part. -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 16:00:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Set trackpad wake to GPP_A21
by Shelley Chen (Code Review) 02 Jul '19

02 Jul '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33820 Change subject: mb/google/hatch: Set trackpad wake to GPP_A21 ...................................................................... mb/google/hatch: Set trackpad wake to GPP_A21 Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for trackpad interrupts due to ITSS not honoring the INVERT config. Now that's fixed, we can configure trackpad wake and interrupts on GPP_A21 only. BUG=b:130436471 BRANCH=None TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad 2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure through "mosys eventlog list" that the wake source is the trackpad. Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb 2 files changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/33820/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a4fb4c9..38e31ba 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -54,12 +54,8 @@ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* A20 : WLAN_INT_L */ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), - /* - * A21 : TRACKPAD_INT_ODL (wake) - * TODO Combine into single gpio, when ITSS IPCx configuration - * is fixed in FSP. - */ - PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), + /* A21 : TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), /* A23 : FPMCU_PCH_INT_ODL */ @@ -209,12 +205,8 @@ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA_0_SNDW4_DATA */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), - /* - * D21 : TRACKPAD_INT_ODL - * TODO Combine into single gpio with invert mode, when ITSS - * IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE), + /* D21 : GPP_D22 ==> NC */ + PAD_NC(GPP_D21, NONE), /* D22 : GPP_D22 ==> NC */ PAD_NC(GPP_D22, NONE), /* D23 : SPP_MCLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index d676843..2582940 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -63,7 +63,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/33820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Gerrit-Change-Number: 33820 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add INVERT to all IOAPIC pads
by Shelley Chen (Code Review) 02 Jul '19

02 Jul '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33819 Change subject: mb/google/hatch: Add INVERT to all IOAPIC pads ...................................................................... mb/google/hatch: Add INVERT to all IOAPIC pads Now that ITSS config is fixed, we can set the IOAPIC pad configs correctly. BUG=b:123967687 BRANCH=None TEST=Make sure Hatch is booting and tested out trackpad to make sure can move cursor and wake by slicking on the trackpad after running powerd_dbus_suspend. Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/gpio.c 2 files changed, 12 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33819/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 9529cc7..a4fb4c9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -52,8 +52,8 @@ PAD_CFG_GPO(GPP_A18, 1, DEEP), /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* A20 : M2_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), + /* A20 : WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), /* * A21 : TRACKPAD_INT_ODL (wake) * TODO Combine into single gpio, when ITSS IPCx configuration @@ -62,11 +62,8 @@ PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), - /* A23 : FPMCU_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE), + /* A23 : FPMCU_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -143,11 +140,8 @@ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : GPP_C12 ==> NC */ PAD_NC(GPP_C12, NONE), - /* C13 : EC_PCH_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, NONE), + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), /* C15 : WWAN_DPR_SAR_ODL @@ -166,12 +160,8 @@ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* - * C21 : H1_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ @@ -451,12 +441,8 @@ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* - * C21 : H1_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* F2 : MEM_CH_SEL */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 7e73724..f95e022 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,11 +19,8 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { - /* C13 : EC_PCH_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, NONE)}; + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; const struct pad_config *override_gpio_table(size_t *num) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Gerrit-Change-Number: 33819 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/variants: Touch pad no function
by Furquan Shaikh (Code Review) 02 Jul '19

02 Jul '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Touch pad no function ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/gpio.c: https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… PS3, Line 37: PAD_CFG_GPI_APIC(GPP_A21, NONE, DEEP, LEVEL, NONE), > The baseboard/gpio.c is PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), it's different. Ah, I missed that this change was still pending: https://review.coreboot.org/c/coreboot/+/33820/5 With that change, GPP_A21 should work for interrupts as well as for wake. You shouldn't need a change specifically for helios here. -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 15:56:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update SPD sources
by Paul Fagerburg (Code Review) 02 Jul '19

02 Jul '19

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update SPD sources ...................................................................... Patch Set 2: Code-Review-1 If the Helios board DRAM select resistors are being loaded for 0010, 0011, or 0100, the best solution is a hardware ECO to not correct them to 0000 and 0001. There should never be any reason to use the empty_ddr4 on a new design. -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 15:50:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants: Touch pad no function
by EricR Lai (Code Review) 02 Jul '19

02 Jul '19

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Touch pad no function ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/gpio.c: https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… PS3, Line 37: PAD_CFG_GPI_APIC(GPP_A21, NONE, DEEP, LEVEL, NONE), > Why is this change required? It is already done in baseboard/gpio. […] The baseboard/gpio.c is PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), it's different. -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 15:41:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants: Touch pad no function
by Furquan Shaikh (Code Review) 02 Jul '19

02 Jul '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Touch pad no function ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/gpio.c: https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… PS3, Line 37: PAD_CFG_GPI_APIC(GPP_A21, NONE, DEEP, LEVEL, NONE), Why is this change required? It is already done in baseboard/gpio.c https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/overridetree.cb: https://review.coreboot.org/#/c/33954/3/src/mainboard/google/hatch/variants… PS3, Line 2: # GPIO community PM configuration : register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_2]" = "0" : register "gpio_pm[COMM_3]" = "0" Did you try without this change to see if touchpad works? -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 14:59:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd: Add picasso to Kconfig
by Marshall Dawson (Code Review) 02 Jul '19

02 Jul '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33750 Change subject: soc/amd: Add picasso to Kconfig ...................................................................... soc/amd: Add picasso to Kconfig Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33750/1 diff --git a/src/soc/amd/Kconfig b/src/soc/amd/Kconfig index 0c33b54..7c08f03 100644 --- a/src/soc/amd/Kconfig +++ b/src/soc/amd/Kconfig @@ -1,4 +1,5 @@ # Load all chipsets before common +source "src/soc/amd/picasso/Kconfig" source "src/soc/amd/stoneyridge/Kconfig" # Load common defaults last -- To view, visit https://review.coreboot.org/c/coreboot/+/33750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845 Gerrit-Change-Number: 33750 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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