coreboot-gerrit July 2019

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Change in ...coreboot[master]: device/pci_rom: Fix on-board optionrom address
by Kyösti Mälkki (Code Review) 02 Jul '19

02 Jul '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33908 ) Change subject: device/pci_rom: Fix on-board optionrom address ...................................................................... device/pci_rom: Fix on-board optionrom address The function pci_rom_probe() may be called multiple times for a device. For cases where CBFS does not contain optionrom file, only the first time probing for the on-board ROM chip worked. PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all the reserved bits of PCI_ROM_ADDRESS register to get correct physical address for rom_header. Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Mike Banon <mikebdp2(a)gmail.com> --- M src/device/pci_rom.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Mike Banon: Looks good to me, approved diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 3160c20..7322e57 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -77,6 +77,8 @@ rom_address|PCI_ROM_ADDRESS_ENABLE); } + rom_address &= PCI_ROM_ADDRESS_MASK; + printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; -- To view, visit https://review.coreboot.org/c/coreboot/+/33908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee Gerrit-Change-Number: 33908 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: security/memory: Clear memory in ramstage
by Philipp Deppenwiese (Code Review) 02 Jul '19

02 Jul '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31550 ) Change subject: security/memory: Clear memory in ramstage ...................................................................... security/memory: Clear memory in ramstage * Add architecture independend way of clearing all DRAM * Implemented in ramstage as MTRRs need to be set to speed up clearing. Takes up to 15 seconds per GiB otherwise. * Use memset_pae on x86 * Add quirks for FSP1.0 Tested on P8H61M-Pro: * Clears 4GiB in less than 1 second Tested on wedge100s: * Clears 8GiB in 2 seconds Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/arch/x86/include/arch/memory_clear.h M src/security/memory/Kconfig M src/security/memory/Makefile.inc A src/security/memory/memory_clear.c 4 files changed, 188 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/arch/x86/include/arch/memory_clear.h b/src/arch/x86/include/arch/memory_clear.h new file mode 100644 index 0000000..87ad7ad --- /dev/null +++ b/src/arch/x86/include/arch/memory_clear.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MEMORY_CLEAR_H +#define MEMORY_CLEAR_H + +#include <memrange.h> + +int arch_clear_memranges(const struct memranges *mem_reserved); + +#endif /* MEMORY_CLEAR_H */ diff --git a/src/security/memory/Kconfig b/src/security/memory/Kconfig index 5436119..d84b80d 100644 --- a/src/security/memory/Kconfig +++ b/src/security/memory/Kconfig @@ -17,7 +17,9 @@ config PLATFORM_HAS_DRAM_CLEAR bool + default y if ARCH_X86 default n + depends on RELOCATABLE_RAMSTAGE help Selected by platforms that support clearing all DRAM after DRAM initialization. diff --git a/src/security/memory/Makefile.inc b/src/security/memory/Makefile.inc index 525c4db..0882ca3 100644 --- a/src/security/memory/Makefile.inc +++ b/src/security/memory/Makefile.inc @@ -1,3 +1,5 @@ romstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c + +ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory_clear.c diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c new file mode 100644 index 0000000..638c41a --- /dev/null +++ b/src/security/memory/memory_clear.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(ARCH_X86) +#include <cpu/x86/pae.h> +#else +#define memset_pae(a, b, c, d, e) 0 +#define MEMSET_PAE_PGTL_ALIGN 0 +#define MEMSET_PAE_PGTL_SIZE 0 +#define MEMSET_PAE_PGTL_SIZE 0 +#define MEMSET_PAE_VMEM_ALIGN 0 +#endif + +#include <memrange.h> +#include <bootmem.h> +#include <bootstate.h> +#include <symbols.h> +#include <console/console.h> +#include <arch/memory_clear.h> +#include <string.h> +#include <security/memory/memory.h> +#include <cbmem.h> +#include <arch/acpi.h> + +/* Helper to find free space for memset_pae. */ +static uintptr_t get_free_memory_range(struct memranges *mem, + const resource_t align, + const resource_t size) +{ + const struct range_entry *r; + + /* Find a spot for virtual memory address */ + memranges_each_entry(r, mem) { + if (range_entry_tag(r) != BM_MEM_RAM) + continue; + + if (ALIGN_UP(range_entry_base(r) + size, align) + size > + range_entry_end(r)) + continue; + + return ALIGN_UP(range_entry_base(r) + size, align); + } + printk(BIOS_ERR, "%s: Couldn't find free memory range\n", __func__); + + return 0; +} + +/* + * Clears all memory regions marked as BM_MEM_RAM. + * Uses memset_pae if the memory region can't be accessed by memset and + * architecture is x86. + * + * @return 0 on success, 1 on error + */ +static void clear_memory(void *unused) +{ + const struct range_entry *r; + struct memranges mem; + uintptr_t pgtbl, vmem_addr; + + if (acpi_is_wakeup_s3()) + return; + + if (!security_clear_dram_request()) + return; + + /* FSP1.0 is marked as MMIO and won't appear here */ + + memranges_init(&mem, IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED | + IORESOURCE_CACHEABLE, + IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED | + IORESOURCE_CACHEABLE, + BM_MEM_RAM); + + /* Add reserved entries */ + void *baseptr = NULL; + size_t size = 0; + + /* Only skip CBMEM, as RELOCATABLE_RAMSTAGE is a requirement, no need + * to separately protect stack or heap */ + + cbmem_get_region(&baseptr, &size); + memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE); + + if (CONFIG(PLATFORM_USES_FSP1_0)) { + /* Protect CBMEM pointer */ + memranges_insert(&mem, CBMEM_FSP_HOB_PTR, sizeof(void *), + BM_MEM_TABLE); + } + + if (CONFIG(ARCH_X86)) { + /* Find space for PAE enabled memset */ + pgtbl = get_free_memory_range(&mem, MEMSET_PAE_PGTL_ALIGN, + MEMSET_PAE_PGTL_SIZE); + + /* Don't touch page tables while clearing */ + memranges_insert(&mem, pgtbl, MEMSET_PAE_PGTL_SIZE, + BM_MEM_TABLE); + + vmem_addr = get_free_memory_range(&mem, MEMSET_PAE_VMEM_ALIGN, + MEMSET_PAE_PGTL_SIZE); + + printk(BIOS_SPEW, "%s: pgtbl at %p, virt memory at %p\n", + __func__, (void *)pgtbl, (void *)vmem_addr); + } + + /* Now clear all useable DRAM */ + memranges_each_entry(r, &mem) { + if (range_entry_tag(r) != BM_MEM_RAM) + continue; + printk(BIOS_DEBUG, "%s: Clearing DRAM %016llx-%016llx\n", + __func__, range_entry_base(r), range_entry_end(r)); + + /* Does regular memset work? */ + if (!(range_entry_end(r) >> sizeof(void *) * 8)) { + /* fastpath */ + memset((void *)(uintptr_t)range_entry_base(r), 0, + range_entry_size(r)); + } + /* Use PAE if available */ + else if (CONFIG(ARCH_X86)) { + if (memset_pae(range_entry_base(r), 0, + range_entry_size(r), (void *)pgtbl, + (void *)vmem_addr)) + printk(BIOS_ERR, "%s: Failed to memset " + "memory\n", __func__); + } else { + printk(BIOS_ERR, "%s: Failed to memset memory\n", + __func__); + } + } + + if (CONFIG(ARCH_X86)) { + /* Clear previously skipped memory reserved for pagetables */ + printk(BIOS_DEBUG, "%s: Clearing DRAM %016lx-%016lx\n", + __func__, pgtbl, pgtbl + MEMSET_PAE_PGTL_SIZE); + + memset((void *)pgtbl, 0, MEMSET_PAE_PGTL_SIZE); + } + + memranges_teardown(&mem); +} + +/* After DEV_INIT as MTRRs needs to be configured on x86 */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, clear_memory, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Philipp Deppenwiese (Code Review) 02 Jul '19

02 Jul '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31549 ) Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... cpu/x86/pae/pgtbl: Add memset with PAE To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation as well. Required for clearing all system memory as part of security API. Tested on wedge100s: Takes less than 2 seconds to clear 8GiB of DRAM. Tested on P8H61M-Pro: Takes less than 1 second to clear 4GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/arch/x86/index.md A Documentation/arch/x86/pae.md M Documentation/security/memory_clearing.md M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 5 files changed, 173 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 3ecb980..73c9823 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -2,6 +2,8 @@ This section contains documentation about coreboot on x86 architecture. +* [x86 PAE support](pae.md) + ## State of x86_64 support At the moment there's no single board that supports x86_64 or to be exact `ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`. diff --git a/Documentation/arch/x86/pae.md b/Documentation/arch/x86/pae.md new file mode 100644 index 0000000..54cd82f --- /dev/null +++ b/Documentation/arch/x86/pae.md @@ -0,0 +1,15 @@ +# x86_32 PAE documentation + +Due to missing x86_64 support it's required to use PAE enabled x86_32 code. +The corresponding functions can be found in ``src/cpu/x86/pae/``. + +## Memory clearing helper functions + +To clear all DRAM on request of the +[Security API](../../security/memory_clearing.md), a helper function can be used +called `memset_pae`. +The function has additional requirements in contrast to `memset`, and has more +overhead as it uses virtual memory to access memory above 4GiB. +Memory is cleared in 2MiB chunks, which might take a while. + +Make sure to enable caches through MTRRs, otherwise `memset_pae` will be slow! diff --git a/Documentation/security/memory_clearing.md b/Documentation/security/memory_clearing.md index 3d98592..e5c1925 100644 --- a/Documentation/security/memory_clearing.md +++ b/Documentation/security/memory_clearing.md @@ -42,3 +42,7 @@ As some platforms place code and stack in DRAM (FSP1.0), the regions can be skipped. + +## Architecture specific implementations + +* [x86 PAE](../arch/x86/pae.md) diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 9c92134..f54a1c3 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2005 Yinghai Lu + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +24,7 @@ #include <cpu/x86/pae.h> #include <string.h> #include <symbols.h> +#include <assert.h> #define PDPTE_PRES (1ULL << 0) #define PDPTE_ADDR_MASK (~((1ULL << 12) - 1)) @@ -59,9 +62,20 @@ #define PTE_IDX_SHIFT 12 #define PTE_IDX_MASK 0x1ff +#define OVERLAP(a, b, s, e) ((b) > (s) && (a) < (e)) + static const size_t s2MiB = 2 * MiB; static const size_t s4KiB = 4 * KiB; +struct pde { + uint32_t addr_lo; + uint32_t addr_hi; +} __packed; +struct pg_table { + struct pde pd[2048]; + struct pde pdp[512]; +} __packed; + void paging_enable_pae_cr3(uintptr_t cr3) { /* Load the page table address */ @@ -101,6 +115,119 @@ write_cr4(cr4); } +/* + * Use PAE to map a page and then memset it with the pattern specified. + * In order to use PAE pagetables for virtual addressing are set up and reloaded + * on a 2MiB boundary. After the function is done, virtual addressing mode is + * disabled again. The PAT are set to all cachable, but MTRRs still apply. + * + * Requires a scratch memory for pagetables and a virtual address for + * non identity mapped memory. + * + * The scratch memory area containing pagetables must not overlap with the + * memory range to be cleared. + * The scratch memory area containing pagetables must not overlap with the + * virtual address for non identity mapped memory. + * + * @param vmem_addr Where the virtual non identity mapped page resides, must + * be 2 aligned MiB and at least 2 MiB in size. + * Content at physical address is preserved. + * @param pgtbl Where pagetables reside, must be 4 KiB aligned and 20 KiB in + * size. + * Must not overlap memory range pointed to by dest. + * Must not overlap memory range pointed to by vmem_addr. + * Content at physical address isn't preserved. + * @param length The length of the memory segment to memset + * @param dest Physical memory address to memset + * @param pat The pattern to write to the pyhsical memory + * @return 0 on success, 1 on error + */ +int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, + void *vmem_addr) +{ + struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl; + ssize_t offset; + + printk(BIOS_DEBUG, "%s: Using virtual address %p as scratchpad\n", + __func__, vmem_addr); + printk(BIOS_DEBUG, "%s: Using address %p for page tables\n", + __func__, pgtbl_buf); + + /* Cover some basic error conditions */ + if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB) || + !IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) { + printk(BIOS_ERR, "%s: Invalid alignment\n", __func__); + return 1; + } + const uintptr_t pgtbl_s = (uintptr_t)pgtbl_buf; + const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table); + + if (OVERLAP(dest, dest + length, pgtbl_s, pgtbl_e)) { + printk(BIOS_ERR, "%s: destination overlaps page tables\n", + __func__); + return 1; + } + + if (OVERLAP((uintptr_t)vmem_addr, (uintptr_t)vmem_addr + s2MiB, + pgtbl_s, pgtbl_e)) { + printk(BIOS_ERR, "%s: vmem address overlaps page tables\n", + __func__); + return 1; + } + + paging_disable_pae(); + + struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp; + /* Point the page directory pointers at the page directories. */ + memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp)); + + pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES; + pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES; + pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES; + pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES; + + offset = dest - ALIGN_DOWN(dest, s2MiB); + dest = ALIGN_DOWN(dest, s2MiB); + + /* Identity map the whole 32-bit address space */ + for (size_t i = 0; i < 2048; i++) { + pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW; + pd[i].addr_hi = 0; + } + + /* Get pointer to PD that's not identity mapped */ + pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT]; + + paging_enable_pae_cr3((uintptr_t)pdp); + + do { + const size_t len = MIN(length, s2MiB - offset); + + /* + * Map a page using PAE at virtual address vmem_addr. + * dest is already 2 MiB aligned. + */ + pd->addr_lo = dest | PDE_PS | PDE_PRES | PDE_RW; + pd->addr_hi = dest >> 32; + + /* Update page tables */ + asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory"); + + printk(BIOS_SPEW, "%s: Clearing %llx[%lx] - %zx\n", __func__, + dest + offset, (uintptr_t)vmem_addr + offset, len); + + memset(vmem_addr + offset, pat, len); + + dest += s2MiB; + length -= len; + offset = 0; + } while (length > 0); + + paging_disable_pae(); + + return 0; +} + #if ENV_RAMSTAGE void *map_2M_page(unsigned long page) { diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 7627187..72bae53 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -1,3 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef CPU_X86_PAE_H #define CPU_X86_PAE_H @@ -41,4 +57,13 @@ #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); +/* To be used with memset_pae */ +#define MEMSET_PAE_VMEM_ALIGN (2 * MiB) +#define MEMSET_PAE_VMEM_SIZE (2 * MiB) +#define MEMSET_PAE_PGTL_ALIGN (4 * KiB) +#define MEMSET_PAE_PGTL_SIZE (20 * KiB) + +int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, + void *vmem_addr); + #endif /* CPU_X86_PAE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/hatch/variants: Touch pad no function
by EricR Lai (Code Review) 02 Jul '19

02 Jul '19

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Touch pad no function ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/33954/1/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/baseboard/devicetree.cb: https://review.coreboot.org/#/c/33954/1/src/mainboard/google/hatch/variants… PS1, Line 98: register "gpio_pm[COMM_0]" = "0" change in board level override https://review.coreboot.org/#/c/33954/1/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/33954/1/src/mainboard/google/hatch/variants… PS1, Line 62: PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, NONE), you should change in board level gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Jul 2019 08:11:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update Spd sources
by Kane Chen (Code Review) 02 Jul '19

02 Jul '19

Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update Spd sources ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: Code-Review-1 > > > > (1 comment) > The DRAM ID table at Proto stage is > > ID 0 Samsung 16Gb 2133MT/s K4E6E304EC/ED-EGCG > ID 1 Samsung 32Gb 2133MT/s K4EB304ED-EGCG > ID 2 Hynix 8Gb 2133MT/s H9CCNNN8GTALAR-NVD > ID 3 Hynix 16Gb 2133MT/s H9CCNNNBJTALAR-NVD > ID 4 Hynix 32Gb 2133MT/s H9CCNNNCLGALAR-NVD > > According to Intel's feedback , current SPD support the same capacity and speed with different brand , so ID 0 and ID 3 use 1 SPD file . ID 1 and ID 4 use another SPD file . who did you contact, i didn't reply you mail about this before -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Jul 2019 07:15:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants: Touch pad no function
by Aamir Bohra (Code Review) 02 Jul '19

02 Jul '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Touch pad no function ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/33954/1/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/baseboard/devicetree.cb: https://review.coreboot.org/#/c/33954/1/src/mainboard/google/hatch/variants… PS1, Line 98: register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_2]" = "0" : register "gpio_pm[COMM_3]" = "0" was this required? -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Jul 2019 07:10:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove variable length arrays
by Patrick Rudolph (Code Review) 02 Jul '19

02 Jul '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33821 ) Change subject: src: Remove variable length arrays ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c: https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c@103 PS8, Line 103: #pragma GCC diagnostic ignored "-Wvla" > > This driver is used in all stages, so no malloc(). […] I'm happy to help out and test on cn81xx, but I'm out of office for the next weeks, so I can't test on real hardware. -- To view, visit https://review.coreboot.org/c/coreboot/+/33821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Gerrit-Change-Number: 33821 Gerrit-PatchSet: 8 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 06:41:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update Spd sources
by Ken Lu (Code Review) 02 Jul '19

02 Jul '19

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update Spd sources ...................................................................... Patch Set 1: > Patch Set 1: Code-Review-1 > > (1 comment) The DRAM ID table at Proto stage is ID 0 Samsung 16Gb 2133MT/s K4E6E304EC/ED-EGCG ID 1 Samsung 32Gb 2133MT/s K4EB304ED-EGCG ID 2 Hynix 8Gb 2133MT/s H9CCNNN8GTALAR-NVD ID 3 Hynix 16Gb 2133MT/s H9CCNNNBJTALAR-NVD ID 4 Hynix 32Gb 2133MT/s H9CCNNNCLGALAR-NVD According to Intel's feedback , current SPD support the same capacity and speed with different brand , so ID 0 and ID 3 use 1 SPD file . ID 1 and ID 4 use another SPD file . -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Jul 2019 06:13:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/superiotool/nuvoton.c: Minor tag update/removal
by Pavel Sayekat (Code Review) 02 Jul '19

02 Jul '19

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33910 Change subject: util/superiotool/nuvoton.c: Minor tag update/removal ...................................................................... util/superiotool/nuvoton.c: Minor tag update/removal Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6 --- M util/superiotool/nuvoton.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/33910/1 diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 7552244..81bff96 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -594,7 +594,7 @@ {0x05, "Keyboard Controller", {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, - {0x06, "CIR", + {0x06, "Consumer IR", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, {0x07, "GPIO 7, GPIO 8", @@ -622,7 +622,7 @@ {0x00,0x00,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x7f,0xa8, 0x08,0x7f,0x00,0x81,0x00,0x00,0x00,0x00,0x87,0x47, 0x00,0x00,0x00,0x02,EOT}}, - {0x0d, "BCLK, WDT2", + {0x0d, "WDT2", {0xe7,0xe8,0xeb,0xed,0xf0,0xf3,EOT}, {0x10,0x32,0x14,0x00,0x00,0x00,EOT}}, {0x0e, "CIR Wake-Up", -- To view, visit https://review.coreboot.org/c/coreboot/+/33910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6 Gerrit-Change-Number: 33910 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update Spd sources
by Furquan Shaikh (Code Review) 02 Jul '19

02 Jul '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update Spd sources ...................................................................... Patch Set 1: Code-Review-1 (1 comment) https://review.coreboot.org/#/c/33953/1/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/helios/Makefile.inc: https://review.coreboot.org/#/c/33953/1/src/mainboard/google/hatch/variants… PS1, Line 18: SPD_SOURCES += LP_8G_2133 # 0b0011 : SPD_SOURCES += LP_16G_2133 # 0b0100 Why are these required? ID 0 and 1 are exactly the same as what you are adding for 3 and 4. -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Jul 2019 03:02:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2019