coreboot-gerrit July 2019

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Change in ...coreboot[master]: src: Remove variable length arrays
by Aaron Durbin (Code Review) 01 Jul '19

01 Jul '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33821 ) Change subject: src: Remove variable length arrays ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c: https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c@103 PS8, Line 103: #pragma GCC diagnostic ignored "-Wvla" > This driver is used in all stages, so no malloc(). In theory this should be really easy to solve because our SPI API is a pure byte pushing API that controls CS independently, so xfer(cmd <concatenated with> data); should just be equivalent to { xfer(cmd); xfer(data); }. In practice, however, there are a lot of weird Intel and AMD controllers that are not really generic SPI controllers but rather specific SPI NOR flash controllers but were still implemented using the generic controller API. They expect that every xfer() they get sent is a whole SPI command (e.g. they inspect dout[0] and expect that it must be a SPI flash opcode). > > I think the only clean solution here would be to make all those drivers that aren't actually SPI controllers stop using the generic SPI API, and instead make them implement custom flash read/write ops by overriding .flash_probe() (like some more recent drivers for special controllers such as Intel fast_spi or the MT8173 flash controller already do). Then we rewrite this cleanly and mandate that from then on forward, drivers shouldn't implement the generic SPI API unless they can actually handle it. But there are a lot of old drivers like this (I think basically everything that implements xfer_vector, which we could remove if we fix them all), so this would be a lot of work (although most of these were copied from each other and are very similar... I think for the most part there's just 6 versions of the Intel controller and 4 versions of the AMD controller). > > A hackier but less complicated option might be to add a new SPI_CNTRLR flag for all these controllers and then make only them run the dangerous code, while other ones could run a safer version. > > +Aaron, what do you think? I think the answer is the 2nd paragraph. For the fixed function spi flash controllers make sure they are implemented according to their semantics. i.e. struct spi_flash->ops should be filled in with special ops corresponding to the controllers' implementations. e.g. src/soc/intel/common/block/fast_spi/fast_spi_flash.c I think the list of things to cutover are any users of spi_flash_vector_helper(). The xfer_vector as you noted is a good proxy as well. The cn81xx spi driver is the odd one out: $ git grep -l xfer_vector src/drivers/spi/spi-generic.c src/drivers/spi/spi_flash.c src/include/spi-generic.h src/soc/amd/stoneyridge/spi.c src/soc/cavium/cn81xx/spi.c src/soc/intel/baytrail/spi.c src/soc/intel/braswell/spi.c src/soc/intel/broadwell/spi.c src/soc/intel/fsp_baytrail/spi.c src/soc/qualcomm/qcs405/spi.c src/southbridge/amd/agesa/hudson/spi.c src/southbridge/amd/cimx/sb800/spi.c src/southbridge/amd/sb700/spi.c src/southbridge/intel/common/spi.c src/southbridge/intel/fsp_rangeley/spi.c $ git grep -l spi_flash_vector_helper src/drivers/spi/spi_flash.c src/include/spi_flash.h src/soc/amd/stoneyridge/spi.c src/soc/intel/baytrail/spi.c src/soc/intel/braswell/spi.c src/soc/intel/broadwell/spi.c src/soc/intel/fsp_baytrail/spi.c src/soc/qualcomm/qcs405/spi.c src/southbridge/amd/agesa/hudson/spi.c src/southbridge/amd/cimx/sb800/spi.c src/southbridge/amd/sb700/spi.c src/southbridge/intel/common/spi.c src/southbridge/intel/fsp_rangeley/spi.c I think having cn81xx just implement xfer would be the fix for its xfer_vector usage. Added a tracking bug here: https://ticket.coreboot.org/issues/217 -- To view, visit https://review.coreboot.org/c/coreboot/+/33821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Gerrit-Change-Number: 33821 Gerrit-PatchSet: 8 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Jul 2019 20:59:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd: Update ACPI code
by Richard Spiegel (Code Review) 01 Jul '19

01 Jul '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33620 Change subject: soc/amd: Update ACPI code ...................................................................... soc/amd: Update ACPI code In preparation to adding merlinfalcon SOC, update ACPI code: Update OSVL (old code does not test for anything newer than WINXP). Update cpu.asl to accept SOC with up to 4 cores. Update lpc.asl to avoid a bug with WIN7 and WIN10. Notice: Fixes are needed (later patch), as Windows still fails (not fully ACPI compatible). Currently only Linux was tested and worked. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: Id3615a4460dd4e0c95e890a38210263dd8ea6887 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/acpi/lpc.asl M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 3 files changed, 153 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/33620/1 diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl index 93b4056..0844a9a 100644 --- a/src/soc/amd/common/acpi/lpc.asl +++ b/src/soc/amd/common/acpi/lpc.asl @@ -32,25 +32,29 @@ Offset(0xA0), BAR,32} // SPI Controller Base Address Register (Index 0xA0) - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources - Name (CRS, ResourceTemplate () // Current Motherboard resources + /* PNP0C02 apparently fails with WIN77 and WIN10. Until better + * understood, block LDRC for these two OS */ + if(LLess(OSVR, 0x06)) { + Device(LDRC) // LPC device: Resource consumption { - Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address - 0x00000000, // Address Base - 0x00000000, // Address Length - BAR0 // Descriptor Name - ) - }) + Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources + Name (CRS, ResourceTemplate () // Current Motherboard resources + { + Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address + 0x00000000, // Address Base + 0x00000000, // Address Length + BAR0 // Descriptor Name + ) + }) - Method(_CRS,0,Serialized) - { - CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address - CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length - Store(BAR,SPIB) // SPI base address mapped - Store(0x1000,SPIL) // 4k space mapped - Return(CRS) + Method(_CRS,0,Serialized) + { + CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address + CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length + Store(BAR,SPIB) // SPI base address mapped + Store(0x1000,SPIL) // 4k space mapped + Return(CRS) + } } } diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 414326e..aa59040 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -34,7 +34,27 @@ /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 2)) { + If (LGreaterEqual (\PCNT, 8)) { + Return (Package () + { + \_PR.P000, + \_PR.P001, + \_PR.P002, + \_PR.P003, + \_PR.P004, + \_PR.P005, + \_PR.P006, + \_PR.P007 + }) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.P000, + \_PR.P001, + \_PR.P002, + \_PR.P003 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { \_PR.P000, diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 3623814..90000e6 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -175,27 +175,125 @@ } /* End Method(_SB._INI) */ -Method(OSFL, 0){ - - if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if (CondRefOf(\_OSI)) +Method(OSFL, 0, NotSerialized) +{ + If(LNotEqual(OSVR, Ones)) { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ + Return(OSVR) + } + Store(0x03, OSVR) + If(CondRefOf(\_OSI, Local0)) + { + If(_OSI("Windows 2001")) { - Store(2, OSVR) + Store(0x04, OSVR) } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ + If(_OSI("Windows 2001.1")) + { + Store(0x05, OSVR) + } + If(_OSI("FreeBSD")) + { + Store(0x06, OSVR) + } + If(_OSI("HP-UX")) + { + Store(0x07, OSVR) + } + If(_OSI("OpenVMS")) + { + Store(0x08, OSVR) + } + If(_OSI("Windows 2001 SP1")) + { + Store(0x09, OSVR) + } + If(_OSI("Windows 2001 SP2")) + { + Store(0x0A, OSVR) + } + If(_OSI("Windows 2001 SP3")) + { + Store(0x0B, OSVR) + } + If(_OSI("Windows 2006")) + { + Store(0x0C, OSVR) + } + If(_OSI("Windows 2006 SP1")) + { + Store(0x0D, OSVR) + } + If(_OSI("Windows 2009")) + { + Store(0x0E, OSVR) + } + If(_OSI("Windows 2012")) + { + Store(0x0F, OSVR) + } + If(_OSI("Windows 2013")) + { + Store(0x10, OSVR) + } + } + Else + { + Store (\_OS, local0) + If(MCTH(local0, "Microsoft Windows NT")) + { + Store(Zero, OSVR) + } + If(MCTH(local0, "Microsoft Windows")) + { + Store(One, OSVR) + } + If(MCTH(local0, "Microsoft WindowsME: Millennium Edition")) + { + Store(0x02, OSVR) + } + If(MCTH(local0, "Linux")) + { + Store(0x03, OSVR) + } + If(MCTH(local0, "FreeBSD")) + { + Store(0x06, OSVR) + } + If(MCTH(local0, "HP-UX")) + { + Store(0x07, OSVR) + } + If(MCTH(local0, "OpenVMS")) + { + Store(0x08, OSVR) } } Return(OSVR) } +Method(MCTH, 2, Serialized) +{ + If(LLess(SizeOf(Arg0), SizeOf(Arg1))) + { + Return(Zero) + } + Add(SizeOf(Arg0), One, Local0) + Name(BUF0, Buffer(Local0){}) + Name(BUF1, Buffer(Local0){}) + Store(Arg0, BUF0) + Store(Arg1, BUF1) + While(Local0) + { + Decrement(Local0) + If(LNotEqual(DerefOf(Index(BUF0, Local0)), DerefOf(Index(BUF1, Local0)))) + { + Return(Zero) + } + } + Return(One) +} + OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) Field( SMIC, ByteAcc, NoLock, Preserve) { /* MISC registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3615a4460dd4e0c95e890a38210263dd8ea6887 Gerrit-Change-Number: 33620 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Kconfig: Enable RAMPAYLOAD for x86
by Subrata Banik (Code Review) 01 Jul '19

01 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33859 Change subject: Kconfig: Enable RAMPAYLOAD for x86 ...................................................................... Kconfig: Enable RAMPAYLOAD for x86 This patch makes CONFIG_RAMPAYLOAD default enable upon selection of HAVE_RAMPAYLOAD kconfig from mainboard for x86 platform. Without this CL, CONFIG_RAMPAYLOAD is still disable although mainboard has selected CONFIG_HAVE_RAMPAYLOAD. Change-Id: I40308bbf970a0dbe5f7e2086ed8a7a70c2a3a32c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33859/1 diff --git a/src/Kconfig b/src/Kconfig index 72d826f..919d257 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -290,7 +290,7 @@ config RAMPAYLOAD bool "Enable coreboot flow without executing ramstage" - default n + default y if ARCH_X86 depends on HAVE_RAMPAYLOAD help If this option is enabled, coreboot flow will skip ramstage -- To view, visit https://review.coreboot.org/c/coreboot/+/33859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40308bbf970a0dbe5f7e2086ed8a7a70c2a3a32c Gerrit-Change-Number: 33859 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/pci_ops: Define pci_find_capability() just once
by Martin Roth (Code Review) 01 Jul '19

01 Jul '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31755 ) Change subject: device/pci_ops: Define pci_find_capability() just once ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Gerrit-Change-Number: 31755 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Jul 2019 15:00:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/sconfig: Add commonlib/helpers.h
by Martin Roth (Code Review) 01 Jul '19

01 Jul '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31932 ) Change subject: util/sconfig: Add commonlib/helpers.h ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcaa1b613aef312d3876e8b536499a9f01a8d19 Gerrit-Change-Number: 31932 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Jul 2019 14:56:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/ifdtool: Enable -Wmissing-prototypes
by Jacob Garber (Code Review) 01 Jul '19

01 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33861 Change subject: util/ifdtool: Enable -Wmissing-prototypes ...................................................................... util/ifdtool: Enable -Wmissing-prototypes Change-Id: Idc31144024f785a42cbad78bf2c965d08dcc5178 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M util/ifdtool/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33861/1 diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index e1188b2..4cddfc5 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -18,7 +18,7 @@ CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -W -Werror -I../../src/commonlib/include +CFLAGS = -O2 -g -Wall -W -Wmissing-prototypes -Werror -I../../src/commonlib/include LDFLAGS = OBJS = ifdtool.o -- To view, visit https://review.coreboot.org/c/coreboot/+/33861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc31144024f785a42cbad78bf2c965d08dcc5178 Gerrit-Change-Number: 33861 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/ifdtool: Make internal functions static
by Jacob Garber (Code Review) 01 Jul '19

01 Jul '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33860 Change subject: util/ifdtool: Make internal functions static ...................................................................... util/ifdtool: Make internal functions static These functions are only used in ifdtool, so they can be made static. Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M util/ifdtool/ifdtool.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/33860/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a1a327f..83caa69 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1067,7 +1067,7 @@ } /* Set the AltMeDisable (or HAP for >= IFD_VERSION_2) */ -void fpsba_set_altmedisable(fpsba_t *fpsba, fmsba_t *fmsba, bool altmedisable) +static void fpsba_set_altmedisable(fpsba_t *fpsba, fmsba_t *fmsba, bool altmedisable) { if (ifd_version >= IFD_VERSION_2) { printf("%sting the HAP bit to %s Intel ME...\n", @@ -1107,7 +1107,7 @@ } } -void inject_region(const char *filename, char *image, int size, +static void inject_region(const char *filename, char *image, int size, unsigned int region_type, const char *region_fname) { frba_t *frba = find_frba(image, size); @@ -1173,7 +1173,7 @@ write_image(filename, image, size); } -unsigned int next_pow2(unsigned int x) +static unsigned int next_pow2(unsigned int x) { unsigned int y = 1; if (x == 0) @@ -1200,7 +1200,7 @@ return !(r1->limit < r2->base || r1->base > r2->limit); } -void new_layout(const char *filename, char *image, int size, +static void new_layout(const char *filename, char *image, int size, const char *layout_fname) { FILE *romlayout; -- To view, visit https://review.coreboot.org/c/coreboot/+/33860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7 Gerrit-Change-Number: 33860 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gat...
by Jeremy Soller (Code Review) 01 Jul '19

01 Jul '19

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31534 Change subject: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter ...................................................................... soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31534/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..534065f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -128,6 +128,10 @@ /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = config->clock_gate_8254; + params->Enable8254ClockGatingOnS3 = config->clock_gate_8254; + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); -- To view, visit https://review.coreboot.org/c/coreboot/+/31534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e Gerrit-Change-Number: 31534 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/ifittool: used strtol function instead of atoi
by Varshit B Pandya (Code Review) 01 Jul '19

01 Jul '19

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33937 Change subject: util/cbfstool/ifittool: used strtol function instead of atoi ...................................................................... util/cbfstool/ifittool: used strtol function instead of atoi atoi doesnot parse hex string, for instance 0x200 is interpreted as 0, and this causes a failure when updating second FIT table using -j option. Use strtol instead of atoi BUG=none BRANCH=none TEST=Build and boot hatch after enabling dual bootblock feature. Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M util/cbfstool/ifittool.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33937/1 diff --git a/util/cbfstool/ifittool.c b/util/cbfstool/ifittool.c index a83fd96..3b16c3f 100644 --- a/util/cbfstool/ifittool.c +++ b/util/cbfstool/ifittool.c @@ -28,7 +28,7 @@ /* Global variables */ partitioned_file_t *image_file; -static const char *optstring = "H:j:f:r:d:t:n:s:caDvh?"; +static const char *optstring = "H:j:f:r:d:t:n:s:cAaDvh?"; static struct option long_options[] = { {"file", required_argument, 0, 'f' }, {"region", required_argument, 0, 'r' }, @@ -230,7 +230,7 @@ } break; case 'j': - topswap_size = atoi(optarg); + topswap_size = strtol(optarg, NULL, 0); if (!is_valid_topswap(topswap_size)) return 1; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/33937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7 Gerrit-Change-Number: 33937 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 01 Jul '19

01 Jul '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 39: Re-init the effort to enable MCU update in Chrome platforms. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 39 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 01 Jul 2019 13:27:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2019