coreboot-gerrit July 2019

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Change in ...coreboot[master]: fintek/f81803a: Add new superio - Fintek F81803A
by Felix Held (Code Review) 02 Jul '19

02 Jul '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21032 ) Change subject: fintek/f81803a: Add new superio - Fintek F81803A ...................................................................... Patch Set 9: this patch can be abandoned, since it was superseded by 33623 -- To view, visit https://review.coreboot.org/c/coreboot/+/21032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fb1a1d42d004123c3b12caf26cf0b03cd4046ec Gerrit-Change-Number: 21032 Gerrit-PatchSet: 9 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jul 2019 12:37:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/basecode/fw_update: Add ELOG events to ucode update
by Paul Menzel (Code Review) 02 Jul '19

02 Jul '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29357 ) Change subject: intel/basecode/fw_update: Add ELOG events to ucode update ...................................................................... Patch Set 17: (4 comments) https://review.coreboot.org/#/c/29357/17/src/soc/intel/common/basecode/fw_u… File src/soc/intel/common/basecode/fw_update/elog.h: https://review.coreboot.org/#/c/29357/17/src/soc/intel/common/basecode/fw_u… PS17, Line 21: * @current : Current microcode revision. Please remove the dot/period at the end. https://review.coreboot.org/#/c/29357/17/src/soc/intel/common/basecode/fw_u… PS17, Line 24: Update update https://review.coreboot.org/#/c/29357/17/src/soc/intel/common/basecode/fw_u… PS17, Line 26: * return 0 on success, -1 on failure. Please use CB_SUCCESS and friends. https://review.coreboot.org/#/c/29357/17/src/soc/intel/common/basecode/fw_u… File src/soc/intel/common/basecode/fw_update/elog.c: https://review.coreboot.org/#/c/29357/17/src/soc/intel/common/basecode/fw_u… PS17, Line 18: #include "elog.h" Both are needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/29357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Gerrit-Change-Number: 29357 Gerrit-PatchSet: 17 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 12:06:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Update macro definition in CB clock driver
by Paul Menzel (Code Review) 02 Jul '19

02 Jul '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33811 ) Change subject: sdm845: Update macro definition in CB clock driver ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba Gerrit-Change-Number: 33811 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jul 2019 11:47:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update SPD sources
by Ken Lu (Code Review) 02 Jul '19

02 Jul '19

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update SPD sources ...................................................................... Patch Set 2: > Patch Set 1: > > (2 comments) Line 7 : SPD Done . Line 9 : Currently , there is no 8Gb 2133MT/s SPD setting come out yet. Stay empty here. -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 11:35:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update SPD sources
by Ken Lu (Code Review) 02 Jul '19

02 Jul '19

Ken Lu has uploaded a new patch set (#2) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update SPD sources ...................................................................... mb/google/hatch/variants/helios: Update SPD sources Add SPD_SOURCES "empty_ddr4", "LP_8G_2133" and "LP_16G_2133" to Makefile.inc. BUG=b:133455595 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 --- M src/mainboard/google/hatch/variants/helios/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33953/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update Spd sources
by Paul Menzel (Code Review) 02 Jul '19

02 Jul '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update Spd sources ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/33953/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/33953/1//COMMIT_MSG@7 PS1, Line 7: Spd SPD https://review.coreboot.org/#/c/33953/1//COMMIT_MSG@9 PS1, Line 9: Add SPD_SOURCES "empty_ddr4", "LP_8G_2133" and "LP_16G_2133" to Makefile.inc. Please add the motivation for this change to the commit messages. Why is empty_ddr4 needed for example? -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 11:21:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants: Touch pad no function
by Paul Menzel (Code Review) 02 Jul '19

02 Jul '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Touch pad no function ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/#/c/33954/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/33954/3//COMMIT_MSG@7 PS3, Line 7: mb/google/hatch/variants: Touch pad no function Please make it a statement. > Fix nonworking touch pad https://review.coreboot.org/#/c/33954/3//COMMIT_MSG@9 PS3, Line 9: Modify GPP_A21 to interrupt and disables PM configuration on all GPIO communities. Please wrap the line after 75 characters. https://review.coreboot.org/#/c/33954/3//COMMIT_MSG@9 PS3, Line 9: disables disable -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jul 2019 11:19:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update Spd sources
by Frank Chu (Code Review) 02 Jul '19

02 Jul '19

Frank Chu has removed Kane Chen from this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update Spd sources ...................................................................... Removed reviewer Kane Chen. -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update Spd sources
by Frank Chu (Code Review) 02 Jul '19

02 Jul '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update Spd sources ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > > Patch Set 1: Code-Review-1 > > > > > > (1 comment) > > The DRAM ID table at Proto stage is > > > > ID 0 Samsung 16Gb 2133MT/s K4E6E304EC/ED-EGCG > > ID 1 Samsung 32Gb 2133MT/s K4EB304ED-EGCG > > ID 2 Hynix 8Gb 2133MT/s H9CCNNN8GTALAR-NVD > > ID 3 Hynix 16Gb 2133MT/s H9CCNNNBJTALAR-NVD > > ID 4 Hynix 32Gb 2133MT/s H9CCNNNCLGALAR-NVD > > > > According to Intel's feedback , current SPD support the same capacity and speed with different brand , so ID 0 and ID 3 use 1 SPD file . ID 1 and ID 4 use another SPD file . > > who did you contact, i didn't reply you mail about this before sorry,i add wrong contact windows, i will remove you -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Jul 2019 09:34:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci_rom: Fix redundant pci_rom_probe() calls
by Kyösti Mälkki (Code Review) 02 Jul '19

02 Jul '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33909 ) Change subject: device/pci_rom: Fix redundant pci_rom_probe() calls ...................................................................... device/pci_rom: Fix redundant pci_rom_probe() calls For the PCI_VENDOR_ID_ATI case, we can rely on pci_rom_acpi_fill_vfct() to make the call if necessary. For hardware other than ATI, pci_rom_probe() was already called from pci_rom_ssdt() and pci_dev_init(), so PCI_ROM_ADDRESS BAR is already enabled, if requested so. Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Mike Banon <mikebdp2(a)gmail.com> --- M src/arch/x86/acpi.c M src/device/pci_rom.c 2 files changed, 13 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Mike Banon: Looks good to me, approved diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 80923e3..8ab993e 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -763,11 +763,14 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = asl_revision; - header->length = sizeof(struct acpi_vfct); header->revision = get_acpi_table_revision(VFCT); current = acpi_fill_vfct(device, vfct, current); + /* If no BIOS image, return with header->length == 0. */ + if (!vfct->VBIOSImageOffset) + return; + /* (Re)calculate length and checksum. */ header->length = current - (unsigned long)vfct; header->checksum = acpi_checksum((void *)vfct, header->length); diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 7322e57..31fe115 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -209,8 +209,6 @@ struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; struct rom_header *rom; - vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; - rom = check_initialized(device); if (!rom) rom = pci_rom_probe(device); @@ -233,6 +231,8 @@ header->ImageLength = rom->size * 512; memcpy((void *)&header->VbiosContent, rom, header->ImageLength); + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + current += header->ImageLength; return current; } @@ -241,9 +241,6 @@ pci_rom_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - struct acpi_vfct *vfct; - struct rom_header *rom; - /* Only handle VGA devices */ if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) return current; @@ -252,19 +249,18 @@ if (!device->enabled) return current; - /* Probe for option rom */ - rom = pci_rom_probe(device); - if (!rom) - return current; - /* AMD/ATI uses VFCT */ if (device->vendor == PCI_VENDOR_ID_ATI) { + struct acpi_vfct *vfct; + current = ALIGN_UP(current, 8); - printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); vfct = (struct acpi_vfct *)current; acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); - current += vfct->header.length; - acpi_add_table(rsdp, vfct); + if (vfct->header.length) { + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } } return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/33909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f Gerrit-Change-Number: 33909 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2019