coreboot-gerrit July 2019

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Change in ...coreboot[master]: intel/basecode/fw_update: Add ELOG events to ucode update
by Rizwan Qureshi (Code Review) 01 Jul '19

01 Jul '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29357 to look at the new patch set (#17). Change subject: intel/basecode/fw_update: Add ELOG events to ucode update ...................................................................... intel/basecode/fw_update: Add ELOG events to ucode update Add ELOG entries for ucode update module. TEST=verified that the eventlog shows event 0xb2 1 | 2018-10-30 06:06:52 | System boot | 161 2 | 2018-10-30 06:06:52 | Unknown | 0xb2 3 | 2018-10-30 06:07:09 | System boot | 162 Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/include/elog.h M src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/elog.c A src/soc/intel/common/basecode/fw_update/elog.h M src/soc/intel/common/basecode/fw_update/ucode_update.c 5 files changed, 83 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29357/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/29357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Gerrit-Change-Number: 29357 Gerrit-PatchSet: 17 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 01 Jul '19

01 Jul '19

Hello Patrick Rudolph, Aaron Durbin, dhaval v sharma, Subrata Banik, Patrick Rudolph, Paul Menzel, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27369 to look at the new patch set (#39). Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If so, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config TOP_SWAP_BASED_VBOOT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sue that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 4 files changed, 257 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 39 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/apl: Add devicetreee options for root ports
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32011 Change subject: soc/apl: Add devicetreee options for root ports ...................................................................... soc/apl: Add devicetreee options for root ports List of options: - PcieRpPmSci - PcieRpTransmitterHalfSwing - PcieRpLtrMaxSnoopLatency - PcieRpLtrMaxNonSnoopLatency - PcieRpAspm Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32011/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..8b38895 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -695,6 +695,24 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + memcpy(silconfig->PcieRpPmSci, cfg->pcie_rp_pm_sci, + sizeof(silconfig->PcieRpPmSci)); + + memcpy(silconfig->PcieRpTransmitterHalfSwing, + cfg->pcie_rp_transmitter_halfswing, + sizeof(silconfig->PcieRpTransmitterHalfSwing)); + + memcpy(silconfig->PcieRpLtrMaxSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxSnoopLatency)); + + memcpy(silconfig->PcieRpLtrMaxNonSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxNonSnoopLatency)); + + memcpy(silconfig->PcieRpAspm, cfg->pcie_rp_aspm, + sizeof(silconfig->PcieRpAspm)); + switch (cfg->serirq_mode) { case SERIRQ_QUIET: silconfig->SirqEnable = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/32011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Gerrit-Change-Number: 32011 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add eMMC and Sdcard config options
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32049 Change subject: soc/apl: Add eMMC and Sdcard config options ...................................................................... soc/apl: Add eMMC and Sdcard config options Change-Id: I5e7df076d1e76358de5a899a3a44e8ca864882ba Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32049/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..3a405af 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,9 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->eMMCEnabled = cfg->emmc_enabled; + silconfig->SdcardEnabled = cfg->sdcard_enabled; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..a995f2d 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -120,6 +120,9 @@ /* PL2 override value in mW for APL */ uint16_t tdp_pl2_override_mw; + uint8_t emmc_enabled; + uint8_t sdcard_enabled; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e7df076d1e76358de5a899a3a44e8ca864882ba Gerrit-Change-Number: 32049 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add HdAudioDspUaaCompliance to devicetree
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32047 Change subject: soc/apl: Add HdAudioDspUaaCompliance to devicetree ...................................................................... soc/apl: Add HdAudioDspUaaCompliance to devicetree Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32047/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..5f83906 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,8 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->HdAudioDspUaaCompliance = cfg->hdaudio_dsp_uaa_compliance; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..e3bcfe5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -127,6 +127,8 @@ uint8_t hdaudio_pwr_gate_enable; uint8_t hdaudio_bios_config_lockdown; + uint8_t hdaudio_dsp_uaa_compliance; + /* SLP S3 minimum assertion width. */ int slp_s3_assertion_width_usecs; -- To view, visit https://review.coreboot.org/c/coreboot/+/32047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Gerrit-Change-Number: 32047 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apl: Add C-States configuration options
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32050 Change subject: soc/apl: Add C-States configuration options ...................................................................... soc/apl: Add C-States configuration options FSP-S options: - C1e - PkgCStateLimit - CStateAutoDemotion - CStateUnDemotion - PkgCStateDemotion - PkgCStateUnDemotion Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32050/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..15f2ba8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,13 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->C1e = cfg->c1e; + silconfig->PkgCStateLimit = cfg->pkg_cstate_limit; + silconfig->CStateAutoDemotion = cfg->cstate_auto_demotion; + silconfig->CStateUnDemotion = cfg->cstate_undemotion; + silconfig->PkgCStateDemotion = cfg->pkg_cstate_demotion; + silconfig->PkgCStateUnDemotion = cfg->pkg_cstate_undemotion; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..6015acf 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -120,6 +120,13 @@ /* PL2 override value in mW for APL */ uint16_t tdp_pl2_override_mw; + uint8_t c1e; + uint8_t pkg_cstate_limit; + uint8_t cstate_auto_demotion; + uint8_t cstate_undemotion; + uint8_t pkg_cstate_demotion; + uint8_t pkg_cstate_undemotion; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Gerrit-Change-Number: 32050 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/up/squared: Add kernel cmdline parameters
by Philipp Deppenwiese (Code Review) 01 Jul '19

01 Jul '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33785 ) Change subject: mb/up/squared: Add kernel cmdline parameters ...................................................................... mb/up/squared: Add kernel cmdline parameters Since ttyS0 isn't used for UART0, configure ttyS4 as default Change-Id: Ia0469226253b08328807d5401c05633296e43d22 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/up/squared/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index fd03b7a..b9f5b27 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -65,6 +65,10 @@ int default 2 +config LINUX_COMMAND_LINE + string + default "console=ttyS4,115200 earlyprintk=ttyS4,115200,keep" if PAYLOAD_LINUXBOOT && UART_FOR_CONSOLE=0 + config UART_FOR_CONSOLE int default 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/33785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0469226253b08328807d5401c05633296e43d22 Gerrit-Change-Number: 33785 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/up/squared: Add kernel cmdline parameters
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33785 ) Change subject: mb/up/squared: Add kernel cmdline parameters ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/33785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0469226253b08328807d5401c05633296e43d22 Gerrit-Change-Number: 33785 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Jul 2019 11:53:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by Julien Viard de Galbert (Code Review) 01 Jul '19

01 Jul '19

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 14: > Patch Set 14: Code-Review+1 > > I tend to agree that spi probably does not belong in the function name. Right I did probably cut spi_lock_bar in two when creating the function ... that would explain the (bad) name. It should probably be lpc_ or pch_. Note that I no longer work at scaleway and didn't found enough free time to setup a build environment yet. Best Regards, Julien VdG -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 14 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Mon, 01 Jul 2019 11:33:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/pci_ops: Define pci_find_capability() just once
by Paul Menzel (Code Review) 01 Jul '19

01 Jul '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31755 ) Change subject: device/pci_ops: Define pci_find_capability() just once ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Gerrit-Change-Number: 31755 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Jul 2019 11:24:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2019