Change in ...coreboot[master]: util/docker/coreboot.org-status: Add more "nice" names for CPUs
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33930
Change subject: util/docker/coreboot.org-status: Add more "nice" names for CPUs ......................................................................
util/docker/coreboot.org-status: Add more "nice" names for CPUs
It's not perfect and we'll need to find a better place for that, but I'll look into that as part of the big board-status rework.
Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Signed-off-by: Patrick Georgi patrick@georgi.software --- M util/docker/coreboot.org-status/board-status.html/tohtml.sh 1 file changed, 72 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33930/1
diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 1992826..41de9ff 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -248,7 +248,12 @@ southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" - cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY"|grep -v CPU_MICROCODE_CBFS_NONE)" + cpu="$(sed -n \ + -e "/ select CPU_/ s, select CPU_,,p" \ + -e "/ select SOC_/ s, select SOC_,,p" \ + "$vendor_board_dir/Kconfig" | \ + grep -v "AMD_AGESA_FAMILY" | \ + grep -v CPU_MICROCODE_CBFS_NONE)" case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" @@ -302,12 +307,24 @@ AMD_SC520) cpu_nice="AMD Élan™SC520"; socket_nice="—";; + AMD_STONEYRIDGE_FP4) + cpu_nice="AMD Stoney Ridge"; + socket_nice="FP4 BGA";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; + MEDIATEK_MT8173) + cpu_nice="MediaTek MT8173"; + socket_nice="—";; + NVIDIA_TEGRA124) + cpu_nice="NVIDIA Tegra 124"; + socket_nice="—";; + NVIDIA_TEGRA210) + cpu_nice="NVIDIA Tegra 210"; + socket_nice="—";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; socket_nice="?";; @@ -317,6 +334,42 @@ TI_AM335X) cpu_nice="TI AM335X"; socket_nice="?";; + IMGTEC_PISTACHIO) + cpu_nice="Imagination Technologies Pistachio"; + socket_nice="—";; + INTEL_APOLLOLAKE) + cpu_nice="Intel® Apollo Lake"; + socket_nice="—";; + INTEL_BAYTRAIL) + cpu_nice="Intel® Bay Trail"; + socket_nice="—";; + INTEL_BRASWELL) + cpu_nice="Intel® Braswell"; + socket_nice="—";; + INTEL_BROADWELL) + cpu_nice="Intel® Broadwell"; + socket_nice="—";; + INTEL_DENVERTON_NS) + cpu_nice="Intel® Denverton-NS"; + socket_nice="—";; + INTEL_FSP_BROADWELL_DE) + cpu_nice="Intel® Broadwell-DE"; + socket_nice="—";; + INTEL_GLK) + cpu_nice="Intel® Gemini Lake"; + socket_nice="—";; + INTEL_ICELAKE) + cpu_nice="Intel® Ice Lake"; + socket_nice="—";; + INTEL_KABYLAKE) + cpu_nice="Intel® Kaby Lake"; + socket_nice="—";; + INTEL_SANDYBRIDGE) + cpu_nice="Intel® Sandy Bridge"; + socket_nice="—";; + INTEL_SKYLAKE) + cpu_nice="Intel® Skylake"; + socket_nice="—";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; socket_nice="Slot 1";; @@ -384,6 +437,24 @@ INTEL_SOCKET_MFCBGA479) cpu_nice="Intel® Mobile Celeron" socket_nice="Socket 479";; + INTEL_WHISKEYLAKE) + cpu_nice="Intel® Whiskey Lake"; + socket_nice="—";; + QC_IPQ806X) + cpu_nice="Qualcomm IPQ806x"; + socket_nice="—";; + QUALCOMM_QCS405) + cpu_nice="Qualcomm QCS405"; + socket_nice="—";; + QUALCOMM_SDM845) + cpu_nice="Qualcomm SDM845"; + socket_nice="—";; + ROCKCHIP_RK3288) + cpu_nice="Rockchip RK3288"; + socket_nice="—";; + ROCKCHIP_RK3399) + cpu_nice="Rockchip RK3399"; + socket_nice="—";; VIA_C3) cpu_nice="VIA C3™"; socket_nice="?"
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33930 )
Change subject: util/docker/coreboot.org-status: Add more "nice" names for CPUs ......................................................................
Patch Set 1: Code-Review+1
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33930 )
Change subject: util/docker/coreboot.org-status: Add more "nice" names for CPUs ......................................................................
Patch Set 1: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33930 )
Change subject: util/docker/coreboot.org-status: Add more "nice" names for CPUs ......................................................................
util/docker/coreboot.org-status: Add more "nice" names for CPUs
It's not perfect and we'll need to find a better place for that, but I'll look into that as part of the big board-status rework.
Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Signed-off-by: Patrick Georgi patrick@georgi.software Reviewed-on: https://review.coreboot.org/c/coreboot/+/33930 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Martin Roth martinroth@google.com --- M util/docker/coreboot.org-status/board-status.html/tohtml.sh 1 file changed, 72 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve
diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 1992826..41de9ff 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -248,7 +248,12 @@ southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" - cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY"|grep -v CPU_MICROCODE_CBFS_NONE)" + cpu="$(sed -n \ + -e "/ select CPU_/ s, select CPU_,,p" \ + -e "/ select SOC_/ s, select SOC_,,p" \ + "$vendor_board_dir/Kconfig" | \ + grep -v "AMD_AGESA_FAMILY" | \ + grep -v CPU_MICROCODE_CBFS_NONE)" case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" @@ -302,12 +307,24 @@ AMD_SC520) cpu_nice="AMD Élan™SC520"; socket_nice="—";; + AMD_STONEYRIDGE_FP4) + cpu_nice="AMD Stoney Ridge"; + socket_nice="FP4 BGA";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; + MEDIATEK_MT8173) + cpu_nice="MediaTek MT8173"; + socket_nice="—";; + NVIDIA_TEGRA124) + cpu_nice="NVIDIA Tegra 124"; + socket_nice="—";; + NVIDIA_TEGRA210) + cpu_nice="NVIDIA Tegra 210"; + socket_nice="—";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; socket_nice="?";; @@ -317,6 +334,42 @@ TI_AM335X) cpu_nice="TI AM335X"; socket_nice="?";; + IMGTEC_PISTACHIO) + cpu_nice="Imagination Technologies Pistachio"; + socket_nice="—";; + INTEL_APOLLOLAKE) + cpu_nice="Intel® Apollo Lake"; + socket_nice="—";; + INTEL_BAYTRAIL) + cpu_nice="Intel® Bay Trail"; + socket_nice="—";; + INTEL_BRASWELL) + cpu_nice="Intel® Braswell"; + socket_nice="—";; + INTEL_BROADWELL) + cpu_nice="Intel® Broadwell"; + socket_nice="—";; + INTEL_DENVERTON_NS) + cpu_nice="Intel® Denverton-NS"; + socket_nice="—";; + INTEL_FSP_BROADWELL_DE) + cpu_nice="Intel® Broadwell-DE"; + socket_nice="—";; + INTEL_GLK) + cpu_nice="Intel® Gemini Lake"; + socket_nice="—";; + INTEL_ICELAKE) + cpu_nice="Intel® Ice Lake"; + socket_nice="—";; + INTEL_KABYLAKE) + cpu_nice="Intel® Kaby Lake"; + socket_nice="—";; + INTEL_SANDYBRIDGE) + cpu_nice="Intel® Sandy Bridge"; + socket_nice="—";; + INTEL_SKYLAKE) + cpu_nice="Intel® Skylake"; + socket_nice="—";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; socket_nice="Slot 1";; @@ -384,6 +437,24 @@ INTEL_SOCKET_MFCBGA479) cpu_nice="Intel® Mobile Celeron" socket_nice="Socket 479";; + INTEL_WHISKEYLAKE) + cpu_nice="Intel® Whiskey Lake"; + socket_nice="—";; + QC_IPQ806X) + cpu_nice="Qualcomm IPQ806x"; + socket_nice="—";; + QUALCOMM_QCS405) + cpu_nice="Qualcomm QCS405"; + socket_nice="—";; + QUALCOMM_SDM845) + cpu_nice="Qualcomm SDM845"; + socket_nice="—";; + ROCKCHIP_RK3288) + cpu_nice="Rockchip RK3288"; + socket_nice="—";; + ROCKCHIP_RK3399) + cpu_nice="Rockchip RK3399"; + socket_nice="—";; VIA_C3) cpu_nice="VIA C3™"; socket_nice="?"
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Martin Roth (Code Review) -
Patrick Georgi (Code Review)
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Paul Menzel (Code Review)