Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33942
Change subject: cpu/amd/msr: Clarify MMIO_CONF shift value ......................................................................
cpu/amd/msr: Clarify MMIO_CONF shift value
MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field. Change it to simply 2. Otherwise its usage winds up evaluating to BusRange << (1 << 1).
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc --- M src/include/cpu/amd/msr.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33942/1
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 5d7b5e4..0f88e51 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -39,7 +39,7 @@ #define MSR_INTPEND 0xC0010055 #define MMIO_CONF_BASE 0xC0010058 #define MMIO_RANGE_EN (1 << 0) -#define MMIO_BUS_RANGE_SHIFT (1 << 1) +#define MMIO_BUS_RANGE_SHIFT 2 /* P-state Current Limit Register */ #define PS_LIM_REG 0xC0010061 /* P-state Maximum Value shift position */
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33942 )
Change subject: cpu/amd/msr: Clarify MMIO_CONF shift value ......................................................................
Patch Set 1: Code-Review+1
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33942 )
Change subject: cpu/amd/msr: Clarify MMIO_CONF shift value ......................................................................
Patch Set 1: Code-Review+2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33942 )
Change subject: cpu/amd/msr: Clarify MMIO_CONF shift value ......................................................................
Patch Set 1: Code-Review+2
Marshall Dawson has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33942 )
Change subject: cpu/amd/msr: Clarify MMIO_CONF shift value ......................................................................
cpu/amd/msr: Clarify MMIO_CONF shift value
MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field. Change it to simply 2. Otherwise its usage winds up evaluating to BusRange << (1 << 1).
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/33942 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Richard Spiegel richard.spiegel@silverbackltd.com Reviewed-by: HAOUAS Elyes ehaouas@noos.fr --- M src/include/cpu/amd/msr.h 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, approved Richard Spiegel: Looks good to me, approved
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 5d7b5e4..0f88e51 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -39,7 +39,7 @@ #define MSR_INTPEND 0xC0010055 #define MMIO_CONF_BASE 0xC0010058 #define MMIO_RANGE_EN (1 << 0) -#define MMIO_BUS_RANGE_SHIFT (1 << 1) +#define MMIO_BUS_RANGE_SHIFT 2 /* P-state Current Limit Register */ #define PS_LIM_REG 0xC0010061 /* P-state Maximum Value shift position */
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HAOUAS Elyes (Code Review) -
Marshall Dawson (Code Review)
-
Paul Menzel (Code Review)
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Richard Spiegel (Code Review)